JPH1063530A - Redundant type system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the reliability of tracking operation by a stand-by system by reducing the burden of writing processing. SOLUTION: In this redundant type system, signal buses 3 and 4 and bus buffers 5 and 6 are connected between an operating system device 1 and a stand-by system device 2 and a signal bus 7 with a shared memory 8 is connected between these bus buffers. In this case, the system is provided with the operating system device 1 closing the buffer 5 on the side of the operating system, making the shared memory an output mode at the time of starting a writing cycle and setting data of this time on the signal bus 3 on the side of an operating system, a comparing means 9 comparing data of this time on the signal bus on the side of the operating system and data of last time in the shared memory with each other, a stoppage request issuing means 11 sending a stoppage request when both of data coincide with each other and a means which finishes the writing cycle at the time of receiving a writing stoppage request, opens the bus buffer on the side of the operating system at the time of not receiving the writing stoppage request and executes a writing request to share this time data in the shared memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a redundant system used for various control systems and the like.

[0002]

2. Description of the Related Art Generally, a standby redundant system to which a standby system is applied is used for industrial control devices from the viewpoint of ensuring high reliability. This standby redundant system has an active system that is actually in charge of the control of the control target, and a standby system that is not in control of the control target while the control of the active system is being executed. And a standby system that takes over the control of the control target when the operation is stopped.

In this type of system, in order to quickly start up a standby system and take over control when the active system goes down, it is necessary to quickly take over control data for the active system. If the standby system takes over the control data after the active system goes down, there is a problem in reliability because the active system may have a failure. For this reason, a tracking operation for sending control data to the standby system during normal execution of the active system control is indispensable.

FIG. 13 is a configuration diagram of a conventional redundant system having a tracking function. In this system, an active processor 101 and a standby processor 102 are provided. These two processors 101 and 102 are connected to a bus buffer 105 and a bus buffer 105 via an active processor control signal bus 103 and a standby processor control signal bus 104, respectively.
106 is connected. These bus buffers 105,
106 are connected by a shared memory control signal bus 108 having a shared memory 107.

In such a redundant system, at the time of controlling a control target by the active processor 101, the active processor 101 opens the bus buffer 105, and then controls the control signal bus 103, the bus buffer 105, and the control signal bus 108. The control data to be tracked is written to the shared memory 107. After writing the control data, the standby processor 102 reads the control data from the shared memory 107 via the control signal bus 104, the bus buffer 106, and the control signal bus 108, and one tracking operation is completed. In addition,
When the present invention is applied to a controller that controls a control target, the controller is required to perform real-time control, and thus the tracking operation is also performed periodically and repeatedly.

FIG. 14 is a block diagram showing another conventional redundant system. This redundant system is divided into an active system 100 and a standby system 120, and the active system 10 is provided with an active system processor 111, a shared memory 112, and the like.
The standby system 120 is also provided with a standby processor 121, a shared memory 122, and the like. 113, 11
4, 123, 124 are control signal buses, 115, 116,
Reference numerals 125 and 126 denote bus buffers, and reference numeral 130 denotes an active-standby connection bus.

[0007] This redundant type system comprises
0 is provided independently for each shared memory, and when the control target is controlled by the active processor 111, the active processor 111
After opening the shared memory 122, the shared memory 122 is routed through the control signal buses 113 and 114 and the operation-standby connection bus 130.
After writing the control data to the standby processor 12
1 periodically reads the contents of the shared memory 122. Therefore, the shared memory 112 is not used while the active processor 111 controls the control target. However, when the active processor 111 is abnormal, the standby processor 121
Controls the control target, the control information is written to the shared memory 112, but at this time, the other shared memory 122 is not used.

[0008]

However, the following problems have been pointed out in the above-mentioned redundant system. (1) It can be said that the tracking operation is an extra operation from the viewpoint of the control operation that the active processors 101 and 111 originally perform. Nevertheless, the active processors 101 and 111 set a write cycle for each predetermined period for the tracking operation, and write the control data this time as new tracking data in the shared memory 107. Since it is necessary to execute the processing, there is a problem that the processing load of the system increases. (2) For the active processors 101 and 111, as the control system to be controlled becomes larger, the amount of data that must be tracked for the standby processors 102 and 121 increases, and the processing load increases. And it cannot be ignored. (3) In addition, the more frequently data is rewritten to the shared memories 107 and 122, the more factors that are affected by disturbances such as noise. As a result, erroneous data is written to the shared memories 107 and 122. In some cases, there is a problem that the standby processors 102 and 121 are affected. (4) Further, in the system shown in FIG. 14, when the control target is controlled by the active processor 111, the standby shared memory 122 is actually used, and the active shared memory 112 is used at this time. It has not been. When the control target is controlled by the standby processor 121, the active shared memory 112 is actually used, but the standby shared memory 122 is not used. Therefore,
When controlling the control target, one shared memory is not always used, so it seems to be a useless system. In this case, the operating system 110 and the standby system 120 can use the same configuration and the same parts. In order to reduce the cost and the number of types of products to be manufactured, such a system uses the same configuration and the same parts for the active system 110 and the standby system 120 and shares the active system side. It is desired to use the memory 112 and the standby-side shared memory 122 at the same time to increase utilization efficiency.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a redundant system which can reduce the load of writing tracking data. Also,
It is another object of the present invention to provide a redundant system that reduces data errors in tracking data and reduces the effect on a standby system.

[0010]

According to a first aspect of the present invention, a shared memory is connected to a control signal bus between an active device and a standby device, and the tracking data from the active device is transmitted to the shared memory. In a redundant system in which the standby system device executes a required process using the tracking data when an error occurs in the active system device, writing to the shared memory, when a write cycle by the active system device starts, Write data comparison means for comparing data with the previous tracking data written in the shared memory, and sending a write stop request to the active device when the two tracking data match. This is a redundant system that avoids the process of writing the current tracking data identical to the previous tracking data in the shared memory.

According to the first aspect of the present invention, by taking the above means, the write data comparing means compares the current tracking data with the previous tracking data written in the shared memory. In comparison, when the two tracking data match, the write cycle to the shared memory is terminated, so that the load of data write processing to the shared memory can be reduced. In the shared memory is reduced, and the effect on the standby system can be reduced.

According to a second aspect of the present invention, there is provided a write history storage means for storing tracking data during a process of writing tracking data to a shared memory by an active system, and a write cycle by the active system. At the start, the current tracking data is compared with the previous tracking data stored in the writing history storage means, and when both tracking data match, a write stop request is sent to the active system device. Writing data comparison means,
This is a redundant system that avoids the process of repeatedly writing the current tracking data identical to the previous tracking data to the shared memory.

According to a second aspect of the present invention, when the above-described means is employed, when the current tracking data and the previous tracking data are compared using the write data comparing means, the writing history Since the previous tracking data stored in the storage means is used, there is no need to perform read access processing to the shared memory, so that the data write processing can be reliably reduced, and erroneous data writing is reduced to reduce the standby system. Can be reduced.

According to a third aspect of the present invention, an operating system having an operating system device and a first control signal bus and a standby system having a standby system device and a second control signal bus are provided with a third control signal. A redundant system connected by a bus, connected to the second control signal bus, for storing current tracking data output from the active system device at the time of write processing in a write cycle; A shared memory that is held as the tracking data used by the standby system device when an error occurs, and is connected to the first control signal bus, and the current tracking data is written during the writing processing of the current tracking data to the shared memory. Write history storage means for holding the current track as history data, and a current track on the first control signal bus at the start of a write cycle by the operating system device. The data for tracking and the previous tracking data, which is the history data written in the write history storage means, are compared. When the two tracking data match, a write stop request is issued to the active system device. This is a redundant system which includes write data comparing means for sending out data and avoids the process of writing the same tracking data as the previous tracking data to the shared memory.

According to the third aspect of the present invention, by taking the above measures, the operating system and the standby system can have the same configuration, thereby reducing costs and replacing each system. This is advantageous for maintenance, etc., and when writing the tracking data to the shared memory this time, it is also written to the write history storage means at the same time, so that it is used as the previous tracking data at the time of data comparison by the write data comparison means. And a shared memory, a memory not conventionally used and a write history storage means can be used simultaneously.
In addition to having the same effects as the inventions corresponding to the first and second aspects, it is possible to reduce costs, maintain excellently, and further increase the memory use efficiency.

Further, the invention corresponding to claim 4, claim 5, and claim 6 newly compares the two tracking data with the configuration of the invention corresponding to claim 1, claim 2, and claim 3. Write data comparing means for performing, and error detecting means for detecting a data error of the current tracking data,
When the coincidence detection of both tracking data by the write data comparison means and the error detection by the error detection means are obtained,
This is a redundant system to which a write stop request issuing means for executing a write stop request to an active device is added.

Therefore, by adopting such means, the same effects as those of the inventions according to the first, second and third aspects can be obtained, and erroneous tracking data can be prevented from being written. It is possible to increase the reliability of the tracking operation by the system and to stabilize the control of the control target.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of an embodiment of the system of the present invention, the circumstances leading to the realization of the present invention will be described. Although the tracking operation is repeated periodically, the control data usually does not always change every period.
Rather, it often changes during a certain period. The reason is based on the property that the controlled object does not change various data at a speed longer than the control cycle. As a result, it can be said that in many tracking operations, the same control data is often overwritten at the same location in the shared memory. Moreover, as is clear from FIGS. 13 and 14, the direction of data transmission at the time of writing and reading data in and from the shared memories 107, 112 and 122 is fixed.
The active system and the standby system do not compete with each other and write to the same location in the shared memories 107, 112, and 122.

The present inventor has paid attention to the above-described characteristics, and has detected a case where the previous control data and the current control data are the same at the start of the control data write cycle. Therefore, by stopping the writing process of the control data, the overwriting of the shared memory is eliminated, thereby shortening the writing time and reducing the load of the writing process.

Therefore, in order to achieve such a demand, the following means are required. I. A means for ascertaining the control data that has been written to the shared memory until immediately before the start of the control data write cycle. B. Means for comparing the control data written this time with the control data written in the shared memory until immediately before and outputting the comparison result. C. Means for switching the write cycle between write execution and write non-execution at the start of the write cycle by the processor.

It is necessary to provide the following. Next, an embodiment of a system having such means will be described. (First Embodiment) FIG. 1 is a block diagram showing one embodiment of a redundant system according to the first aspect.

The system comprises an active processor 1 for actually controlling a controlled object, a standby processor 2 for controlling the controlled object in place of the active processor 1 in the event of a failure including an abnormality in the active processor 1, Connected to control signal buses 3 and 4 derived from these processors 1 and 2,
Bus buffers 5 and 6 that open and close according to access control from each processor 1 and 2, a shared memory control signal bus 7 that connects the bus buffers 5 and 6, and are connected to the shared memory control signal bus 7 to track. A shared memory 8 for storing control data is provided.

The active processor 1, while actually controlling the object to be controlled, stores address data on the control signal bus 3 before writing control data to be tracked in a write cycle for each predetermined cycle. And the current write data (control data) are set in a bit. When a write stop request signal described later is received from the outside,
Alternatively, it has a function of terminating the write cycle when receiving a write end response signal from the shared memory 8.

Further, this system includes a write data comparing means 9 for comparing the current write data on control signal bus 3 with the previous write data on control signal bus 7 at the start of a write cycle, and the write data comparing means 9. Stop request issuing means 11 for issuing a write stop request signal 10 to the active processor 1 when both write data match from the comparison result by the comparing means 9 is provided. When receiving the write stop request signal 10, the active processor 1 performs the write cycle without performing the write processing of the current write data, that is, without performing a write instruction and writing to the shared memory. To end.

Next, the operation of the above-described redundant system will be described with reference to FIG. Active processor 1
Sets the address data and the current write data on the control signal bus 3 at the start of the write cycle. At the start of the write cycle, the bus buffer 5 is closed and the shared memory 8 is in the output mode, so that the previous write data is loaded on the control signal bus 7.

In this state, the write data comparing means 9
Captures the current write data on the control signal bus 3 and the previous write data on the control signal bus 7, and compares the two write data. Here, when a match between the two write data is detected,
Upon receiving the coincidence signal, the stop request issuing means 11 issues a write stop request signal 10 and sends it to the active processor 1.

When the active processor 1 receives the write stop request signal 10, the active processor 1 terminates the current write cycle to stop writing. Due to the stoppage of writing at the end of the write cycle, there is no more write data on the control signal bus 3 this time, so that the write data is not written on the shared memory 8 and the write request by the stop request issuing means 11 The stop request is terminated.

On the other hand, if the two write data do not match, the write stop request signal 10 is not issued, so that the active processor 1 continues the write cycle, opens the bus buffer 5 and sends the address data to the control signal bus 7. And write data this time, and then execute a write command. As a result, the current write data is overwritten on the corresponding address of the shared memory 8 based on the address data on the control signal bus 7. When the writing of the write data is completed this time, a response signal is output from the shared memory 8, so that the active processor 1
The writing of the current write data is terminated based on the response signal from the shared memory 8.

Therefore, according to the above embodiment, at the start of the write cycle, the current write data is compared with the previous write data already stored in the shared memory 8, and the current write data is When the write data is the same as the previous write data, the write cycle is terminated under the write stop request. Therefore, even if the data amount to be tracked to the standby processor 2 is large, the current write data is the same as the previous write data. Since the writing process is not performed on, the writing time can be shortened and the load of the writing process can be reduced. In addition, the less the frequency of data rewriting, the less likely it is to be affected by disturbances, and the more accurate the tracking data.

It should be noted that this embodiment is not limited to the invention according to claim 1, and the following invention can be realized. That is, a control signal bus and a bus buffer are connected between the active system device and the standby system device, respectively, and a control signal bus for a shared memory having a shared memory is connected between the bus buffers and output from the active system device. In a redundant system in which the tracking data is written into the shared memory and the standby system device performs a required process using the tracking data when the active system device is abnormal, at the start of a write cycle, An operating system device that closes a side bus buffer, sets the shared memory in an output mode, and sets current tracking data on the operating system control signal bus; and a write cycle by the operating system device. At the start, the current tracking data on the operating system control signal bus and the previous data stored in the shared memory Write data comparing means for comparing the tracking data, when both the tracking data has been matched by the write data comparison means, and stop request issuing means for sending a write stop request to the operating system device,
When the active device receives a write stop request from the stop request issuing means, the write cycle is terminated without performing the write processing of the current tracking data in the shared memory, and the write stop request is not received. When the active bus buffer is controlled to open, a write command is executed and the current tracking data is stored in the shared memory, so that only when the two tracking data do not match, Since the writing process is performed and the tracking data is stored in the shared memory this time, the writing time is reduced, the load of the writing process is reduced, and the frequency of data rewriting is reduced.
Tracking data is less susceptible to disturbances,
The accuracy of the tracking data can be expected. (Second Embodiment) FIG. 3 is a block diagram showing one embodiment of a redundant system according to the second embodiment.

In this system, control signal buses 3 and 4 and bus buffers 5 and 6 are connected between the active processor 1 and the standby processor 2 as in FIG. 1, and a shared memory connecting these bus buffers 5 and 6 is provided. A shared memory 8 is connected to the control signal bus 7.

Further, this system has a shared memory 8
Separately, a write history memory 21 for holding write data on the control signal bus 3 and a current write data on the control signal bus 3 and a control signal bus 22 read from the write history memory 21 during a write cycle. Write data comparing means 23 for comparing with the previous write data, and write data comparing means 23
And a stop request issuing means 25 for issuing a write stop request signal 24 to the active processor 1 when both write data match from the result of the comparison.

Next, the operation of the redundant system having the above-described embodiment will be described with reference to FIG. The active processor 1 controls the control object, and sets the address data and the current write data on the control signal bus 3 at the start of the write cycle. At this time, the write history memory 21 is in the output mode to output the previous write data, and since the bus buffer 5 is open, the address data and the current write data are written on the shared memory control signal bus 7. There is data.

In this state, the write data comparing means 23
Captures the current write data on the control signal bus 3 and the previous write data on the control signal bus 22, and compares the two write data. Here, upon detecting a match between the two write data, the stop request issuing means 25 receives the match signal, issues a write stop request signal 24 and sends it to the active processor 1.

When the active processor 1 receives the write stop request signal 24, it immediately ends the write cycle being executed. At the end of this write cycle, there is no more write data on the control signal buses 3 and 7 this time, so that the write data is not written on the shared memory 8 and the stop request issuing means 25 Ends.

On the other hand, if the two write data do not match, the write stop request signal 24 is not issued, so that the active processor 1 continues the write cycle and executes the write instruction. Is written to the corresponding address of the shared memory 8, and the current write data on the control signal bus 7 is written to the corresponding address of the write history memory 21 to update the history data. And
When the writing of the write data is completed this time, the shared memory 8
The active processor 1 receives the response signal from the shared memory 8 and terminates the writing of the current write data.

Therefore, according to the present embodiment, a dedicated write history memory 21 is provided for referencing the previous write data, and the current write on the control signal bus 3 is started when the write cycle of the active processor 1 starts. The data and the previous write data in the write history memory 21 are compared, and when the two write data match, the writing of the current write data to the shared memory 8 is stopped, so that the number of write processes is reliably reduced. Therefore, an effect similar to that of the first embodiment can be obtained. Also, as compared with the first embodiment, a dedicated write history memory 21 is used when comparing data.
Since the previous write data is referred to, there is no need to add a read access to the shared memory 8, and the tracking operation can be greatly reduced.

This embodiment is not limited to the invention according to claim 2, but the following invention can be realized. That is, a control signal bus and a bus buffer are connected between the active device and the standby device, respectively, and a shared memory control signal bus having a shared memory is connected between the bus buffers and output from the active device. In a redundant system in which tracking data is written to the shared memory and the standby system device performs a required process using the tracking data when the active system device is abnormal, the standby system device is connected to the active system side control signal bus. Writing history storage means for storing the tracking data at the time of writing the tracking data to the shared memory by the active system device, and at the start of a write cycle, opening the active system side buffer, and The write history storage means is set to the output mode state, and the current time is output to the operating system side control signal bus. It said active system device for setting the Kkingu data, beginning write cycle by the operating system device,
Write data comparison means for comparing the current tracking data on the operating system side control signal bus with the previous tracking data stored in the write history storage means; And a stop request issuing unit for sending a write stop request to the active system device, and when the active system device receives a write stop request from the stop request issuing unit, the stop request issuing unit sends the write request to the shared memory. When the write cycle is terminated without performing the write processing of the write data and the write stop request is not received, a write command is executed and the current tracking data is stored in the shared memory and the write history storage means. With the configuration including the simultaneous storage means for storing data, in addition to the same effects as those of the first embodiment, it is possible to use only a special data comparing function in comparison with the first embodiment. Since reference to previous write data of the write history memory 21, it is not necessary to add a read access to the shared memory 8, it is possible to reduce the tracking operation significantly. (Third Embodiment) FIG. 5 is a block diagram showing an embodiment of a redundant system according to the third aspect.

In this embodiment, the operation system 30 and the standby system 4
The same components and configurations are used for the operating system 30 and the standby system 40 to reduce costs and increase maintenance efficiency.

The operating system 30 includes, specifically, an operating system processor 1, a bus buffer 31 connected to a control signal bus 3 derived from the operating system processor 1, and a control signal bus output from the bus buffer 31. A bus buffer 33 connected to the control signal bus 32 and a memory 1 which is not used in FIG.
12, the shared write / write history memory 34 for effective use of the memory 12, the current write data on the control signal bus 3 at the start of the write cycle, and the previous write data output from the write history / shared memory 34. And a stop request issuing means for issuing a write stop request signal 36 to the active processor 1 when both write data match from the comparison result of the write data comparing means 35. 37.

The standby system 40 employs exactly the same configuration as the active system 30, and includes a standby processor 2, a bus buffer 41 connected to a control signal bus 4 derived from the standby processor 2, and a bus buffer 41. It has a bus buffer 43 connected to the output control signal bus 42, a write history shared memory 44 connected to the control signal bus 42, and further includes a write data comparing means 45 and a write stop request signal 46. Is issued.

Reference numeral 48 denotes an operating-standby connection bus for connecting the bus buffers 33 and 43 to each other. The operation of the system employing such an embodiment will be described with reference to FIG.

The active processor 1 controls the control object, and sets the address data and the current write data on the control signal bus 3 at the start of the write cycle. At this time, each of the bus buffers 31, 33, 41, and 43 is in a closed state, and the shared memory / write history memory 34 is in the output mode, and the previous write data is loaded on the control signal bus 32. I have. The active-standby connection bus 48 and the control signal bus 42 have invalid data because the bus buffer is closed.

In such a state, the write data comparing means 35 takes in the current write data on the control signal bus 3 and the previous write data output from the shared memory / write history memory 34, and Perform data comparison. Here, upon detecting a match between the two write data, the stop request issuing means 37 receives the match signal, issues a write stop request signal 36, and sends it to the active processor 1.

Upon receiving write stop request signal 36, active processor 1 immediately terminates the write cycle being executed. At the end of this write cycle, there is no more data to be written this time on the control signal buses 3 and 32, so that the data to be written this time is not written in the shared memory 44 for writing history and the stop request issuing means 37 The write stop request ends.

When the two write data do not match, the write stop request signal 36 is not issued, so that the active processor 1 continues the write cycle and
When the write command is executed after the current write data is loaded on the control signal bus 42, the control signal bus 4 is opened.
2, the current write data on the control signal bus 32 is written to the corresponding address of the shared memory / write history memory 34, and the current write data on the control signal bus 32 is written to the corresponding address of the shared memory / write history memory 34. Update history data. When the writing of the write data is completed this time, a response signal is output from the shared memory 44.
Receives the response signal from the shared memory 44 and terminates the writing of the current write data.

Therefore, according to the above-described embodiment, the operating system 30 and the standby system 40 have the same configuration, thereby reducing the manufacturing cost and the operating system 3 associated with an abnormality.
0, it is very effective when replacing the standby system 40, and storage management of replacement parts is also facilitated. Further, the shared memory (FIG. 14), which has not been used during the actual control of the operating system, is used as the shared memory / write history memory 34, and the current write data and the shared memory / write on the control signal bus 3 are used. The write cycle is terminated when the previous write data of the history memory 34 is compared with the previous write data, and the memory is not wasted.
Effective utilization of the entire system can be achieved. (Fourth Embodiment) FIG. 7 is a block diagram showing an embodiment of a redundant system according to the fourth aspect.

This system is different from the configuration of FIG. 1 described in the first embodiment in that an error detecting means 51 for detecting an error in the current write data on the control signal bus 7 and a write data comparing means 9 and a write stop request issuing means 53 for outputting a write stop request signal 52 upon detection of a mismatch between the two write data based on the comparison result and upon detection of a data error by the error detection means 51.

The data error detection by the error detection means 51 is performed, for example, when the current write data is output from the active processor 1 by adding, for example, a 1-bit check bit to the current write data. To detect a data error by using a parity check method, or to set a data range that cannot be taken as write data in advance and to detect a data error when the write data enters this range, Various other well-known check methods are used.

Next, the operation of the above system will be described with reference to FIG. The active processor 1 sets the address data and the current write data on the control signal bus 3 at the start of the write cycle. At this time, since the bus buffer 5 is closed and the shared memory 8 is in the output mode, the previous write data is loaded on the control signal bus 7.

Therefore, the write data comparing means 9 takes in the current write data on the control signal bus 3 and the previous write data on the control signal bus 7 and compares the two write data.
Here, upon detecting a match between the two write data, the stop request issuing means 53 receives the match signal S1 and issues a write stop request signal 52, sends it out to the active processor 1, and sets the write cycle being executed to To end.

On the other hand, when the two write data do not match, the write stop request signal 52 is not issued, so that the active processor 1 opens the bus buffer 5 and stores the address data and the current write data on the control signal bus 7. After that, the write instruction is executed to try to write the current write data to the corresponding address of the shared memory 8. It is determined whether there is an error in the current write data. If there is an error, an error detection signal S2 is output, and a write stop request signal 52 is sent to the active processor 1 via the stop request issuing means 53. , End the current write cycle.

Therefore, according to the above-described embodiment, the current write data is compared with the previous write data, and when the two write data match, the write cycle is terminated. Can be reduced, and the processing load can be reduced. When writing the current write data to the shared memory 8, for example, if an error occurs in the current write data somewhere on the transmission path, the writing of the erroneous write data is stopped. There is no need to worry about giving data, and the control operation by the standby system can be stabilized.

This embodiment is not limited to the invention according to claim 4, and the following invention can be realized. That is, a control signal bus and a bus buffer are connected between the active system device and the standby system device, respectively, and a control signal bus for a shared memory having a shared memory is connected between the bus buffers and output from the active system device. In a redundant system in which the tracking data is written into the shared memory and the standby system device performs a required process using the tracking data when the active system device is abnormal, at the start of a write cycle, An operating system device that closes a side bus buffer, sets the shared memory in an output mode, and sets current tracking data on the operating system control signal bus; and a write cycle by the operating system device. At the start, the current tracking data on the operating system control signal bus and the previous data stored in the shared memory A write data comparing means for comparing the data with the racking data; and an error for detecting a data error of the current tracking data to be written into the shared memory when the two tracking data do not match from the comparison result of the write data comparing means. A write stop request for sending a write stop request to the active device when a match between both tracking data is detected from the comparison result of the detection means and the write data comparison means and an error is detected by the error detection means; Issuing means and, when the active system device receives a write stop request from the stop request issuing means, terminates the write cycle without performing the current tracking data writing process in the shared memory; When the request is not received, after opening the active system bus buffer, a write instruction is executed, and the tracking data is written to the shared memory this time. With this configuration, the writing process is performed only when the two tracking data do not match, and the current tracking data is stored in the shared memory. By reducing the processing load and the data rewriting frequency, the tracking data is less likely to be affected by disturbance, and the accuracy of the tracking data can be improved. Further, when writing the current write data to the shared memory 8, for example, if an error occurs in the current write data somewhere on the transmission path, the writing of the erroneous write data is stopped.
There is no fear of giving erroneous data to the standby system, and the control operation by the standby system can be stabilized. (Fifth Embodiment) FIG. 9 is a block diagram showing an embodiment of the system according to the fifth aspect.

This embodiment is different from the configuration of FIG. 3 described in the second embodiment in that an error detecting means 51 for detecting an error in the current write data on the control signal bus 7 and a write data A write stop request issuing unit 53 that outputs a write stop request signal 52 when a mismatch between both write data is detected based on the comparison result of the comparison unit 9 and when a data error is detected by the error detection unit 51 is added. .

Also in this system, the active processor 1 sets the address data and the current write data on the control signal bus 3 at the start of the write cycle. At this time, the write history memory 21 is in the output mode to output the previous write data, and since the bus buffer 5 is open, the address data and the current write data are written on the shared memory control signal bus 7. There is data.

In this state, the write data comparing means 23
Compares the current write data on the control signal bus 3 with the previous write data on the control signal bus 22, and when the two write data match, the stop request issuing means 53 sends the write stop request signal 52 The write cycle is sent to the active processor 1 to end the write cycle being executed.

On the other hand, when the two write data do not match, the active processor 1 outputs a write command and the control signal bus 7
The above-mentioned current write data is stored in the shared memory 8 and the current write data on the control signal bus 3 is written into the write history memory 21. The current write data is written on the control signal bus 7 before this write. When the bit of the embedded data is set, the error detection means 51
Determines whether there is an error in the current write data, outputs an error detection signal S2 if there is an error, and sends a write stop request signal 5 to the active processor 1 via the stop request issuing means 53.
2 to end the current write cycle.

Therefore, according to this embodiment, since the previous write data in the dedicated write history memory 21 is referred to when comparing both write data, the previous write can be performed without adding read access to the shared memory 8. Since the data can be referred to and the write processing of the shared memory 8 is stopped when the two write data match, the write processing of the tracking data is reduced, and the processing load can be reduced.
Also, if an error occurs in the current write data somewhere on the transmission path, the writing of the incorrect write data is stopped, so that there is no need to worry about giving the standby system erroneous data, and the control operation by the standby system is stabilized. Can be secured.

This embodiment is not limited to the invention according to claim 5, and the following invention can be realized. That is, a control signal bus and a bus buffer are connected between the active device and the standby device, respectively, and a shared memory control signal bus having a shared memory is connected between the bus buffers and output from the active device. In a redundant system in which tracking data is written to the shared memory and the standby system device performs a required process using the tracking data when the active system device is abnormal, the standby system device is connected to the active system side control signal bus. Writing history storage means for storing the tracking data at the time of writing the tracking data to the shared memory by the active system device, and at the start of a write cycle, opening the active system side buffer, and The write history storage means is set to the output mode state, and the current time is output to the operating system side control signal bus. It said active system device for setting the Kkingu data, beginning write cycle by the operating system device,
Write data comparing means for comparing the current tracking data on the operating system side control signal bus with the previous tracking data stored in the write history storage means; and a write data comparing means existing on the shared memory control signal bus. Error detection means for detecting a data error in the tracking data this time, and when the coincidence detection of the two tracking data and the error detection by the error detection means are performed based on the comparison result of the write data comparison means, A write stop request issuing unit for sending a write stop request; and when the operating system device receives a write stop request from the stop request issuing unit, the write processing of the current tracking data is not performed in the shared memory. When the write cycle is completed and the write stop request is not received, a write instruction is executed to store the current tracking data with the shared memory. With the configuration including means for storing in the write history storage means, in addition to the same effect as in the second embodiment, a dedicated write history can be used when comparing data as compared with the second embodiment. Since the previous write data in the memory 21 is referred to, there is no need to add a read access to the shared memory 8, and the tracking operation can be greatly reduced. (Sixth Embodiment) FIG. 11 is a block diagram showing an embodiment of the system according to the sixth aspect.

In this embodiment, an error detecting means 51 for detecting an error in currently written data on the control signal bus 42 is newly provided as an operating system in addition to the configuration of FIG. And a write stop request issuing means 53 for outputting a write stop request signal 52 when a match between the two write data is detected based on the comparison result of the write data comparing means 35 and when a data error is detected by the error detecting means 51. Configuration.

In the standby system 40, the error detecting means 5
1 'and a write stop request issuing means 53' are provided. Next, the operation of the above system will be described with reference to FIG.
This will be described with reference to FIG.

The active processor 1 sets the address data and the current write data on the control signal bus 3 at the start of the write cycle. At this time, each bus buffer 3
1, 33, 41 and 43 are in a closed state,
Also, the shared memory / write history memory 34 is in the output mode, and the previous write data is loaded on the control signal bus 32.

In such a state, the write data comparison means 35 compares the current write data on the control signal bus 3 with the previous write data on the control signal bus 32, and when both data match, a stop request is issued. The issuing unit 53 issues a write stop request signal 52.

Here, upon receiving the write stop request signal 52, the active processor 1 immediately ends the write cycle being executed. At the end of this write cycle, there is no more current write data on the control signal buses 3 and 32, so that the current write data is not written in the write history / shared memory 44 and the write by the stop request issuing means 53 is performed. The stop request is terminated.

On the other hand, when the two data do not match, when the active processor 1 opens the buffers 31, 33, 43,
The error detecting means 51 determines whether there is an error in the current write data, and if there is an error, outputs an error detection signal S2,
A write stop request signal 52 is sent to the active processor 1 via the stop request issuing means 53, and the write cycle being executed is terminated.

When the standby processor 2 becomes active and an error is detected using the error detecting means 51 ', a write stop request signal 52' is output via a stop request issuing means 53 '. It is sent to the standby processor 2.

Therefore, according to this embodiment, in addition to the same effects as in the third embodiment, if an error occurs in the current write data somewhere on the transmission path, the erroneous write data is written. Is stopped, there is no need to worry about giving erroneous data to the standby system, and the control operation by the standby system can be stabilized.

[0069]

As described above, according to the present invention, the following various effects can be obtained. According to the first aspect of the present invention, at the start of a write cycle, when the current write data is the same as the previous write data, the write cycle is terminated under a write stop request. In the same case as described above, it is not necessary to perform the writing process. As a result, the writing time can be reduced and the load of the writing process can be reduced. Further, if the frequency of rewriting data is reduced, the influence of disturbance is reduced, and the reliability of the tracking operation by the standby system can be improved.

According to the second aspect of the present invention, a dedicated write history memory is provided, and when the current write data matches the previous write data in the write history memory at the start of the write cycle of the active processor, the shared memory is used. Since the writing of the current write data to the memory is stopped, the write processing can be surely reduced, and the same effect as in the first embodiment can be obtained. Further, as compared with the first embodiment, since the previous write data in the dedicated write history memory is referred to when comparing data, there is no need to add read access to the shared memory, and the tracking operation is greatly reduced. be able to.

According to the third aspect of the present invention, the operating system and the standby system can have the same configuration, so that the manufacturing cost can be reduced and maintenance such as replacement of the operating system and the standby system in the event of an abnormality can be smoothly performed. In addition, storage management of equipment is also facilitated. Conventionally, in the system of FIG. 14, one of the shared memories is not used. However, in the present invention, by using it as a write history memory, previously written data can be taken out, and the memory is wasted. And the system can be used effectively.

Further, in the inventions of claims 4 to 6, in addition to the same effects as those of claims 1 to 3,
By providing the error detecting means, when an error occurs in the write data, the writing of the erroneous write data is stopped, so that there is no need to worry about giving erroneous data to the standby system, and the control operation by the standby system is stabilized. Can be secured.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a redundant system according to claim 1;

FIG. 2 is a time chart for explaining the operation of the system shown in FIG. 1;

FIG. 3 is a configuration diagram showing an embodiment of a redundant system according to claim 2;

FIG. 4 is a time chart for explaining the operation of the system shown in FIG. 3;

FIG. 5 is a configuration diagram showing an embodiment of a redundant system according to claim 3;

FIG. 6 is a time chart for explaining the operation of the system shown in FIG. 5;

FIG. 7 is a configuration diagram showing an embodiment of a redundant system according to claim 4.

FIG. 8 is a time chart for explaining the operation of the system shown in FIG. 7;

FIG. 9 is a configuration diagram showing an embodiment of a redundant system according to claim 5;

FIG. 10 is a time chart for explaining the operation of the system shown in FIG. 9;

FIG. 11 is a configuration diagram showing an embodiment of a redundant system according to claim 6;

FIG. 12 is a time chart for explaining the operation of the system shown in FIG. 11;

FIG. 13 is a configuration diagram of a conventional redundant system.

FIG. 14 is a configuration diagram of another conventional redundant system.

[Explanation of symbols]

1 ... active processor, 2 ... standby processor, 3,
4, 7: control signal bus, 8: shared memory, 9, 23, 3
5, 45... Write data comparing means, 11, 25, 37, 4
7 ... stop request issuing means, 21 ... write history memory, 30 ...
Active system, 40 standby system, 34 shared memory and write history memory, 44 shared write history and shared memory, 51 error detecting means, 53 stop request issuing means.

Claims (6)

[Claims] 1. A shared memory is connected to a control signal bus between an active system device and a standby system device, and tracking data output from the active system device is written into the shared memory. In the redundant system in which the standby system device performs a required process using the tracking data at the time, at the start of the write cycle by the active system device, the current tracking data and the last time written to the shared memory are written. A write data comparison unit that compares the tracking data with the active data and sends a write stop request to the active system device when the two tracking data match each other; A redundant system for avoiding redundant writing processing to said shared memory. 2. A shared memory is connected to a control signal bus between an active system device and a standby system device, and current tracking data output from the active system device is written into the shared memory. In a redundant system in which the standby system device performs required processing using the tracking data when an abnormality occurs, the tracking data is stored when the active system device writes the tracking data to the shared memory. At the start of a write cycle by the active system device, a comparison is made between the current tracking data and the previous tracking data stored in the write history storage unit, and when the two tracking data match. Writing data comparison means for sending a writing stop request to the active system device. A redundant type system for avoiding an overlapping writing process of the same tracking data as the current data to the shared memory. 3. A redundant system in which an operating system having an operating system device and a first control signal bus and a standby system having a standby system device and a second control signal bus are connected by a third control signal bus. In the type system, the current control unit is connected to the second control signal bus, and stores current tracking data output from the active device during a write process in a write cycle. And a shared memory connected to the first control signal bus and used to hold the current tracking data as history data when writing the current tracking data to the shared memory. At the start of a write cycle by the operating system device, the current tracking data on the first control signal bus and the write data Write data comparing means for comparing with the previous tracking data, which is the history data written in the history storage means, and sending a write stop request to the active device when the two tracking data match; And a redundant system for avoiding an overlapping writing process of the current tracking data identical to the previous tracking data to the shared memory. 4. A shared memory is connected to a control signal bus between an active device and a standby device, and tracking data from the active device is written into the shared memory. In a redundant system in which a standby device performs a required process using the tracking data, at the start of a write cycle by the active device, the current tracking data and the previous tracking data written in the shared memory are used. Write data comparing means for comparing the data with the write data, and error detection for detecting a data error of the current tracking data to be written into the shared memory when the two tracking data do not match from the comparison result of the write data comparing means. Means for detecting the coincidence of both tracking data and the error detecting means from the comparison result of the write data comparing means. And a write stop request issuing means for sending a write stop request to the operating system device when an error is detected by a stage. 5. A shared memory is connected to a control signal bus between an active system device and a standby system device, and writes tracking data from the active system device to the shared memory. In a redundant system in which a standby device performs a required process using the tracking data, a write history storing the tracking data when the active device writes the tracking data in the shared memory. Storage means; write data comparison means for comparing the current tracking data with the previous tracking data stored in the write history storage means at the start of a write cycle by the active system device; When the two tracking data do not match from the comparison result of the means, the current tracking data to be written to the shared memory. An error detecting means for detecting a data error of the data, and a write stop request to the active device when the coincidence of both tracking data is detected from the comparison result of the write data comparing means and the error is detected by the error detecting means. And a write stop request issuing means for sending out. 6. A redundant system in which an operating system having an operating system device and a first control signal bus and a standby system having a standby system device and a second control signal bus are connected by a third control signal bus. In the type system, the current control unit is connected to the second control signal bus, and stores current tracking data output from the active device during a write process in a write cycle. And a shared memory connected to the first control signal bus and used to hold the current tracking data as history data when writing the current tracking data to the shared memory. At the start of a write cycle by the operating system device, the current tracking data on the first control signal bus and the write data A write data comparing means for comparing with the previous tracking data which is history data written in the history storage means; and when the two tracking data do not match based on a comparison result of the write data comparing means, the shared memory Error detecting means for detecting a data error of the current tracking data to be written in the active device; and detecting the coincidence of the two tracking data from the comparison result of the write data comparing means and detecting the error by the error detecting means. And a write stop request issuing means for sending a write stop request to the redundant system.