JPH1055270A - Digital processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve test efficiency by fetching data added to an input port or an external terminal while the logic of a test mode specifying terminal is active and setting the value of a program counter. SOLUTION: A boot strap control part 2 responds to reset cancellation and executes a boot strap function. A sequencer part 3 generates the control signals of respective parts required in a boot strap period and a normal operation period. Then, the setting means 4b of an instruction memory (I-RAM) control part 4 generates the read-write address of an I-RAM 5 from the value of the program counter(PC) 4a, and when a 'specified instruction' is added to the input port 7 when TEST is active in the boot strap period, the value of the PC 4a is set by the contents of the 'prescribed field' of the instruction. Thus, access to the specified area of the I-RAM 5 is freely performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital processing device, and more particularly to a digital processing device having an instruction memory.

[0002]

2. Description of the Related Art Microprogram control includes an input / output unit,
It realizes the "control unit" of various digital processing devices consisting of four basic function blocks, a storage unit, an operation unit, and a control unit. The operation of the storage unit and the operation unit is broken down into basic operations (micro operation) Then, a microinstruction obtained by combining one or more m-step operations is stored in a memory (instruction memory) called "control storage", and a series of microinstructions (microprogram) necessary for executing the instruction is sequentially read out. It is to control.

The control memory is a ROM (read only memor)
y) using “fixed control memory” and RAM (random access)
memory) or the like. Note that there is also a "semi-fixed control storage" using an EPROM, but is ignored since it has no direct relation to the present invention. FIG.
(A) is a conceptual diagram of fixed control storage. I-ROM (instruction RO) mounted on digital processing device
A microprogram is written in M) in advance. Suitable for mass production, but cannot change or modify programs. On the other hand, FIG. 7B is a conceptual diagram of the rewritable control storage, and an external storage device or the like stores information before the start of control.
Load the microprogram into RAM (instruction RAM). Although the overhead of program loading cannot be denied, it is particularly used for products in the development stage and products with a small number of products because of the feature that the program can be changed or modified freely.

FIG. 8 is an address map of the I-RAM. Immediately after startup, all addresses are empty, but in response to the reset release of the digital processing device, the automatic loading function of the microprogram (so-called bootstrap function) works, and the microinstructions are sequentially read from an external storage device or the like. The program counter (PC) is sequentially incremented and written to the address indicated by the PC. At the same time as the end of the bootstrap period, the PC
Is returned to a predetermined value (generally 0), and the microprogram is started from that value.

[0005]

By the way, in a digital processing device having a bootstrap function, the completion test of the digital processing device is performed by loading a test program into an instruction memory using the bootstrap function. The bootstrap function is a fixed address method in which the start address (indicated by A in FIG. 8) of the instruction memory is a load start address and the last address (indicated by X in FIG. 8) is a load end address. Therefore, for example, even if it is desired to load a test program into specific areas B to C shown by hatching in FIG.
There is a problem that unnecessary processing such as writing dummy data to b is required, and the efficiency of the test is low.

It is conceivable to extend the bootstrap function so that it can be loaded to an arbitrary address. However, such an extended function is used only once at the time of completion inspection. It can not be said. Accordingly, it is an object of the present invention to enable a test program to be loaded into a specific area of an instruction memory without writing dummy data, thereby improving test efficiency.

[0007]

According to the present invention, in order to achieve the above object, in response to a reset release, an external microinstruction is sequentially read, and the program counter is incremented by a value indicated by the program counter. In the digital processing device for sequentially writing to the address of the instruction memory, while the logic of the test mode designation terminal is active, the data applied to the input port or the external terminal is taken in, and the value of the program counter is set according to the contents of the data. It is characterized by comprising a setting means for performing the setting.

According to the present invention, when the test mode is designated, the value of the program counter can be externally operated, and the access to a specific area of the instruction memory can be freely performed. Therefore, the test program can be loaded into a specific area without writing dummy data, or the start address of the program can be set freely, so that the test can be performed more efficiently.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a digital processing device according to the present invention.
processor). First, the configuration will be described. In FIG. 1, 1 is a DSP, Din is a 32-bit data input terminal, Dout is a 32-bit data output terminal, RSTX is a negative logic reset input terminal,
TEST is a positive logic test mode designation terminal. Although various terminals are provided in addition to these, they are omitted to avoid complicating the drawing.

The DSP 1 includes a bootstrap control unit 2, a sequencer unit 3, an I-RAM control unit 4, an I-RAM
(Instruction memory) 5, address operation unit 6,
An input port 7, an output port 8, a register file 9, an arithmetic unit 10, internal buses 11 and 12, and the like are mounted.
The detailed functions of the main parts are as follows. [Bootstrap control unit 2] The one that executes the "bootstrap function" described at the beginning in response to the reset release, that is, when the logic of RSTX transitions from L level to H level, the sequencer unit 3 and I-RAM Control unit 4
To read a microinstruction (for example, one read from an external storage device) applied to the input port 7 and increment the program counter (PC) 4a of the I-RAM 4 as indicated by the PC 4a. The operation of writing to the address of the I-RAM 5 is repeatedly executed until the value of the PC 4a reaches a predetermined value. [Sequencer section 3] This section generates a control signal for each section necessary for a bootstrap period and a normal operation period. [I-RAM control unit 4] From the value of PC4a, I-RAM5
When a "specific instruction" is added to the input port 7 during the bootstrap period and TEST is active, the value of the PC 4a is stored in the contents of the "predetermined field" of the instruction. Is the point having the setting means 4b for setting

FIG. 2 shows two types of formats that exemplify a specific instruction, both of which are 32-bit instructions. The upper three bits (bits 31 to 29) are an identification field. If "001" is set in this identification field, the instruction is a specific instruction. Note that the value of the identification field is not limited to “001”. Any value can be used as long as it can be distinguished from other instructions of the DSP1.

Bit 28 is an auxiliary identification field, bits 11 to hit 0 are an address field as the predetermined field, and when the auxiliary identification field is "0", the content of the address field is a write address of the I-RAM 5. When the auxiliary identification field is "1", it indicates that the content of the address field is the start address of the microprogram. Hereinafter, the instruction when the auxiliary identification field is “0” is referred to as “write address setting instruction SET”, and the instruction when the auxiliary identification field is “1” is referred to as “program start address setting instruction STP”.

Therefore, the setting means 4b of the I-RAM control unit 4 decodes at least the instruction applied to the input port 7 during the bootstrap period and when TEST is active, and the value of the identification field of the instruction is changed. In the case of "001", the value of the PC 4a is replaced with the value of the address field of the instruction, and if the value of the auxiliary identification field of the instruction is "0", the I-RAM 4 is set to the write mode, or If the value of the auxiliary identification field is "1", the I-RAM 4 is set to the read mode. [I-RAM5] A rewritable control storage for storing a microprogram having a capacity of 4K words (1 word = 64 bits). An address corresponding to the value of the PC 4a of the I-RAM control unit 4 is read / written. Note that I-RA
The read of M5 is performed in word units, but the write is performed with a 32-bit width in accordance with the internal buses 11 and 12 (2
Write one word in each time)
The number of bits of C4a is 12 bits, and the number of bits at the time of writing is 13 bits obtained by adding 1 bit to LSB.

Next, the operation will be described. FIG. 3 is a timing chart immediately after the start of the bootstrap. In this timing chart, SCLK is a system clock,
RSTX is a reset signal, PC is the value of PC4a, IMR
EX is a read enable signal of the I-RAM 5, IMWE
X is a write enable signal of the I-RAM 5, BOOT is a signal indicating a bootstrap period, DB-31: 0 is a signal of an internal data bus, DI-32: 0 is data of an input port 7 (external input), and WI is an input. Port 7 write signal (external input), FFIX is input port 7 full signal (external output), I-PORT is input port 7 register data, IFE is input port 7 empty signal, IFRX
Is a register read signal of the input port 7.

As described above, the bootstrap is started in response to the reset release (rising of RSTX). In the figure, t1 is the time point of reset release, and this t1
After one cycle of SCLK, BOOT becomes active to start bootstrap. When bootstrap is started, first, the PC is returned to the initial value (000 + 0),
The first input data D1 (lower half of one word) is written to the address of the I-RAM 5 indicated by the initial value,
Next, the LSB of the PC is set to 1 and the next input data D2 (upper half of one word) is written at the same address (000 + 1). That is, by switching the LSB of the PC, the 32-bit data is written twice to form a one-word instruction.

FIG. 4 is a timing chart of the end of the bootstrap and the start of the program. At this timing, the IRLT is the output latch of the I-RAM 5,
R is an instruction register. The other signals are common to FIG. The end of the bootstrap period is when the value of PC reaches the maximum value (FFF + 1). In the figure, t2 is the end point, at which time BOOT goes low. When BOOT goes low, the LSB of the PC is ignored. That is, counting is performed with 12 bits, and the value is from 000 to FFF. PC = 000 indicates the start address of the program, and the program is started from the instruction at the address 0 of the I-RAM 5.

The above-described operations of bootstrap start, end, and program start are not different from those of the prior art. However, in this embodiment, TEST is activated at the start of bootstrap and a specific instruction is input to the input port 7. By adding one (write address setting instruction SET), the value of the PC can be freely changed, and the bootstrap start address of the I-RAM 5 can be arbitrarily set.

FIG. 5 is a timing chart. In this figure, "SET A" is an instruction meaning that address A is set in the PC as a write address.
That is, the "SET A" instruction applied to the input port 7 is decoded by the setting means 4b of the I-RAM control unit 4, and the value of the PC is replaced by the value (A) of the address field.

Therefore, according to this timing chart, TEST is activated during the bootstrap period, and the write address setting instruction S
Since the start address of the bootstrap can be freely changed by a simple procedure only by giving an ET, for example, when a test program is loaded into a specific area (areas B to C in FIG. 8) of the I-RAM 5 By setting "B" in the address field of the write address setting instruction SET, writing of dummy data to the other areas a and b becomes unnecessary, and the efficiency of the test can be improved.

Further, in this embodiment, at the end of the bootstrap period, TEST is activated and another one of the specific instructions (program start address setting instruction STP) is applied to the input port 7 to start the program. PC value can be set freely. FIG. 6 is a timing chart. In this figure, "STP A"
Uses the address A as the program start address
This is an instruction that means to set That is, the "STP A" instruction applied to the input port 7 is decoded by the setting means 4b of the I-RAM control unit 4, and the value of the PC is replaced with the value (A) of the address field.

Therefore, according to this timing chart, the TEST is activated at the end of the bootstrap period, and the start address of the program can be freely set by a simple procedure of only applying the program start address setting instruction STP to the input port 7. For example, when executing a test program loaded in a specific area (areas B to C in FIG. 8) of the I-RAM 5, "B" is added to the address field of the program start address setting instruction STP. By setting, the test program can be executed immediately without using a jump instruction or the like, and the efficiency of the test can be improved.

In the above embodiment, a specific instruction such as a write address setting instruction or a program start address setting instruction is added to the input port 7, but the present invention is not limited to this. In short, when the test mode is specified at the start or end of the bootstrap period, any data may be taken from outside the DSP 1. For example, an appropriate external terminal (a dedicated terminal or a shared terminal may be used). May be fetched through the Internet.

[0023]

According to the present invention, when the test mode is designated,
The value of the program counter can be freely manipulated from outside.
For this reason, access to a specific area of the instruction memory becomes free. For example, a test program can be loaded into a specific area without writing dummy data, and a start address of a program can be freely set. The test efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of one embodiment.

FIG. 2 is a format diagram of a specific instruction of one embodiment.

FIG. 3 is a timing chart (start of a bootstrap period) of one embodiment.

FIG. 4 is a timing chart (end of a bootstrap period and program start) in one embodiment.

FIG. 5 is a timing chart (write address setting instruction) of one embodiment.

FIG. 6 is a timing chart (program start address setting instruction) of one embodiment.

FIG. 7 is a conceptual diagram of fixed control storage and rewritable control storage.

FIG. 8 is a memory map diagram of an instruction memory.

[Explanation of symbols]

 TEST: Test mode designation terminal 4a: Program counter 4b: Setting means 5: I-RAM (instruction memory) 7: Input port

Claims (1)

[Claims] In a digital processing device, a micro-instruction is sequentially read in response to a reset release, and sequentially written to an instruction memory address indicated by the program counter while incrementing a program counter. A digital processing device comprising: a set unit for fetching data applied to an input port or an external terminal while a logic of a designated terminal is active, and setting a value of the program counter in accordance with the content of the data.