JPH10500254A - 半導体基板中に埋め込まれた酸化物層を備えた低転位密度構造の製造プロセス - Google Patents
半導体基板中に埋め込まれた酸化物層を備えた低転位密度構造の製造プロセスInfo
- Publication number
- JPH10500254A JPH10500254A JP7529423A JP52942395A JPH10500254A JP H10500254 A JPH10500254 A JP H10500254A JP 7529423 A JP7529423 A JP 7529423A JP 52942395 A JP52942395 A JP 52942395A JP H10500254 A JPH10500254 A JP H10500254A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- epitaxy
- substrate
- dislocation density
- dislocations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 230000008569 process Effects 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 100
- 238000000407 epitaxy Methods 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 25
- 239000001301 oxygen Substances 0.000 claims abstract description 17
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- -1 oxygen ions Chemical class 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 230000007547 defect Effects 0.000 description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 11
- 239000013078 crystal Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000009467 reduction Effects 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000003993 interaction Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000013386 optimize process Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.低転位密度のエピタキシャル構造を製造するためのプロセスであって、前記 構造は、半導体材料基板(4)中に酸化物層(6)を有し、 埋め込み酸化物層を形成するために、基板の表面(3)を通して基板(4)中 に酸素イオン(2)を少なくとも1回注入するプロセスと、 半導体材料の融点以下の温度において、基板に対して、状態を良好にするため の、少なくとも一回の第1熱処理を行うプロセスと、 基板の表面上に半導体材料層(14)のエピタキシーを行うプロセスと、 不安定なエネルギー配置にある、この構造中の大部分の転位を消滅させるため の、基板の半導体材料およびエピタキシー層の半導体材料の融点以下の温度で、 第2熱処理を施すプロセスとを有し、 少なくとも第1熱処理または第2熱処理のいずれかにおいては、第2熱処理の 間に再結合する転位(8)を解放するために、イオン注入において形成された酸 化物の凝集物の全てを、実質的に消滅させることを可能とする温度で、熱処理が されることを特徴とする、低転位密度のエピタキシャル構造を製造するためのプ ロセス。 2.前記半導体材料がシリコンであることを特徴とする請求項1記載のプロセス 。 3.前記第1熱処理の温度が800から1405℃の間で行われることを特徴と する請求項2記載のプロセス。 4.請求項2または3記載のプロセスであって、第2熱処理の温度が、800か ら1405℃の間であることを特徴とするプロセス。 5.請求項1から4までのいずれかに記載されたプロセスであって、転位密度を 105個/cm2以下にするために、第1熱処理または第2熱処理のうち、少なく とも一方は、1200℃以上望ましくは約1300℃で行われることを特徴とす るプロセス。 6.請求項1から5までのいずれかに記載されたプロセスであって、半導体材料 のエピタキシー層は0.05μm以上の厚さであることを特徴とするプロセス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR94/06061 | 1994-05-18 | ||
FR9406061A FR2720189B1 (fr) | 1994-05-18 | 1994-05-18 | Procédé de réalisation d'une structure à faible taux de dislocations comprenant une couche d'oxyde enterrée dans un substrat semi-conducteur. |
PCT/FR1995/000644 WO1995031825A1 (fr) | 1994-05-18 | 1995-05-17 | Procede de realisation d'une structure a faible taux de dislocations comprenant une couche d'oxyde enterree dans un subsrat semi-conducteur |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10500254A true JPH10500254A (ja) | 1998-01-06 |
Family
ID=9463308
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7529423A Ceased JPH10500254A (ja) | 1994-05-18 | 1995-05-17 | 半導体基板中に埋め込まれた酸化物層を備えた低転位密度構造の製造プロセス |
Country Status (6)
Country | Link |
---|---|
US (1) | US6110802A (ja) |
EP (1) | EP0760162B1 (ja) |
JP (1) | JPH10500254A (ja) |
DE (1) | DE69518418T2 (ja) |
FR (1) | FR2720189B1 (ja) |
WO (1) | WO1995031825A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999039380A1 (fr) * | 1998-02-02 | 1999-08-05 | Nippon Steel Corporation | Substrat soi et procede de fabrication dudit substrat |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10284431A (ja) * | 1997-04-11 | 1998-10-23 | Sharp Corp | Soi基板の製造方法 |
US6291313B1 (en) | 1997-05-12 | 2001-09-18 | Silicon Genesis Corporation | Method and device for controlled cleaving process |
US20070122997A1 (en) | 1998-02-19 | 2007-05-31 | Silicon Genesis Corporation | Controlled process and resulting device |
US6033974A (en) | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6159824A (en) | 1997-05-12 | 2000-12-12 | Silicon Genesis Corporation | Silicon-on-silicon wafer bonding process using a thin film blister-separation method |
US6548382B1 (en) | 1997-07-18 | 2003-04-15 | Silicon Genesis Corporation | Gettering technique for wafers made using a controlled cleaving process |
US6291326B1 (en) | 1998-06-23 | 2001-09-18 | Silicon Genesis Corporation | Pre-semiconductor process implant and post-process film separation |
US6500732B1 (en) | 1999-08-10 | 2002-12-31 | Silicon Genesis Corporation | Cleaving process to fabricate multilayered substrates using low implantation doses |
US6263941B1 (en) | 1999-08-10 | 2001-07-24 | Silicon Genesis Corporation | Nozzle for cleaving substrates |
JP2001297989A (ja) * | 2000-04-14 | 2001-10-26 | Mitsubishi Electric Corp | 半導体基板及びその製造方法並びに半導体装置及びその製造方法 |
US8507361B2 (en) * | 2000-11-27 | 2013-08-13 | Soitec | Fabrication of substrates with a useful layer of monocrystalline semiconductor material |
US8187377B2 (en) | 2002-10-04 | 2012-05-29 | Silicon Genesis Corporation | Non-contact etch annealing of strained layers |
CN100342492C (zh) * | 2003-03-14 | 2007-10-10 | 中国科学院上海微系统与信息技术研究所 | 一种厚膜绝缘层上硅材料的制备方法 |
US8993410B2 (en) | 2006-09-08 | 2015-03-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
US8293619B2 (en) | 2008-08-28 | 2012-10-23 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled propagation |
US7811900B2 (en) | 2006-09-08 | 2010-10-12 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a thick layer transfer process |
US9362439B2 (en) | 2008-05-07 | 2016-06-07 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
US8330126B2 (en) | 2008-08-25 | 2012-12-11 | Silicon Genesis Corporation | Race track configuration and method for wafering silicon solar substrates |
US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
US8329557B2 (en) | 2009-05-13 | 2012-12-11 | Silicon Genesis Corporation | Techniques for forming thin films by implantation with reduced channeling |
CN102790007A (zh) * | 2012-07-24 | 2012-11-21 | 沈阳硅基科技有限公司 | 一种厚膜tm-soi硅片的制备方法 |
WO2014020387A1 (en) | 2012-07-31 | 2014-02-06 | Soitec | Methods of forming semiconductor structures including mems devices and integrated circuits on opposing sides of substrates, and related structures and devices |
-
1994
- 1994-05-18 FR FR9406061A patent/FR2720189B1/fr not_active Expired - Fee Related
-
1995
- 1995-05-17 US US08/737,812 patent/US6110802A/en not_active Expired - Fee Related
- 1995-05-17 DE DE69518418T patent/DE69518418T2/de not_active Expired - Fee Related
- 1995-05-17 JP JP7529423A patent/JPH10500254A/ja not_active Ceased
- 1995-05-17 EP EP95920950A patent/EP0760162B1/fr not_active Expired - Lifetime
- 1995-05-17 WO PCT/FR1995/000644 patent/WO1995031825A1/fr active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999039380A1 (fr) * | 1998-02-02 | 1999-08-05 | Nippon Steel Corporation | Substrat soi et procede de fabrication dudit substrat |
US6617034B1 (en) | 1998-02-02 | 2003-09-09 | Nippon Steel Corporation | SOI substrate and method for production thereof |
Also Published As
Publication number | Publication date |
---|---|
FR2720189A1 (fr) | 1995-11-24 |
DE69518418T2 (de) | 2001-03-15 |
EP0760162B1 (fr) | 2000-08-16 |
DE69518418D1 (de) | 2000-09-21 |
EP0760162A1 (fr) | 1997-03-05 |
US6110802A (en) | 2000-08-29 |
WO1995031825A1 (fr) | 1995-11-23 |
FR2720189B1 (fr) | 1996-08-30 |
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