JPH10341015A - Horizontal dmos field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To materialize a DMOSFET capable of reducing on-resistance, by equipping this field effect transistor with a wiring layer which covers the whole of a substrate connected to a source electrode, and a second interlayer insulating film which insulates a drain electrode and the wiring layer. SOLUTION: Since a source electrode 11 is connected to a wiring layer which covers a DMOSFET at large, the wiring resistance of the source electrode 11 decreases sharply. Accordingly, there is no voltage drop caused by the wiring resistance of the source electrode 11, so the voltage between the gate and the source does not change, and the on-resistance does not change, either. Generally, in the case of such structure that the source electrode 11 and the drain electrode 13 cross each other, the point of field concentration shifts to the drain side, and the breakdown strength drops. In this case, the resistance value of a drift channel is reduced by raising the concentration of impurities of the drift layer 15. As a result, the on-resistance is reduced by forming a second interlayer insulating film 25 at the DMOSFET, and connecting the wiring layer 26 with the source electrode 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lateral DMOSFET (Double-diffused Meta-
l Oxide Semiconductor Field Effect Transistor: Hereinafter, simply referred to as DMOSFET. ), And particularly to a DMOSFET with reduced on-resistance.

[0002]

2. Description of the Related Art A conventional DMOSFET is used for a semiconductor relay and has a low output capacitance as compared with a vertical DMOSFET, so that a high-speed operation becomes possible.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor relay using a DMOSFET. In FIG. 4, 1 is an LED, 2 is a voltage output type photodiode array, 3 is a resistor, 4 and 5 are DMOSFETs, 100a and 100
b is an input terminal, and 101a and 101b are output terminals.

The input terminal 1 on the primary side of the semiconductor relay
00a and 100b are connected to the anode and cathode of LED1, respectively.

On the other hand, on the secondary side of the semiconductor relay, one end of the voltage output type diode array 2 is
The other end of the voltage output type diode array 2 is connected to the gates of the OSFETs 4 and 5, the other end of the resistor 3, the DMOSFE
Connected to the sources of T4 and T5.

The drains of the DMOSFETs 4 and 5 are connected to output terminals 101a and 101b, respectively.

Here, the operation of the semiconductor relay shown in FIG. 4 will be briefly described. When a voltage is applied to the input terminals 100a and 100b, the LED 1 emits light, and a voltage is generated at both ends of the voltage output type diode array 2.

Since this voltage is applied between the gate and source of the DMOSFETs 4 and 5, the DMOSFETs 4 and 5
Becomes "on", and the output terminals 101a and 101b are connected.

The resistor 3 is for discharging the electric charge stored in the gate electrodes of the DMOSFETs 4 and 5.

As a result, the connection between the output terminals 101a and 101b on the secondary side can be controlled by applying a voltage to the input terminals 100a and 100b on the primary side, so that the relay operates as a relay.

FIG. 5 is a configuration block diagram showing an example of an application example in which such a semiconductor relay is used as an input switch circuit of a recorder.

In FIG. 5, 6 is a resistance thermometer, 7 is a thermocouple, 8 is a common mode voltage, 9 is a semiconductor relay array,
10 is an input stage circuit, and 102 is an output signal. Also, 9
And 10 are components constituting the recorder 50.

The resistance thermometer 6, the thermocouple 7, and the common mode voltage 8 are connected to a semiconductor relay array 9. The output of the semiconductor relay array 9 is input to an input stage circuit 10, and the input stage circuit 10 outputs an output signal 102. Output.

Here, the operation of the application example shown in FIG. 5 will be briefly described. Signals from the resistance temperature detector 6, the thermocouple 7, and the common mode voltage 8 are appropriately selected in the semiconductor relay array 9 and input to the input stage circuit 10.

The input stage circuit 10 performs an amplification process as necessary, converts the data into digital data, and outputs it as an output signal 102 to a higher-level control circuit or the like (not shown).

As a result, by using a semiconductor relay as an input switch circuit of a device such as a recorder, it is possible to realize a highly reliable recorder and the like and to reduce its size.

FIG. 6 is a pattern diagram of a general DMOSFET. In FIG.
Is a gate electrode, and 13 is a drain electrode. The source electrode 11 is arranged so as to surround the drain electrode 13 with the gate electrode 12 interposed therebetween.

FIG. 7 is a sectional view showing a section taken along the line AA 'in FIG. 11-13 In 7 are denoted by the same reference numerals as in FIG. 6, 14 p ^- forms of substrate, 1
5 is a drift layer in which an n-type impurity is diffused, 16 is a p-type impurity diffusion layer, 17 is a p ^{+ -type} impurity diffusion layer, 18 is an n ^{+ -type} impurity diffusion layer, 19 is a gate oxide film, 20 is an oxide separation film, 21 is an interlayer insulating film.

Here, p or n is described.
⁺ "Or" ^- "subscript represents the difference in the diffusion concentration of impurities diffused," ⁺ "is denser diffusion concentration who take," ^- "it is a thin diffusion concentration who arrive.

For example, for the p-type impurity,
The diffusion concentration of the p-type impurity is increased in the order of the p-type impurity diffusion layer 16 and the p ^{+ -type} impurity diffusion layer 17. For the n-type impurity, the drift layer 15 and the n ^{+ -type} impurity diffusion layer 18
, The diffusion concentration of the n-type impurity increases.

A drift layer 15 and a p-type impurity diffusion layer 16 are formed on the substrate 14 so as to surround the drift layer 15.

On the p-type impurity diffusion layer 16, p ⁺ and n
^{The + type} impurity is double-diffused to form ap ^{+ type} impurity diffusion layer 17 and an n ^{+ type} impurity diffusion layer 18, respectively. Similarly, an n ^{+ -type} impurity is diffused also over drift layer 15 so that n ⁺
Formed impurity diffusion layer 18 is formed.

The substrate 14, the p-type impurity diffusion layer 16 and the n ⁺
A gate oxide film 19 is formed astride the p-type impurity diffusion layer 18, and an oxide isolation film 2 is formed in other portions to insulate the substrate 14, the drift layer 15 and the p-type impurity diffusion layer 16.
0 is formed.

After the gate electrode 12 is formed on the gate oxide film 19 and a part of the adjacent oxide separation film 20, the substrate 1
4, an interlayer insulating film 21 is formed.

In the formed interlayer insulating film 21, the p ^{+ -type} impurity diffusion layer 17 and the n ^+
The portion adjacent to the ^{+ type} impurity diffusion layer 18 and the portion of the n ^{+ type} impurity diffusion layer 18 on the drift layer 15 are removed by etching or the like, and the source electrode 11 and the drain electrode 13 are formed in the respective portions.

Here, the DMOSFE shown in FIGS.
The operation of T will be described. However, description of the basic operation is omitted.

The drift layer 15 reduces the electric field concentration between the gate electrode 12 and the drain electrode 13 and
A predetermined breakdown voltage is ensured by arranging 3 so as to surround it with source electrode 11.

Also, the on-resistance “Ro” of the DMOSFET
n ”is the resistance of the drift layer 15 if the resistance of the wiring or the like is ignored, and“ Rch ”is the resistance of the channel generated immediately below the gate electrode 12 by applying a voltage to the gate electrode 12. Then, Ron = Rd + Rch (1)

That is, in order to reduce the on-resistance of the DMOSFET, the depth of the gate electrode 12 in FIG.
"Rch" by increasing the width of
To reduce. Alternatively, if the voltage applied to the gate electrode 12 is increased, “Rch” can be reduced.

[0030]

However, the gate electrode 1
In order to increase the voltage applied to the voltage output type diode array 2, the number of diodes constituting the voltage output type diode array 2 shown in FIG.
However, problems such as an increase in the chip area and an increase in cost and a restriction on the package size occur.

Further, even if the width of the gate electrode is increased, there is a limit on a chip having a limited area, resulting in a pattern as shown in FIG.

FIG. 8 is a pattern diagram showing an example of a pattern of a conventional DMOSFET. Reference numerals 11 to 13 are denoted by the same reference numerals as in FIG.

Here, when the pattern shown in FIG. 8 is taken, the area which can be used for the wiring of the source electrode 11 and the drain electrode 13 is small, and the wiring resistance of the source electrode 11 and the drain electrode 13 is reduced. It cannot be ignored.

For example, FIG. 9 shows the DMMOS shown in FIGS. 6 and 7.
FIG. 4 is a circuit diagram showing an equivalent circuit in an ON state of ET. In FIG. 9, reference numerals 22a, 22b, 22c, 22d, and 22e denote wiring resistances of the drain electrode 13, 23a, 23b, 23c,
23d, 23e and 23f are the on-state resistances of the DMOSFET itself, 24a, 24b, 24c and 24d are the wiring resistances of the source electrode 11, 103 is the source terminal, and 104 is the drain terminal.

The source terminal 103 is connected to one end of the resistor 23a and one end of the wiring resistor 24a, and the other end of the resistor 23a is connected to one end of the wiring resistor 22a.

The other end of the wiring resistor 22a is connected to the resistor 23b and one end of the wiring resistor 22b, and the other end of the wiring resistor 24a is connected to the other end of the resistor 23b and one end of the wiring resistor 24b.

Similarly, wiring resistances 22b to 22d and wiring resistances 24b to 24d are connected in series, respectively, and resistors 23c to 23e are connected between the connection points.

The other end of the wiring resistor 24d is connected to a resistor 23f.
And the other end of the resistor 23f is connected to a wiring resistor 22d.
Is connected to one end of the wiring resistor 22e, and the other end of the wiring resistor 22e is connected to the drain terminal 104. Further, a plurality of equivalent circuits having the same connection relationship are connected in parallel.

In this state, when a large drain current flows through the DMOSFET, the voltage actually applied to the source electrode 11 decreases due to the voltage drop due to the wiring resistance of the source electrode 11, and the gate-source voltage decreases.

FIG. 10 is a characteristic curve showing the relationship between the gate-source voltage and the on-resistance "Ron". As can be seen from FIG. 10, when the gate-source voltage decreases, the on-resistance "Ron" sharply increases. There is a problem that said.

That is, FIG. 11 is a characteristic curve diagram showing the characteristics of the load voltage / load current of the semiconductor relay using the DMOSFET. As shown in FIG. Is about 5Ω, but there is a problem that the on-resistance is reduced to about 7Ω due to the influence of the wiring resistance of the source electrode 11 at the point indicated by “b” in FIG. Therefore, an object to be solved by the present invention is to provide a DMOS capable of reducing on-resistance.
It is to implement FET.

[0042]

According to a first aspect of the present invention, there is provided a lateral DMOS field-effect transistor having a substrate, a drift layer formed on the substrate, and a p-type impurity diffusion layer. A layer; an n ^{+ -type} impurity diffusion layer formed on the drift layer and the p-type impurity diffusion layer; a p ^{+ -type} impurity diffusion layer formed on the p-type impurity diffusion layer; An impurity diffusion layer and the n
A gate oxide film formed over the ⁺ -type impurity diffusion layer, an oxide isolation film insulating the substrate, the drift layer and the p-type impurity diffusion layer, and a gate electrode formed on the gate oxide film; A drain electrode formed on the n ^{+ -type} impurity diffusion layer formed on the drift layer;
A source electrode formed in a portion where the p ^{+ -type} impurity diffusion layer and the n ^{+ -type} impurity diffusion layer are adjacent to each other; a first interlayer insulating film that insulates the gate electrode from the source electrode;
A wiring layer connected to the source electrode and covering the entire substrate; and a second interlayer insulating film for insulating the drain electrode from the wiring layer.

In order to achieve such an object, the second aspect of the present invention is characterized in that in the first aspect of the present invention, the impurity diffusion concentration of the drift layer is set high.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration sectional view showing a section of an embodiment of a DMOSFET according to the present invention.

In FIG. 1, reference numerals 11 to 21 denote the same reference numerals as in the conventional example shown in FIG. 7, 25 denotes an interlayer insulating film, and 26 denotes a wiring layer made of aluminum.

The basic structure is almost the same as that of the conventional example shown in FIG. 7 except that the interlayer insulating film 25 is formed on the DMOSFET shown in FIG.
Is removed by etching or the like, and the entire wiring layer 2 is removed.
6 is the point formed.

Here, the operation of the embodiment shown in FIG. 1 will be described. Since the source electrode 11 is connected to the wiring layer 26 that covers the entire DMOSFET, the wiring resistance of the source electrode 11 is drastically reduced as compared with the conventional example.

Therefore, the equivalent circuit in the ON state of the DMOSFET shown in FIG. 9 is as shown in FIG. 2, and the wiring resistances 24a to 24d of the source electrode 11 shown in FIG. 9 can be neglected.

Therefore, even if a large drain current flows through the DMOSFET shown in FIG. 1, there is no voltage drop due to the wiring resistance of the source electrode 11, so that the gate-source voltage does not change and the on-resistance does not change.

However, in general, when the source electrode 11 and the drain electrode 13 cross each other as shown in FIG.
The point of the electric field concentration affecting the breakdown phenomenon in the SFET shifts to the drain side, and the breakdown voltage decreases.

For example, the drift channel length indicated by “a” in FIG. 1 is “15 μm”, and the surface concentration of the drift layer 15 is “4 × 10” which is a general value of a conventional DMOSFET.
¹⁵ [1 / cm ³ ] ”.

In this case, the breakdown voltage of the conventional example shown in FIG.
On the other hand, when the structure is the same as the embodiment shown in FIG. 1, the breakdown voltage is reduced to "190 V".

On the other hand, FIG. 3 is a characteristic curve diagram showing the relationship between the surface concentration of the drift layer 15 and the breakdown voltage. From FIG. 3, the surface concentration of the drift layer 15 is set to "4.6 to 5.0 × 10 ¹⁵ [1 / c
m ³ ] ", the structure shown in FIG.
A withstand voltage of 0 V "or more can be obtained.

As described above, by increasing the surface concentration of the drift layer 15, that is, the impurity diffusion concentration of the drift layer 15, the resistance value “Rd” of the drift channel is increased.
Is smaller by about 9 to 12% than that of the conventional example, so that the on-resistance “Ron” is also reduced from the equation (1).

As a result, the second interlayer insulating film 25 is formed on the DMOSFET, and the wiring layer 26 formed on the second interlayer insulating film 25 and the source electrode 11 are connected.
Since the wiring resistance of the source electrode 11 is negligible, the on-resistance is reduced. Further, an increase in on-resistance when a large drain current flows is eliminated.

Furthermore, by increasing the impurity diffusion concentration of the drift layer 15 as compared with the conventional example, the resistance value “Rd” of the drift channel becomes smaller, so that the on-resistance is also reduced.

[0057]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. DMOSFET
By forming a second interlayer insulating film on the substrate and connecting the wiring layer formed on the second interlayer insulating film to the source electrode, the on-resistance can be reduced because the wiring resistance of the source electrode can be ignored. A simple DMOSFET can be realized.

Further, since the wiring resistance of the source electrode can be ignored, the on-resistance does not increase when a large drain current flows, and the resistance value of the drift channel can be reduced by increasing the impurity diffusion concentration of the drift layer as compared with the conventional example. It becomes smaller and the on-resistance also decreases.

[Brief description of the drawings]

FIG. 1 is a configuration sectional view showing a section of an embodiment of a DMOSFET according to the present invention.

FIG. 2 is an equivalent circuit of a DMOSFET in an ON state.

FIG. 3 is a characteristic curve diagram showing a relationship between a surface concentration of a drift layer and a withstand voltage.

FIG. 4 is a circuit diagram showing an example of a conventional semiconductor relay using a DMOSFET.

FIG. 5 is a block diagram showing an example of an application example in which a semiconductor relay is used as an input switch circuit of a recorder.

FIG. 6 is a pattern diagram of a DMOSFET.

FIG. 7 is a cross-sectional view showing a cross section taken along line A-A ′.

FIG. 8 is a pattern diagram showing an example of a pattern of a conventional DMOSFET.

FIG. 9 is a circuit diagram showing an equivalent circuit of a DMOSFET in an ON state.

FIG. 10 is a characteristic curve diagram showing a relationship between a gate-source voltage and an on-resistance.

FIG. 11 is a characteristic curve diagram showing a load voltage / load current characteristic of a semiconductor relay using a DMOSFET.

[Explanation of symbols]

1 LED 2 Voltage output type photodiode array 3, 23a, 23b, 23c, 23d, 23e, 23f
Resistance 4,5 DMOSFET 6 RTD 7 Thermocouple 8 Common mode voltage 9 Semiconductor relay array 10 Input stage circuit 11 Source electrode 12 Gate electrode 13 Drain electrode 14 Substrate 15 Drift layer 16 P-type impurity diffusion layer 17 p ^{+ -type} impurity Diffusion layer 18 n ^{+ -type} impurity diffusion layer 19 Gate oxide film 20 Oxidation separation film 21, 25 Interlayer insulation film 22a, 22b, 22c, 22d, 22e, 24a, 2
4b, 24c, 24d Wiring resistance 26 Wiring layer 50 Recorder 100a, 100b Input terminal 101a, 101b Output terminal 102 Output signal 103 Source terminal 104 Drain terminal

Claims (2)

[Claims] 1. A lateral DMOS field-effect transistor, comprising: a substrate; a drift layer and a p-type impurity diffusion layer formed on the substrate; and an n-layer formed on the drift layer and the p-type impurity diffusion layer.
^{A + -type} impurity diffusion layer; a p ^{+ -type} impurity diffusion layer formed on the p-type impurity diffusion layer; and a gate formed over the substrate, the p-type impurity diffusion layer, and the n ^{+ -type} impurity diffusion layer. An oxide film; an oxide isolation film insulating the substrate, the drift layer and the p-type impurity diffusion layer; a gate electrode formed on the gate oxide film; and the n ^{+ -type} formed on the drift layer. A drain electrode formed on the impurity diffusion layer, a source electrode formed at a portion where the p ^{+ -type} impurity diffusion layer and the n ^{+ -type} impurity diffusion layer are adjacent to each other, and insulating the gate electrode and the source electrode A horizontal type comprising: a first interlayer insulating film; a wiring layer connected to the source electrode and covering the entire substrate; and a second interlayer insulating film for insulating the drain electrode from the wiring layer. DMOS electricity Effect transistor. 2. A lateral DMOS field effect transistor according to claim 1, wherein the impurity diffusion concentration of said drift layer is set high.