JP4473837B2 - Transistor - Google Patents

Description

  The present invention relates to a transistor.

Excellent operating characteristics and reliability in applications such as personal computer bus switches, mobile phone antenna changeover switches, and automatic test equipment (ATE) changeover switches used in IC and LSI test processes There is a need for compatible switching elements. As such a switching element, a photo relay or an analog switch using a field effect transistor is expected instead of a conventional mechanical contact type relay. Also for power MOSFETs, there is a need for elements with high breakdown voltage, capable of high-speed operation, and low on-resistance (Ron).
In order to meet these expectations, the present inventors have invented a switching element using a lateral field effect transistor having a low on-resistance and a small output capacitance (Cout) (for example, Patent Document 1).

For example, in the case of the transistor disclosed in FIG. 33 or FIG. 34 of Patent Document 1, the n ⁺ -type source region 5 and the p ⁺ -type contact layer 6 are provided equidistant from the drain 7. That is, the source region 5 and the contact layer 6 are in contact with the base layer 4 at a common linear boundary line. However, when the contact layer 6 is aligned with the source region 5 in this way, the effective channel width is narrowed. That is, the path of the electron current flowing from the base layer 4 to the source in the on state is limited to the n ⁺ type source region 5 only. Since the portion where the p ⁺ -type contact layer 6 is in contact with the base layer 4 does not act as an outflow path for electrons, the effective channel width is narrowed, which is disadvantageous from the viewpoint of reducing the on-resistance. Become.
JP 20046731 A

  The present invention provides a transistor capable of ensuring a switching breakdown voltage while suppressing an increase in on-resistance.

According to one aspect of the present invention, a source unit having a plurality of first conductivity type source regions and a plurality of second conductivity type base contact regions arranged alternately, a first conductivity type drain unit, A semiconductor layer provided between the source portion and the drain portion and having a second conductivity type base region in contact with the source region and the base contact region; and a gate provided in contact with the base region A gate electrode provided opposite to the base region with the gate insulating film interposed between the insulating film and the base region, wherein the source region and the base contact region are arranged alternately A transistor is characterized in that the ratio of the channel length to the width of the source region is 1.5 or more .

  According to the present invention, it is possible to provide a transistor capable of ensuring a switching breakdown voltage while suppressing an increase in on-resistance.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a schematic view illustrating a transistor according to the first embodiment of the invention. 1A is a cross-sectional view of a transistor, and FIG. 1B is a schematic view illustrating a planar arrangement of a semiconductor portion of the transistor.

  The transistor of this embodiment is formed in a so-called SOI (Silicon On Insulator) layer. That is, the SOI layer 20 made of silicon is provided on the support substrate 2 made of silicon via the buried insulating layer 3 made of silicon oxide. The SOI layer 20 is provided with a source part S, a drain part D, and a p-type base region 4 and a drift region 18 provided therebetween.

The source portion S has a structure in which n ⁺ type source regions 5 and p ⁺ type base contact regions 6 are alternately arranged in a direction perpendicular to the channel. These n ⁺ type source region 5 and p ⁺ type base contact region 6 are both connected to the source electrode. The p ⁺ type base contact region 6 has a role of fixing the potential of the p type base region 4 to the source potential.
On the other hand, the drain part D consists of an n ⁺ -type drain region 7.

The p-type base region 4 is a semiconductor region that forms a channel. The drift region 18 is made of p ^- type or n ^- type silicon having a higher resistance than the p-type base region 4 and has a role of increasing the breakdown voltage of the transistor.

  A gate insulating film 14 is provided on the p-type base region 4, and a gate electrode 15 is provided thereon. A conductive layer 16 made of tungsten silicide (WSi) or the like is appropriately provided on the gate electrode 15 in order to reduce connection resistance with a gate wiring (not shown).

In this transistor, when a predetermined voltage is applied to the gate electrode 15, a channel is formed in the p-type base region 4 and the transistor is turned on, so that a current can flow between the source region 5 and the drain region 7. By providing the p ⁺ -type base contact region 6, the potential of the p-type base region 4 is fixed to the source potential in the off state, and the parasitic bipolar effect during the off state and switching can be suppressed to improve the breakdown voltage of the transistor.

In this embodiment, the p ⁺ type base contact region 6 is offset from the n ⁺ type source region 5. That is, as shown in FIG. 1B, the p ⁺ type base contact region 6 is provided farther from the n ⁺ type source region 5 by the offset amount Loff (p ⁺ ) when viewed from the drain portion D. The junction between the n ⁺ -type source region 5 and the p-type base region 4 is provided closer to the n ⁺ -type drain region 7 than the junction between the p ⁺ -type base contact region 6 and the p-type base region 4. In this way, an effective channel area can be ensured in the on state, and a high switching breakdown voltage can be realized while suppressing an increase in the on resistance.

When the p ⁺ -type base contact region 6 is formed so as to protrude toward the base region 4 rather than the source region etching, the effective channel width decreases. As a result, there arises a problem that the on-resistance increases.

That is, there is a problem that the p ⁺ -type contact layer 6 tends to protrude in the direction of the base region 4 rather than the source region 5 when attempting to form the structure of Patent Document 1 using a normal formation method. FIG. 13 is a schematic diagram showing this transistor obtained when formed using a normal method.

That is, when the structure shown in FIG. 33 or FIG. 34 of Patent Document 1 is to be formed, those skilled in the art usually use the polysilicon pattern of the gate electrode 15 formed on the SOI layer 20 as a mask, and form an n-type impurity. And p-type impurities are selectively introduced into the source part, respectively, so that the n ⁺ -type source region 5 and the p ⁺ -type contact layer 6 are formed. In such a case, it is common to use arsenic (As) as the n-type impurity and boron (B) as the p-type impurity.

However, in silicon, boron diffuses more easily than arsenic. Therefore, when these impurities are introduced using the same gate mask, boron diffuses a longer distance in the lateral direction, that is, below the gate mask. As a result, as shown in FIG. 13, the p ⁺ type contact layer 6 protrudes toward the base layer 4 rather than the n ⁺ type source region 5.

When the p ⁺ -type contact layer 6 protrudes in this way, the effective channel width further decreases. That is, in the portion where the p ⁺ -type contact layer 6 protrudes, an inversion channel is not formed even when an electric field is applied from the gate electrode 15. For this reason, the area X represented by hatching in FIG. 13 becomes an invalid area as an electron flow path, and there arises a problem that the on-resistance further increases.

In contrast, in the transistor of this embodiment illustrated in FIG. 1, the effective channel width and channel region are increased by retracting the p ⁺ type base contact region 6 with respect to the n ⁺ type source region 5. The on-resistance can be lowered.

On the other hand, in this embodiment, the switching breakdown voltage can be improved by reducing the width W (Ns) of the source region 5. That is, even when the offset amount Loff (p ⁺ ) of the base contact region 6 is zero, the switching tolerance of the transistor can be greatly improved by reducing the width W (Ns) of the source region 5.
Hereinafter, these effects will be described in order.

2A and 2B are schematic views illustrating the in-plane distribution of the impurity concentration of the SOI layer in the comparative example and the transistor of this embodiment, respectively, by contour lines. In these schematic diagrams, the higher the n-type impurity concentration, the lighter the p-type impurity concentration.
FIG. 13A shows the distribution of impurity concentration when an n-type impurity and a p-type impurity are introduced using a polysilicon gate as a common mask as described above with reference to FIG. It can be seen that the p-type impurity in the p ⁺ -type base contact region 6 protrudes toward the base region 4 and narrows the junction between the n ⁺ -type source region 5 and the base region 4. As the p ⁺ -type base contact region 6 protrudes in this manner, the effective channel width is narrowed and the on-resistance is increased.

On the other hand, FIG. 2B shows the impurity concentration distribution in the transistor of this embodiment. In the present embodiment, the p ⁺ type base contact region 6 is formed so as to recede from the n ⁺ type source region 5. As a result, as shown in FIG. 2B, the n-type impurity in the n ⁺ -type source region 5 extends to the junction between the p ⁺ -type base contact region 6 and the p-type base region 4 and is effective. The channel width can be significantly increased.

  FIGS. 3A and 3B are schematic views showing density distributions of electron currents in the comparative example illustrated in FIG. 2 and the transistor of this embodiment illustrated in FIG. 1, respectively. That is, these schematic diagrams represent the density distribution in the plane of the electron current in the ON state by contour lines. In these schematic diagrams, the higher the density of the electron current, the higher the density, and the lower the density, the lighter the density.

In the case of the transistor of the comparative example shown in FIG. 3A, the p ⁺ type base contact region 6 protrudes and extends to the front of the n ⁺ type source region 5, so that it flows from the base region 4 to the source region 5. It can be seen that the flow path of the electron current is greatly narrowed. By narrowing the flow path of the electron current in this way, the average density of the electron current in the p-type base region 4 is lowered, and the on-resistance is increased. This problem becomes more serious as the pattern width W (Ns) (see FIG. 1B) of the n ⁺ -type source region 5 is narrowed.

On the other hand, in the transistor of this embodiment, the electrons flowing into the n ⁺ type source region 5 are offset as shown in FIG. 3B by offsetting the p ⁺ type base contact region 6 away from the p ⁺ type base contact region 6. The flow path of the current is greatly expanded, and a high electron current density is obtained over the entire p-type base region 4. As a result, the on-resistance can be greatly reduced. In the transistor of the comparative example shown in FIG. 3A, when the drain voltage Vd is 0.35 volts, the drain current Id is only 0.063 amperes, but in the present embodiment shown in FIG. In the transistor, the drain current Id rose to 0.1045 amps when the drain voltage Vd was 0.35 volts. That is, the on-resistance can be reduced by about 40% compared to the comparative example.

In the case of a transistor formed only by the n ⁺ type source region 5 without providing the p ⁺ type base contact region 6 in the source part S, the drain current Id was 0.1064 amperes under the same conditions. In other words, according to the present embodiment, p ⁺ -type base if the contact region 6 is not provided and it is possible to reduce the on-resistance to almost the same level, the on-resistance due to the provision of the p ⁺ -type base contact region 6 It is possible to almost eliminate the rise. That is, according to the present embodiment, the parasitic bipolar effect in the off state and the switching state can be suppressed by providing the p ⁺ type base contact region 6 while suppressing an increase in the on-resistance, and a high switching breakdown voltage can be obtained.

FIG. 4 is a graph illustrating the turn-off characteristics of the transistor of this embodiment. That is, the horizontal axis in the figure represents time, and the vertical axis represents current and voltage.
The current of approximately zero volts and 0.1 amperes in the on state decreases rapidly in about 0.8 microseconds with the transistor turning off, and transitions to zero amperes at 20 volts. This is a turn-off speed equivalent to that of a field effect transistor in which the p ⁺ -type base contact region 6 is not provided in the source portion S. In other words, according to the present embodiment, the p ⁺ type base contact region 6 is provided to fix the potential of the p type base region 4, and the on-resistance is greatly reduced to reduce the CR (capacitance / resistance) product. Thus, the switching speed can be greatly improved.

Here, in order to manufacture the transistor of this embodiment, for example, as described later with reference to FIG. 8, the p ⁺ type base contact region 6 and the n ⁺ type source region 5 are formed using different masks. Good. That is, when the p ⁺ -type base contact region 6 is formed, a p-type impurity is selectively introduced into the source portion S using a mask having a narrow opening along the channel direction (left-right direction in FIG. 1). On the other hand, when the n ⁺ -type source region 5 is formed, if an n-type impurity is selectively introduced into the source portion S using a mask having a wide opening along the channel direction (left-right direction in FIG. 1), As shown in FIG. 1, a structure in which the p ⁺ type base contact region 6 is provided farther than the n ⁺ type source region 5 when viewed from the drain portion D can be formed.

More specifically, for example, the p ⁺ -type contact region 6 is formed by introducing a p-type impurity into the source portion S using a mask having a first opening, and then the mask is etched to widen the opening. Then, the n ⁺ type source region 5 may be formed by introducing an n type impurity.

Alternatively, after an n ⁺ -type source region 5 is formed by introducing an n-type impurity into the source portion S using a mask having a first opening, an opening is formed by forming another mask on the mask. After narrowing, the p ⁺ -type base contact region 6 may be formed by introducing a p-type impurity.

Hereinafter, the structural parameters of the transistor of this embodiment will be described more quantitatively.
FIG. 5 is a graph illustrating the relationship between the offset amount of the p ⁺ type base contact region 6 and the CR product of the transistor. That is, the horizontal axis of the figure represents the offset amount Loff (p ⁺ ), and the vertical axis represents the CR product (pF · Ω).
In the legend of the figure, “standard” means that the gate length (the length in the horizontal direction in FIGS. 1A and 1B) is 1 micrometer and the gate width (FIG. 1B). The length in the vertical direction) is 2700 micrometers. “Low C” represents a structure in which the gate length is 1 micrometer and the gate width is 1400 micrometers in order to reduce the capacitance. On the other hand, “low R” represents a structure in which the gate length is 1 micrometer and the gate width is 5500 micrometers in order to reduce resistance.

Further, “(0.5: 0.5)” attached to these is the case where the width W (p ⁺ ) (see FIG. 1B) of the p ⁺ -type base contact region 6 is 0.5 micrometers, and n The width W (Ns) of the ⁺ type source region 5 (see FIG. 1B) also represents 0.5 micrometer. Similarly, “(1:19)” means that the width W (p ⁺ ) of the p ⁺ -type base contact region 6 (see FIG. 1B) is 1 micrometer and the width W of the n ⁺ -type source region 5. (Ns) (see FIG. 1B) represents 19 micrometers. That is, “(0.5: 0.5)” corresponds to a structure in which the p ⁺ type base contact region 6 and the n ⁺ type source region 5 are miniaturized in the width direction.

  As can be seen from FIG. 5, when the offset amount Loff (p +) of the p + -type base contact region 6 increases from zero to 0.15 micrometers, the base contact region 6 and the source region 5 are made finer structures (“(0 .5: 0.5) "), the CR product decreases rapidly. This is presumably due to a decrease in on-resistance (Ron) as described above with reference to FIGS. As the offset amount Loff (p +) further increases, the CR product continues to decrease slightly, but the change is gradual. That is, from the viewpoint of CR product or on-resistance, it can be seen that the offset amount Loff (p +) should be 0.15 micrometers or more in a miniaturized structure.

FIG. 6 is a graph illustrating the relationship between the offset amount of the p ⁺ -type base contact region 6 and the switching tolerance of the transistor. That is, the horizontal axis of the figure represents the offset amount Loff (p +), and the vertical axis represents the switching tolerance (volt). The legend in FIG. 6 is the same as that described above with reference to FIG.
From the viewpoint of switching withstand capability, the miniaturized structure ("(0.5: 0.5)") significantly improves the switching tolerance compared to the non-miniaturized structure ("(1:19)"). I understand that. Further, regarding the miniaturized structure, when the offset amount is zero (Loff (p ⁺ ) = 0) and the offset amount is about 0.15 to 0.3 micrometers, it is about 70 than the structure that is not miniaturized. It can be seen that there is a percentage improvement.

That is, when the results shown in FIGS. 5 and 6 are summarized, the width W (p ⁺ ) of the base contact region 6 and the width W (Ns) of the source region 5 are reduced, and the offset amount is 0.15 micrometers or more. If it is 0.3 micrometer or less, a sufficiently high level of switching withstand can be obtained while effectively reducing the on-resistance and suppressing an increase in CR product.

Next, the effect of reducing the width of the source region 5 will be further described.
In the case of an element having a rated drain voltage of 20 volts, a switching withstand capacity of 20 volts or more is required for actual use. When the pattern width W (Ns) of the source region 5 is large, breakdown occurs due to a bipolar parasitic effect during switching. In order to avoid this destruction, it is necessary to secure a contact to the source electrode of the p-type base region 4 and the distance between the contacts to the base region 4, that is, the width W (Ns) of the pattern of the source region 5. Need to be narrowed.

FIG. 7 shows the relationship between the pattern width of the source region 5 and the switching breakdown voltage at the time of switching of a 20-volt element in the transistor of this embodiment. That is, the horizontal axis of the figure represents the width W (Ns) of the source region 5, and the vertical axis represents the switching voltage of the field effect transistor.
As can be seen from this graph, when the pattern width W (Ns) of the source region 5 is 1 micrometer or less, a switching voltage withstand capability of 20 volts or more that can be actually used is obtained.

Next, the opening of the mask for forming the base contact region 6 and the source region 5 will be described.
FIG. 8 is a schematic diagram for explaining the opening of the mask and the impurity concentration distribution. That is, the graph of FIG. 6A represents the impurity concentration distribution of the n ⁺ type source region 5, and the graph of FIG. 4B represents the impurity concentration distribution of the p ⁺ type base contact region 6. The horizontal axis of these graphs represents the distance in the channel direction (the horizontal direction in FIG. 1B). In these graphs, the positions of the gate electrode 15 and the respective mask openings are also shown.

As shown in FIGS. 8A and 8B, in this embodiment, the p ⁺ -type base contact region 6 (p-type impurity concentration peak region) is provided far away by the offset amount Loff 1 when viewed from the drain portion. At the same time, the n ⁺ -type source region 5 (the peak region of the n-type impurity concentration) can be moved away from the end of the gate electrode 15 by the offset amount Loff 2. That is, the junction between the source region 5 and the base region 4 is provided closer to the drain part D than the junction between the base contact region 6 and the base region 4. In the present specification, the “junction between the base contact region 6 and the base region 4” is an opening end of a mask for selectively forming p-type impurities in the base contact region 6. The portion where the p-type impurity concentration starts to decrease toward the base region 4 is assumed. Further, the opening end of the mask for selectively forming the n-type impurity in the source region 4 is provided on the drain part D side by Loff1 rather than the mask opening end for selectively forming the p-type impurity in the base contact region 6. Thus, the junction between the source region 5 and the base region 4 is provided closer to the drain portion D than the junction between the base contact region 6 and the base region 4.

In this case, the offset amount Loff (p ⁺ ) of the p ⁺ -type base contact region 6 and the offset amount Loff (Ns) from the end of the gate electrode 15 of the n ⁺ -type source region 5 are respectively p of the base contact region 6. The gate side opening end of the mask used in the step of selectively forming the n-type impurity, the gate side opening end of the mask used in the step of selectively forming the n-type impurity of the source region 5, and the gate mask pattern end And can be defined by adjusting the relationship.
That is, the openings of the mask used when introducing impurities to form these regions 6 and 5 may be shifted as shown in the figure. In this way, the parasitic bipolar effect in the source part S can be suppressed and the switching tolerance can be further improved while reducing the on-resistance.

Next, the offset of the n ⁺ type drain region 7 will be described.
FIG. 9 is a schematic diagram for explaining the offset of the n ⁺ -type drain region 7. That is, the graph of FIG. 6 represents the impurity concentration distribution of the n ⁺ -type drain region 7, and the horizontal axis represents the distance in the channel direction (the horizontal direction in FIG. 1B). This graph also shows the positions of the gate electrode 15 and the mask opening.

As shown in FIG. 9, in this embodiment, the n ⁺ -type drain region 7 can be formed away from the end of the gate electrode 15 by an offset amount Loff 3. That is, the opening of the mask used in the step of introducing impurities for forming the drain region 7 may be arranged away from the gate end as shown in FIG.

  FIG. 10 is a schematic view illustrating a field effect transistor according to a modification example of this embodiment. 1A is a cross-sectional view of a field effect transistor, and FIG. 1B is a schematic view illustrating a planar arrangement of a semiconductor portion of the field effect transistor. In the figure, the same elements as those described above with reference to FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

In this modification, a drift region 18 in which n-type stripe regions 18 a and p-type stripe regions 18 b are alternately provided is formed between the p-type base region 4 and the n ⁺ -type drain region 7. Each of the n-type stripe region 18a and the p-type stripe region 18b is formed in a stripe shape extending along the channel direction. The width W (width in the direction perpendicular to the channel) of the n-type stripe region 18a and the p-type stripe region 18b is set to be smaller than the width of the depletion layer generated in the pn junction in the thermal equilibrium state. ing. In this way, when the transistor is in the off state (drain voltage is 0 volts), the drift region 18 is depleted by the diffusion potential, and high frequency can be reliably cut off by reducing the output capacitance. Such a depletion effect of the drift region 18 can greatly reduce the capacitance between the source and the drain and the capacitance between the drain and the gate when the transistor is in the off state.

In order to deplete the drift region 18 in a thermal equilibrium state, it is desirable that the width W of the n-type stripe region 18a and the p-type stripe region 18b satisfy the following condition.
W <(2εs · Vbi (Np + Nn) / (qNpNn)) ^0.5
Here, εs is the relative dielectric constant of silicon, and Vbi is the diffusion potential of the pn junction of the stripe regions 18a and 18b.

  When a positive potential is applied to the gate electrode 15, the depleted drift region 18 is filled with electrons generated by the gate voltage to reduce the resistance, and as a result, the transistor enters a low on-resistance state.

  FIG. 11 is a schematic view illustrating a transistor according to a second modification of this embodiment. 1A is a cross-sectional view of a transistor, and FIG. 1B is a schematic view illustrating a planar arrangement of a semiconductor portion of the transistor. In this figure, the same elements as those described above with reference to FIGS. 1 to 10 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the present embodiment, the second gate electrode 30 is provided on the back side of the support substrate 2. As described above with reference to FIGS. 1 and 10, when the transistor is turned on, a voltage is applied to the gate electrode 15 to form a channel in the p-type base region 4, but an electric field is not sufficiently applied to the drift region 18. There is also. Therefore, in this modified example, the second gate electrode 30 is provided on the back surface side of the support substrate 2, an electric field is applied to the drift region 18 through the buried insulating layer 3, and a channel is reliably formed in the drift region 18. Low on-resistance can be realized.

  Here, since the second gate electrode 30 is provided via the buried insulating layer 3 thicker than the gate insulating film 14, it suppresses a decrease in device breakdown voltage and an increase in gate-drain capacitance Cdg. However, a low on-resistance can be realized.

  FIG. 11 illustrates the drift region 18 using a low-concentration p-type semiconductor or n-type semiconductor. However, the present invention is not limited to this, and a plurality of drift regions 18 may be used as illustrated in FIG. The same effect can be obtained even if a stripe region is used.

  Further, the second gate electrode 30 may be provided on the back surface of the buried insulating layer 3 without providing the support substrate 2 on the back surface of the buried insulating layer 3.

Next, a photo relay using the transistor of this embodiment will be described.
FIG. 12 is a schematic diagram showing a circuit of the photorelay of this embodiment.

  In other words, the photorelay includes a GaAs infrared light emitting diode 50, a PDA (Photo Diode Array) 52, and MOSFET switches 54 and 56, and can be accommodated in a 4-pin package (SOP) or the like. The chip size is about 0.8 × 0.8 mm. Two MOSFET switches 54 and 56 are connected in one chip to form an AC switch. As the MOSFET switches 54 and 56, the field effect transistors described above with reference to FIGS. 1 to 11 can be used.

In this case, the thickness of the SOI layer 20 used for the MOSFET switches 54 and 56 is about 0.1 micrometers, the thickness of the buried insulating layer 3 is about 3 micrometers, and the thickness of the gate insulating film 14 is about 0.14 micrometers. The offset amount Loff (Nd) between the n ⁺ -type drain region 7 and the end of the gate electrode 15 can be about 0.6 micrometers.

  According to the present embodiment, by using the MOSFETs 54 and 56 having a low on-resistance and a high switching tolerance, an extremely high isolation characteristic of 10 decibels can be obtained for a signal frequency of 2.5 GHz. At the same time, the insertion loss of this photorelay is as low as 1 decibel at a signal frequency of 2 gigahertz, so that both high breakdown voltage and low loss can be achieved.

  Hereinafter, other embodiments of the present invention will be described. In addition, about the element similar to what was mentioned above, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

[Second Embodiment]
FIG. 14 is a schematic view illustrating a transistor according to the second embodiment of the invention. 1A is a cross-sectional view of a transistor, and FIG. 1B is a schematic view illustrating a planar arrangement of a semiconductor portion of the transistor.

  The transistor according to the present embodiment also has an SOI structure as in the first embodiment. That is, an SOI layer 20 is provided on a support substrate 2 made of silicon via a buried insulating layer 3 made of silicon oxide. The SOI layer 20 includes a source portion S, a drain portion D, and these A p-type base region 4 and a drift region 18 provided therebetween are provided.

The source portion S has a structure in which n ⁺ type source regions 5 and p ⁺ type base contact regions 6 are alternately arranged in a direction perpendicular to the channel. The n ⁺ type source region 5 and the p ⁺ type base contact region 6 are both connected to the source electrode, and the p ⁺ type base contact region 6 plays a role of fixing the potential of the p type base region 4 to the source potential. Have.

The drain part D is composed of an n ⁺ type drain region 7. The p-type base region 4 is a semiconductor region that forms a channel. The drift region 18 is made of p ^- type or n ^- type silicon having a higher resistance than the p-type base region 4 and has a role of increasing the breakdown voltage of the transistor.

A gate insulating film 14 is provided on the p-type base region 4, and a gate electrode 15 is provided thereon. The gate electrode 15 includes a part of the n ⁺ -type source region 5 (near the junction between the p-type base region 4 and the n ⁺ -type source region 5) and a part of the drift region 18 (the p-type base region 4 and the drift region). 18 to the vicinity of the joint portion with 18). A conductive layer 16 made of tungsten silicide (WSi) or the like is appropriately provided on the gate electrode 15 in order to reduce connection resistance with a gate wiring (not shown).

Also in this embodiment, when a predetermined voltage is applied to the gate electrode 15, a channel is formed in the p-type base region 4 to be turned on, and a current can flow between the source region 5 and the drain region 7. By providing the p ⁺ -type base contact region 6, the potential of the p-type base region 4 is fixed to the source potential in the off state, and the parasitic bipolar effect during the off state and switching can be suppressed to improve the breakdown voltage of the transistor.

Furthermore, the present inventors have designed the ratio of the channel length Lch to the width W (Ns) of the source region 5 to be 1.5 or more, that is, Lch / W (Ns) ≧ 1.5, The hole current generated at the time of device switching or in the avalanche region can be efficiently discharged to the source electrode through the p ⁺ -type base contact region 6, and the parasitic bipolar effect is suppressed, thereby increasing the avalanche resistance and switching resistance. The knowledge that it can improve was obtained.

  The width W (Ns) of the source region 5 is a width seen in the direction in which the source regions 5 and the base contact regions 6 are alternately arranged (perpendicular to the direction connecting the source portion S and the drain portion D). . The channel length Lch is the length of the base region 4 below the gate electrode 15 as viewed in a direction parallel to the direction connecting the source portion S and the drain portion D. However, since the actual channel length Lch varies depending on the manufacturing process, the gate length Lg given as a nominal value (the length of the gate electrode 15 as viewed in a direction parallel to the direction connecting the source portion S and the drain portion D). ) May be adopted as the channel length Lch.

  FIG. 15 shows a transistor having the structure shown in FIG. 14 and designed with a device breakdown voltage (static breakdown voltage) Vdss = 34 (V), and various Lch / W (Ns) values are set. It is a figure showing the result of having calculated the drain voltage peak by simulation. The horizontal axis represents Lch / W (Ns), and the vertical axis represents the drain voltage peak (V) during switching.

  When Lch is 0.5 micrometer (μm) and W (Ns) is 1 micrometer (μm) (Lch / W (Ns) = 0.5), Lch is 1 micrometer (μm) and W (Ns ) Is 1.6 micrometers (μm) (Lch / W (Ns) = 0.625), Lch is 1 micrometer (μm), and W (Ns) is 0.8 micrometers (μm). In this case (Lch / W (Ns) = 1.25), Lch is 1 micrometer (μm), and W (Ns) is 0.4 micrometer (μm) (Lch / W (Ns) = 2.5 ), When Lch is 2 micrometers (μm) and W (Ns) is 0.8 micrometers (μm) (Lch / W (Ns) = 2.5), Lch is 2 micrometers (μm), W When (Ns) is 0.4 micrometers (μm) (L h / W (Ns) = 5), Lch is 4 micrometers (μm), W (Ns) is 0.8 micrometers (μm) (Lch / W (Ns) = 5), Lch is 4 micrometers When the meter (μm) and W (Ns) are set to 0.4 micrometer (μm), the drain voltage peak at the time of switching was calculated by simulation for seven cases (Lch / W (Ns) = 10).

The width W (P ⁺ ) of the base contact region 6 in the direction in which the source regions 5 and the base contact regions 6 are alternately arranged (perpendicular to the direction connecting the source portion S and the drain portion D) is , Fixed to 1.6 micrometers (μm).

  In FIG. 15, the approximate straight line of data smaller than the element breakdown voltage Vdss (= 34V) and the approximate straight line of data larger than the element breakdown voltage Vdss (= 34V) intersect at Lch / W (Ns) = 1.5. That is, with Lch / W (Ns) = 1.5 as a boundary, when Lch / W (Ns) is smaller than 1.5, the switching withstand voltage is smaller than the element withstand voltage Vdss (= 34V), and Lch / W (Ns) By setting the value to 1.5 or more, a switching withstand voltage of element withstand voltage Vdss (= 34 V) or more can be obtained.

You may combine this 2nd Embodiment and 1st Embodiment mentioned above. That is, when viewed from the drain portion D, the p ⁺ type base contact region 6 may be offset so as to recede far from the n ⁺ type source region 5. By doing so, an effective channel area can be ensured in the on-state, an increase in on-resistance can be suppressed, and a high breakdown voltage can be realized by satisfying Lch / W (Ns) ≧ 1.5.

  Further, while satisfying Lch / W (Ns) ≧ 1.5 and as described above with reference to FIG. 7, the switching region can be further improved by setting the width W (Ns) of the source region 5 to 1 micrometer or less. Can be improved.

  Further, as shown in FIG. 10, the drift region 18 may have a configuration in which n-type stripe regions 18a and p-type stripe regions 18b are alternately provided.

  Also, the transistor according to the second embodiment can be used as the MOSFET switches 54 and 56 in the photorelay described above with reference to FIG. 12, as in the first embodiment. The gate drive voltage of the MOSFET switches 54 and 56 is substantially equal to or higher than the drain-source breakdown voltage of the MOSFET switches 54 and 56.

  By reducing the thickness of the SOI layer (for example, by reducing it to 1 micrometer or less), the output capacity can be reduced. Such thin-film SOIMOSFETs have been commercialized as low-voltage CMOS for signal processing in LSI logic circuits and the like, but in such fields, the device withstand voltage may be relatively low, The decline did not become a problem. However, when a relatively high breakdown voltage is required, and a relay MOSFET having a large area (a large gate width Wg) or a thin-film SOI structure MOSFET is used in the power device field, it is important to reduce switching resistance and avalanche resistance. It became a serious problem and prevented commercialization.

  However, according to the transistor of the present embodiment, a high breakdown voltage can be obtained while reducing the output capacitance by thinning the SOI layer, so that the thin film SOI structure MOSFET is applied to products in the field of semiconductor relays and power devices. It becomes possible to do.

[Third Embodiment]
FIG. 16 is a schematic perspective view illustrating the plan and cross-sectional structure of the main part of the transistor according to the third embodiment of the invention.
17 is a cross-sectional view taken along line AA in FIG.
The transistor according to this embodiment is a MOSFET having a so-called trench gate structure.

On the main surface of the drain layer 27 made of n ⁺ type silicon, a drift layer 28 made of n ⁻ type silicon is provided. A trench T is formed in the surface layer portion of the drift layer 28, and the trench T is filled with a gate electrode 21 made of, for example, polysilicon via a gate insulating film 24. A drain electrode 26 is provided on the surface opposite to the main surface of the drain layer 27.

A base region 23 made of p-type silicon is provided on the drift layer 28 between the adjacent trenches T, and a source part is provided on the base region 23. The source portion has a structure in which n ⁺ -type source regions 22 and p ⁺ -type base contact regions 25 are alternately arranged in a direction perpendicular to the channel (a direction perpendicular to the depth direction of the trench T). . Source region 22 and base contact region 25 are both connected to source electrode 41. The base contact region 25 has a role of fixing the potential of the base region 23 to the source potential.

  When a predetermined voltage is applied to the gate electrode 21, a channel is formed in the base region 23 and is turned on, so that a current can flow between the source region 22 and the drain layer 27. By providing the base contact region 25, the potential of the base region 23 is fixed to the source potential in the off state, the parasitic bipolar effect during the off state and switching can be suppressed, and the breakdown voltage of the transistor can be improved.

Also in the present embodiment, as in the second embodiment, the source region 22 and the drain with respect to the width W (Ns) of the source region 22 as viewed in the direction in which the source regions 22 and the base contact regions 25 are alternately arranged. The ratio of the channel length Lch viewed in the direction parallel to the direction connecting the layer 27 is 1.5 or more, that is, Lch / W (Ns) ≧ 1.5. Thereby, the hole current generated at the time of device switching or in the avalanche region can be efficiently discharged to the source electrode 41 through the p ⁺ -type base contact region 25, and the parasitic bipolar effect is suppressed, and the avalanche resistance is increased. In addition, the switching tolerance can be improved.

  When a predetermined voltage is applied to the gate electrode 21, an inversion layer is formed in a portion of the base region 23 facing the gate electrode 21, and a charge storage layer is formed in a portion of the drift layer 28 facing the gate electrode 21. Become a channel. Therefore, the channel length Lch in the present embodiment includes not only the length of the portion facing the gate electrode 21 in the base region 23 but also the length of the portion facing the gate electrode 21 in the drift layer 28.

[Fourth Embodiment]
FIG. 18 is a schematic perspective view illustrating the plan and cross-sectional structure of the main part of the transistor according to the fourth embodiment of the invention.
19 is a cross-sectional view taken along the line BB in FIG.
The transistor according to this embodiment is an IGBT (Insulated Gate Bipolar Transistor) having a so-called trench gate structure.

On the main surface of the collector layer 31 made of p-type silicon, an n ⁺ -type silicon layer 32 and a drift layer 28 made of n ⁻ -type silicon are provided in this order. A trench T is formed in the surface layer portion of the drift layer 28, and the trench T is filled with a gate electrode 21 made of, for example, polysilicon via a gate insulating film 24. A collector electrode 35 is provided on the surface opposite to the main surface of the collector layer 31.

A base region 23 made of p-type silicon is provided on the drift layer 28 between adjacent trenches T, and an emitter portion is provided on the base region 23. The emitter section has a structure in which n ⁺ -type emitter regions 34 and p ⁺ -type base contact regions 25 are alternately arranged in a direction perpendicular to the channel (a direction perpendicular to the depth direction of the trench T). . Both the emitter region 34 and the base contact region 25 are connected to the emitter electrode 36. The base contact region 25 has a role of fixing the potential of the base region 23 to the emitter potential.

  When a predetermined voltage is applied to the gate electrode 21, a channel is formed in the base region 23 and is turned on, so that a current can flow between the emitter region 34 and the collector layer 31. By providing the base contact region 25, the potential of the base region 23 is fixed to the emitter potential in the off state, the parasitic bipolar effect during the off state and switching can be suppressed, and the breakdown voltage of the transistor can be improved.

Further, in the present embodiment, with respect to the direction connecting the emitter region 34 and the collector layer 31 with respect to the width W (Ns) of the emitter region 34 in the direction in which the emitter regions 34 and the base contact regions 25 are alternately arranged. The channel length Lch ratio in the parallel direction is designed to be 1.5 or more, that is, Lch / W (Ns) ≧ 1.5. As a result, the hole current generated at the time of device switching or in the avalanche region can be efficiently discharged to the emitter electrode 36 through the p ⁺ -type base contact region 25, and the parasitic bipolar effect is suppressed and the avalanche resistance is reduced. In addition, the switching tolerance can be improved.

  Similarly to the third embodiment, the channel length Lch includes not only the length of the portion facing the gate electrode 21 in the base region 23 but also the length of the portion facing the gate electrode 21 in the drift layer 28.

  The transistors according to the third and fourth embodiments can also be used as the MOSFET switches 54 and 56 in the photorelay described above with reference to FIG.

[Fifth Embodiment]
FIG. 20 is a schematic view illustrating the cross-sectional structure of a transistor according to the fifth embodiment of the invention.

  Similar to the first and second embodiments, the transistor according to the present embodiment also has an SOI structure. That is, the SOI layer 20 is provided on the main surface of the silicon substrate 2 via the buried insulating layer 3 made of silicon oxide. This SOI structure is obtained, for example, by forming the buried insulating layer 3 on the main surface of the silicon substrate 2 by high-temperature oxidation and attaching the SOI layer 20 on the first main surface of the buried insulating layer 3. It is done. The conductivity type of the silicon substrate 2 is n-type, for example, but may be p-type.

  The SOI layer 20 is provided with a source part S, a drain part D, and a p-type base region 4 and a drift region 18 provided therebetween. The source part S, the drain part D, the base region 4 and the drift region 18 are provided on the first main surface of the buried insulating layer 3.

Also in this embodiment, as in the second embodiment, as shown in FIG. 14B, the source portion S includes an n ⁺ type source region 5 and a p ⁺ type base contact region 6 as a channel. And alternately arranged in the vertical direction. The drain part D is composed of an n ⁺ type drain region 7. By providing the p ⁺ -type base contact region 6, the potential of the p-type base region 4 is fixed to the source potential in the off state, the parasitic bipolar effect during the off state and switching can be suppressed, and the breakdown voltage of the transistor can be improved.

A gate insulating film 14 is provided on the base region 4, and a first gate electrode 15 is provided thereon. The gate insulating film 14 and the gate electrode 15 are part of the n ⁺ type source region 5 (near the junction between the p type base region 4 and the n ⁺ type source region 5) and part of the drift region 18 (p type base). (Near the junction between the region 4 and the drift region 18). The gate insulating film 14 is formed thicker than a gate insulating film used in, for example, a digital semiconductor integrated circuit such as a memory device or a logic circuit in order to ensure a withstand voltage required for power electronics applications.

  On the surface (back surface) opposite to the main surface of the silicon substrate 2, a second gate electrode 37 is provided over the entire surface. The buried insulating layer 3 also functions as a second gate insulating film corresponding to the second gate electrode 37. The second gate electrode 37 may be selectively provided at least in a portion facing the base region 4, but in this case, since alignment accuracy is required, in the present embodiment, from the viewpoint of facilitating manufacturing. The second gate electrode 37 is formed over the entire back surface of the silicon substrate 2.

  An interlayer insulating film 39 is provided on the SOI layer 20 so as to cover the first gate electrode 15, and a contact opening exposing a part of the source region 5 and a part of the base contact region 6 to the interlayer insulating film 39. A source electrode 41 in contact with the source region 5 and the base contact region 6 is provided through the contact opening. That is, the source region 5 and the base contact region 6 are both connected to the source electrode 41, and the base contact region 6 has a role of fixing the potential of the base region 4 to the source potential.

  The interlayer insulating film 39 is also formed with a contact opening that exposes a part of the drain region 7, and a drain electrode 42 that is in contact with the drain region 7 is provided through the contact opening.

The drift region 18 is made of p ⁻ type or n ⁻ type silicon having a higher resistance than the p type base region 4, improves the breakdown voltage between the source and the drain, and has a gate-drain capacitance (Cgd) and a source / drain. It serves to reduce the inter-space capacity (Csd). The thickness of the SOI layer 20 is, for example, 0.1 to reduce capacitance such as gate-drain capacitance (Cgd), source-drain capacitance (Csd), and drain-second gate capacitance (Cg2). It is as thin as a micrometer (μm). The capacitance between the output terminals when the signal is cut off (when off) includes the source-drain capacitance (Csd), the gate-drain capacitance (Cgd), and the drain-second gate capacitance (Cg2). Of these, the gate-drain capacitance (Cgd) and the source-drain capacitance (Csd) occupy a large proportion.

  In the present embodiment, a part of the silicon substrate 2 includes a second main surface of the buried insulating layer 3 (a surface opposite to the first main surface on which the SOI layer 20 is formed) and the silicon substrate 2. And a cavity 38 surrounded by. The cavity 38 is provided in contact with the portion of the second main surface of the buried insulating layer 3 that faces the drain region 7 and the drift region 18. If the cavity 38 is provided at a position overlapping the base region 4, the formation of the channel ch 2 by the second gate electrode 37 is hindered. Therefore, it is desirable that the cavity 38 does not overlap the base region 4. . However, due to manufacturing variations, the cavity 38 may slightly overlap the base region 4 to the extent that it does not significantly affect the formation of the channel ch2.

  FIG. 21 is a schematic view illustrating the method for forming the cavity 38.

  Before the buried insulating layer 3 is provided on the silicon substrate 2, a portion where the cavity 38 is to be formed in the silicon substrate 2 is removed by etching, and then a sacrificial layer is buried by, for example, SOG (Spin On Glass) method. Then, the buried insulating layer 3 and the SOI layer 20 are formed. Then, after forming a via 38a that penetrates each layer on the sacrificial layer and reaches the sacrificial layer, the sacrificial layer is removed by etching through the via 38a to form the cavity 38. Thereafter, the opening of the via 38a is sealed with a sealing material 43 such as a resin. The cavity 38 may be air or sealed with the sealing material 43 in an inert gas atmosphere such as nitrogen gas or argon gas, so that the inert gas is filled in the cavity 38. It is good also as a structure.

  In the present embodiment, when a predetermined voltage is applied to the first gate electrode 15, the first channel ch 1 is formed on the gate insulating film 14 side in the p-type base region 4, and further, the second gate electrode 37 When a predetermined voltage is applied, a second channel ch2 is formed on the buried insulating layer 3 side in the p-type base region 4. That is, when the element is turned on, channels can be generated from both sides of the base region 4, and a low on-resistance can be realized.

  Further, in the present embodiment, the cavity portion 38 is provided in the portion under the drain region 7 in the silicon substrate 2 so that the dielectric portion under the drain region 7 is thickened. As a result, the breakdown voltage between the source and the drain when the element is off can be improved, the capacitance between the drain region 7 and the second gate electrode 37 can be reduced, and the output capacitance and the CR product can be reduced.

  For example, the thickness of the gate insulating film 14 is 0.14 micrometers (μm), and the thickness of the buried insulating layer 3 is the same thickness as the gate insulating film 14 (0.14 micrometers), It is more thick (about 3 micrometers). When the buried insulating layer 3 is thicker than the gate insulating film 14, a threshold voltage Vth2 that applies a positive voltage to the second gate electrode 37 and the drain electrode 42 to make the second channel ch2 conductive (on state). Is larger than the threshold value Vth1 for applying a positive voltage to the first gate electrode 15 and the drain electrode 42 to turn on the first channel ch1 (on state), for example, four times or more.

[Sixth Embodiment]
FIG. 22 is a schematic view illustrating the cross-sectional structure of a transistor according to the sixth embodiment of the invention.

  In the present embodiment, an insulating layer 44 surrounded by the second main surface of the buried insulating layer 3 and the silicon substrate 2 is provided on a part of the silicon substrate 2. The insulating layer 44 is provided in contact with the portion of the second main surface of the buried insulating layer 3 that faces the drain region 7 and the drift region 18. If the insulating layer 44 is provided so as to overlap the base region 4, the channel ch 2 is prevented from being formed by the second gate electrode 37. Therefore, it is desirable that the insulating layer 44 does not overlap the base region 4. . However, due to manufacturing variations, the insulating layer 44 may slightly overlap the base region 4 to the extent that it does not significantly affect the formation of the channel ch2.

  The insulating layer 44 is silicon oxide embedded by, for example, the SOG method after forming a recess in the silicon substrate 2.

  Also in this embodiment, the dielectric layer under the drain region 7 is thickened by providing the insulating layer 44 in the portion under the drain region 7 in the silicon substrate 2. As a result, the breakdown voltage between the source and the drain when the element is off can be improved, the capacitance between the drain region 7 and the second gate electrode 37 can be reduced, and the output capacitance and the CR product can be reduced.

[Seventh Embodiment]
FIG. 23 is a schematic view illustrating the cross-sectional structure of a transistor according to the seventh embodiment of the invention.

  In this embodiment, after forming the SOI structure, the source portion S, the base region 4, the drift region 18, the drain portion D, the gate insulating film 14, the gate electrode 15, the source electrode 41, the drain electrode 42, etc., the support substrate is removed. A second gate electrode 45 is provided on the second main surface of the buried insulating layer 3 exposed by removing the support substrate.

  The second gate electrode 45 is provided in a portion facing the base region 4 and the source region 5 on the second main surface of the buried insulating layer 3. Further, by not providing the second gate electrode 45 in a portion facing the drain region 7, the capacitance between the drain region 7 and the second gate electrode 45 can be reduced, and the output capacitance and the CR product can be reduced. it can. If the second gate electrode 45 is provided at a position overlapping the drift region 18, the channel ch 2 can be extended to the drift region 18 when a gate voltage is applied to the second gate electrode 45. Although resistance can be achieved, since the second gate electrode 45 approaches the drain region 7, the capacitance between the drain region 7 and the second gate electrode 45 may be increased.

[Eighth Embodiment]
FIG. 24 is a schematic view illustrating the cross-sectional structure of a transistor according to the eighth embodiment of the invention.

  In the present embodiment, an insulating layer 46 that insulates and separates the silicon substrate 2 into the first portion 2a and the second portion 2b is provided on the second main surface of the buried insulating layer 3. The insulating layer 46 is provided in a portion facing the drift region 18, and the silicon substrate 2 is divided into a first portion 2 a facing the source region 5 and the base region 4, and a second portion 2 b facing the drain region 7. Insulating and separating. The insulating layer 46 is made of, for example, silicon oxide. Alternatively, a hollow portion may be provided instead of the insulating layer 46.

  Further, after the conductive film 37 is formed on the entire back surface of the silicon substrate 2, a dividing groove 58 is formed by etching, for example, and the first portion 47 and the first portion 47 are separated from the position where the insulating layer 46 is provided. Insulated and separated from the second portion 48. The first portion 47 of the conductive film 37 functions as a second gate electrode to which a gate voltage is applied. No voltage is applied to the second portion 48 of the conductive film 37. Further, an insulating layer 46 that is a dielectric is interposed between the second gate electrode 47 and the drain region 7. As a result, the parasitic capacitance between the drain and the second gate can be suppressed, and the output capacitance and the CR product can be reduced.

[Ninth Embodiment]
FIG. 25 is a schematic view illustrating the cross-sectional structure of a transistor according to the ninth embodiment of the invention.

  Even if the cavity 38 in the fifth embodiment described above with reference to FIG. 20 is not provided over the entire portion facing the drift region 7, as in the present embodiment shown in FIG. The drain region 7 may be provided only under the vicinity of the junction with the drift region 18. That is, by providing the cavity portion 38 between the second gate electrode 37 and the drain region 7, the parasitic capacitance between the drain and the second gate is suppressed, and the output capacitance and the CR product are reduced. Can be made.

[Tenth embodiment]
FIG. 26 is a schematic view illustrating the cross-sectional structure of the terminal portion of the transistor according to the tenth embodiment of the invention.

  The transistors according to the fifth to ninth embodiments whose cross-sectional structures of the element portion are shown in FIGS. 20 to 25 can adopt, for example, the structure shown in FIG. .

  A plurality of insulating layers 52 that are spaced apart from each other when viewed in a direction parallel to the main surface of the silicon substrate 2 and are each thicker than the buried insulating layer 3 are connected to the pad portion 42a of the drain electrode 42 and the second portion at the terminal portion. It is provided between the gate electrode 37. These insulating layers 52 are formed, for example, by forming a buried insulating layer 3 on the silicon substrate 2 and then forming a plurality of trenches that penetrate the buried insulating layer 3 and reach the middle of the silicon substrate 2. Can be obtained by, for example, embedding with silicon oxide. The insulating layer 52 can suppress the parasitic capacitance between the drain pad portion and the second gate in the termination portion, and can reduce the output capacitance and the CR product.

[Eleventh embodiment]
FIG. 27 is a schematic view illustrating the cross-sectional structure of a transistor according to the eleventh embodiment of the invention.

  In the present embodiment, the structures of the source region 61, the base region 62, the drift region 63, and the drain region 64 on the buried insulating layer 3 are different from those of the fifth embodiment described above with reference to FIG. That is, the source region 61 is selectively formed in the surface layer portion of the base region 62, and the source region 61 and the base region 62 are provided at positions that overlap when viewed in the thickness direction.

  Next, FIG. 28 is a graph showing the result of comparison of CR products between the structure of the embodiment of the present invention and the structure of the comparative example.

  Example 1 on the horizontal axis of the graph corresponds to the structure of the fifth embodiment shown in FIG. 20, and Example 2 corresponds to the seventh embodiment shown in FIG. 3 corresponds to the eighth embodiment shown in FIG. Further, the comparative example corresponds to a structure in which the cavity portion 38 is not provided in the fifth embodiment shown in FIG. In the comparative example and Examples 1 to 3, the drain-source breakdown voltage is 20 (V), the gate voltage Vg is 40 (V), the substrate potential is 80 (V), and the drain current Id is 0.1 (A). .

  Table 1 shows the ON resistance Ron (Ω), the drain-source breakdown voltage Vdss (V), the drain-substrate capacitance (pF), the output capacitance Cout (pF), and the CR product (pFΩ) in Examples 1 to 3. ).

  From the result of FIG. 28, the CR product is 2.5 (pFΩ) in the structure of the comparative example, whereas in Examples 1 and 2, it can be about 0.5 (pFΩ). In Example 3, it can be reduced to 0.25 (pFΩ), which is about 1/10 of that of the comparative example. This value of 0.25 (pFΩ) is much higher than the limit of silicon MOSFETs that are currently commercialized.

  FIG. 29 is a schematic diagram showing a photorelay circuit using any of the transistors described above with reference to FIGS. 20 to 27 as MOSFET switches 66 and 67.

  A light emitting element (light emitting diode) 71 that emits light in response to the switching control signal is connected between the input terminals IN1 and IN2 to which the switching control signal is input. A photodiode array 72 (consisting of a plurality of photodiodes connected in series) that receives the light emitted from the light emitting element 71 and generates a DC voltage is provided.

  The first gate electrode G11 and the second gate electrode G21 of the MOSFET switch 66 and the first gate electrode G12 and the second gate electrode G22 of the MOSFET switch 67 are connected to each other, and a photodiode array is connected to these gate electrodes. The DC voltage output from 72 is supplied via the control circuit 73. The drain electrodes D1, D2 of the MOSFET switches 66, 67 are connected to the output terminals OUT1, OUT2.

  When the DC voltage output from the photodiode array 72 is applied to the gate electrodes G11, G21, G12, and G22 of the MOSFET switches 66 and 67 via the control circuit 73, the MOSFET switches 66 and 67 are turned on. As a result, the output terminals OUT1 and OUT2 become conductive. When the switching control signal input to the input terminals IN1 and IN2 becomes zero, the light emitting element 71 stops emitting light, and thereby the DC voltage generated between both terminals of the photodiode array 72 is also extinguished, and the MOSFET switch 66, 67 is switched from the on state to the off state.

  The control circuit 73 has a discharge circuit 74 connected between the gate electrodes G11, G21, G12, G22 of the MOSFET switches 66, 67 and the source electrodes S1, S2. The discharge circuit 74 is a circuit for rapidly discharging the charge charged between the gate and the source when the MOSFET switches 66 and 67 are switched from the on state to the off state.

  One of the main applications in which semiconductor relays are used is measurement equipment such as LSI testers. In such a measuring instrument, by increasing the frequency of the signal that conducts / cuts off between the output terminals OUT1 and OUT2, in addition to lowering the on-resistance when the output terminals OUT1 and OUT2 are turned on, the output terminal OUT1 and OUT2 are cut off. A reduction in capacity is desired.

  In this embodiment, by using any of the transistors described above with reference to FIGS. 20 to 27 as the MOSFET switches 66 and 67, the on-resistance and the off-capacitance can be reduced, and a high breakdown voltage can be obtained.

The fifth to ninth embodiments described above with reference to FIGS. 20 to 25 can be combined with the first embodiment and the second embodiment. That is, when viewed from the drain region 7, the p ⁺ type base contact region 6 may be offset so as to recede far from the n ⁺ type source region 5. In this way, an effective channel area is secured in the on-state, an increase in on-resistance is suppressed, and a high breakdown voltage is achieved by setting the channel length Lch / the width W (Ns) of the source region 5 ≧ 1.5. Can be realized.

  Further, while satisfying Lch / W (Ns) ≧ 1.5 and as described above with reference to FIG. 7, the switching region can be further improved by setting the width W (Ns) of the source region 5 to 1 micrometer or less. Can be improved.

  Further, the drift region 18 in the fifth to ninth embodiments may have a configuration in which n-type stripe regions 18a and p-type stripe regions 18b are alternately provided as shown in FIG.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.
For example, the present invention is not limited as long as it has the gist of the present invention even if those skilled in the art have made various design changes with respect to the size, material, arrangement relationship, etc. of each element constituting the field effect transistor or photorelay. It is included in the range.

(A) is sectional drawing of the field effect transistor concerning the 1st Embodiment of this invention, (b) is a schematic diagram which illustrates planar arrangement | positioning of the semiconductor part of this field effect transistor. (A) And (b) is the schematic diagram which illustrated the distribution in the plane of the impurity concentration of the SOI layer in the transistor of a comparative example and 1st Embodiment by the contour line, respectively. (A) And (b) is a schematic diagram showing the density distribution of the electronic current in the transistor of 1st Embodiment illustrated in the comparative example illustrated in FIG. 2, and FIG. 1, respectively. It is a graph which illustrates the turn-off characteristic of the field effect transistor of the 1st embodiment of this invention. FIG. 5 is a graph illustrating the relationship between the offset amount of p ⁺ type base contact region 6 and the CR product of a transistor. FIG. 6 is a graph illustrating the relationship between the offset amount of the p ⁺ type base contact region 6 and the switching tolerance of the transistor. The relationship between the width | variety of the pattern of the source region 5 and switching breakdown voltage at the time of switching of the 20 volt element of the field effect transistor of 1st Embodiment is represented. It is a schematic diagram for demonstrating the opening part of a mask, and impurity concentration distribution. FIG. 6 is a schematic diagram for explaining an offset of an n ⁺ type drain region 7. It is a schematic diagram which illustrates the field effect transistor concerning the modification of the 1st Embodiment of this invention. It is a schematic diagram which illustrates the field effect transistor concerning the 2nd modification of the 1st Embodiment of this invention. It is a schematic diagram showing the circuit of the photo relay of the embodiment of the present invention. (A) is sectional drawing of the conventional field effect transistor obtained when it forms using a normal method, (b) is a schematic plan view of the semiconductor part. It is the schematic diagram which illustrated the field effect transistor concerning the 2nd Embodiment of this invention. In the field effect transistor concerning a 2nd embodiment of the present invention, Lch / W (Ns) is set up variously, and it is a figure showing the result of having performed simulation calculation of the drain voltage peak at the time of switching. FIG. 10 is a schematic perspective view illustrating the plane and cross-sectional structure of the main part of a transistor according to a third embodiment of the invention. It is AA sectional drawing in FIG. FIG. 10 is a schematic perspective view illustrating the plan and cross-sectional structure of the main part of a transistor according to a fourth embodiment of the invention. It is BB sectional drawing in FIG. FIG. 10 is a schematic view illustrating the cross-sectional structure of a transistor according to a fifth embodiment of the invention. FIG. 10 is a schematic view illustrating a method for forming a cavity in a transistor according to a fifth embodiment of the invention. FIG. 10 is a schematic view illustrating the cross-sectional structure of a transistor according to a sixth embodiment of the invention. FIG. 10 is a schematic view illustrating the cross-sectional structure of a transistor according to a seventh embodiment of the invention. FIG. 10 is a schematic view illustrating the cross-sectional structure of a transistor according to an eighth embodiment of the invention. FIG. 10 is a schematic view illustrating the cross-sectional structure of a transistor according to a ninth embodiment of the invention. It is a schematic diagram which illustrates the cross-section of the termination | terminus part of the transistor concerning 10th Embodiment of this invention. It is a schematic diagram which illustrates the cross-section of the transistor concerning 11th Embodiment of this invention. It is a graph showing the result of having compared CR product with the structure of the embodiment of the present invention, and the structure of a comparative example. It is a schematic diagram showing the circuit of the photo relay of the embodiment of the present invention.

Explanation of symbols

2 ... support substrate, 3 ... buried insulating layer, 4 ... base region, 5 ... n ⁺ type source region, 6 ... p ⁺ type base contact region, 7 ... n ⁺ type drain region, 14 ... gate insulating film, 15 ... Gate electrode, 16 ... conductive layer, 18 ... drift region, 18a ... n-type stripe region, 18b ... p-type stripe region, 20 ... SOI layer, 21 ... gate electrode, 22 ... source region, 23 ... base region, 24 ... gate Insulating film, 25 ... base contact region, 26 ... drain electrode, 27 ... drain layer, 28 ... drift layer, 30 ... second gate electrode, 34 ... emitter region, 35 ... collector electrode, 31 ... collector layer, 37 ... first 2 gate electrode, 38 ... cavity, 41 ... source electrode, 42 ... drain electrode, 43 ... sealing material, 44 ... insulating layer, 45 ... second gate electrode, 46 ... insulating layer, 47 ... second gate Gate electrode, 52: insulating layer, 61 ... source region, 62 ... base region 63 ... drift region 64 ... drain region

Claims (5)

A source unit having a plurality of first conductivity type source regions and a plurality of second conductivity type base contact regions arranged alternately, a first conductivity type drain unit, and the source unit and the drain unit. A semiconductor layer having a second conductivity type base region provided between and in contact with the source region and the base contact region;
  A gate insulating film provided in contact with the base region;
  A gate electrode provided opposite to the base region with the gate insulating film interposed between the base region;
  With
  A transistor, wherein a ratio of a channel length to a width of the source region in a direction in which the source region and the base contact region are alternately arranged is 1.5 or more. The transistor according to claim 1, wherein a junction between the source region and the base region is provided closer to the drain portion than a junction between the base contact region and the base region. The semiconductor layer is an SOI (Silicon On Insulator) layer provided on the first main surface of an insulating layer having a first main surface and a second main surface opposite to the first main surface. And
  The gate insulating film is provided on the base region;
  The transistor according to claim 1, wherein the gate electrode is provided on the gate insulating film. 4. The transistor according to claim 3, further comprising a dielectric provided in a portion of the insulating layer facing the drain portion on the second main surface side. 5. The transistor according to claim 3, further comprising a second gate electrode provided at a portion of the insulating layer facing the base region on the second main surface side.