JPH10340937A - Composite ic test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a test at a memory part and a logic part automatically in a short time without requiring any manual work by juxtaposing a memory test system and a logic test system and providing means for feeding a tested IC automatically to another test system. SOLUTION: A unit 40 for automatically carrying an IC is disposed between a memory test system and a logic test system and a tested IC is delivered from the memory test system to the logic test system. The test at the logic part finishes in a relatively short time but the test at the memory part requires a relatively long time. Assuming the test at the memory part requires 80 sec and the test at the logic part requires only 5 sec per piece, 30 sec is required for 16 pieces. Since all tests have been ended at the logic part when the test for next IC ends at the memory test system, the test can be carried out with maximum efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite IC test system for testing an IC in which a memory section and a logic section are mixed among ICs.

[0002]

2. Description of the Related Art Conventionally, IC types are mainly classified into memory ICs and logic ICs. The number of pins (the number of terminals) of the memory IC is at most 1 in spite of the increase in the memory capacity.
It is suppressed to about 0 pins (20 to 40 pins).
On the other hand, many logic ICs have a large number of terminals and several hundred pins (about 500 pins).

As described above, since the number of pins is significantly different between a memory IC and a logic IC and the test method is completely different, a memory test system for a memory IC and a logic test system for a logic IC have conventionally existed. ,
The memory IC and the logic IC are tested by completely different test systems. Incidentally, as a recent trend, composite ICs having a relatively large-capacity memory built in a logic IC are being manufactured. In order to test such a complex IC, it is originally desirable to conduct a comprehensive test in a form in which a logic circuit and a memory are combined. However, since the time required for the test is long, an expensive test system is required for a long time. Since it must be used, there is a disadvantage that the cost required for the test becomes too high.

For this reason, the extraction of pins (terminals) is generally devised so that the memory portion and the logic portion can be separately tested in a separated form, the memory portion is tested by a memory test system, and the logic portion is tested by a logic test system. A testing method is adopted. here,
The difference between the conventionally used memory test system for memory IC test and the logic test system for logic IC will be described in more detail. As described above, since the memory IC has a relatively small number of pins and is about 20 to 40 pins, an apparatus for testing a large number of ICs at once can be configured.
In other words, the part that brings the IC under test into contact with the test apparatus is called a test head, but the number of contacts that can be formed on this test head is limited.

For this reason, in a memory test system, for example, an IC having 60 pins is used in accordance with the number of pins of the IC under test.
Then, the number of ICs that can be tested is determined according to the number of pins of the IC under test, such that 16 ICs are tested at a time, and a 30-pin IC tests 32 ICs. Further, the reason why a large number of ICs are tested at one time in the memory test system is that the capacity of the memory is increasing, so that the time required for the test tends to be long. Also from this point, by testing a large number of ICs at once, the time required for the test is reduced, and the cost required for the test is reduced.

On the other hand, in a logic test system, since the number of bins of a logic IC is several hundred, the number of ICs that can be tested at one time is limited. For this reason, an apparatus for testing one to several devices at a time is generally used. This is shown in FIG. 3 and FIG. FIG. 3 shows a schematic configuration of the memory test system. In the figure, reference numeral 11A denotes a memory test handler constituting the memory test system, and 12A.
A indicates a test head for memory test mounted on the handler 11A, and 13A indicates a tester main body for memory test. The memory tester main body 13A is electrically connected to the memory test test head 12A by a cable 14, and tests the IC under test 15 attached to the contact portion of the memory test test head 12A.

The IC under test 15 is supplied to the memory test handler 11A by being stored in the supply tray 16. The wafer is conveyed from the supply side tray 16 to the memory test test head 12A by, for example, a memory test XY conveyance device 30A equipped with a vacuum suction head. The XY transfer device 30A for the memory test includes, for example, a rail 31 laid between the tray mounting side and the mounting position of the test head 12A for the memory test. Arm 32 that moves in the direction
And supported by this arm 32, and Y
Head 33 that moves in the direction
The vacuum suction head 34 is mounted in a posture of being suspended downward, and is moved downward by an air cylinder or the like, and attracts and suspends the IC 15 by suction of air. The example shown in FIG. 3 shows a case in which six vacuum suction heads 34 are mounted on the moving head 33 and six ICs are suctioned and conveyed at a time.

[0008] Similarly, the IC 15 after the test is mounted on the vacuum suction head 34 of the XY transfer device 30A for the memory test.
And is returned to the discharge side tray 17. A memory is provided for each storage position of the discharge side tray 17 and stores a judgment result of the quality of the stored IC. In the memory test system, as shown in the figure, a plurality (for example, about 16)
Are tested.

FIG. 4 shows a schematic configuration of a logic test system. Parts corresponding to those in FIG. 3 are denoted by the same reference numerals. As shown in the figure, a logic test system generally has a structure in which several (one in the example in the figure) ICs are tested at a time. In this logic test system, the IC 15 is transported from the supply side tray 16 to the test head 12B for logic test by the XY transport device 30B, and the IC 15 tested by the test head 12B for logic test is similarly XY-tested for logic test. The sheet is stored in the discharge tray 17 by the transport device 30B.

FIGS. 5 and 6 show a test system for testing a wafer. FIG. 5 shows a schematic configuration of a memory test system for testing a memory formed on a wafer, and FIG. 6 shows a schematic configuration of a logic test system for testing a logic circuit formed on a wafer. In general, a belt conveyor type transfer device is used as a wafer transfer device, but in this case, an XY transfer device will be described for simplification of description.

In a test system for testing in a wafer state, a memory test head 12A has a chuck 18 for sucking and supporting a wafer, and an XY transfer device 30A takes out one wafer WF from a supply side wafer container 19. To the test head 12 </ b> A and adsorb it to the chuck 18. A probe (not particularly shown) is inserted from the surroundings around the chuck 18 to electrically contact the probe with the terminal portion of each chip formed on the wafer WF, and each chip is electrically connected to the memory tester main body 13A. Connecting. This type of memory test system also has a structure in which probes are connected to a plurality of chips and a plurality of chips are simultaneously tested. In FIG. 5, the shaded portion indicates the portion of the chip being tested. To change the position of the chip to be tested, the chuck 18 is moved in the X-Y direction, and the position of the chip with which the probe contacts is changed to test each chip. After the test, the XY transfer device 30A stores the wafer WF in the discharge-side wafer container 20.

In the logic test system shown in FIG.
In the example of FIG. 6, a probe is brought into contact with one chip with respect to one wafer WF, and the chips are tested one by one. Other configurations and operations are the same as those of the memory test system shown in FIG.

[0013]

When testing an IC incorporating a logic circuit and a memory by the conventional IC test system shown in FIGS. 3 to 6, for example, the memory portion is tested by a memory test system and the memory portion is tested. After completing the test, the logic test is performed by the logic test system.

In this case, an IC which has been tested by the memory test system is manually transferred to the logic test system, and the IC is supplied to the logic test system. Therefore, the operator must perform the work of transferring the IC from one test system to the other test system, and thus the time required for moving the IC becomes longer and the time required for the test becomes longer. In addition, since the operator must be always present, labor and labor are required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a composite IC test system capable of automatically executing a test of a memory portion and a test of a logic portion in a short time and without human intervention.

[0016]

According to the present invention, there is provided an IC for automatically transferring an IC under test to a test head by using the automatic transfer device for transferring an IC, and testing the IC under test with the test head. The test system has a structure in which a memory test system for testing memory and a logic test system are provided side by side, and an automatic transfer mechanism for sending an IC that has been tested in one test system to the other test system is provided. It is a feature.

According to the configuration of the present invention, when an IC under test is supplied to one test system, the IC for which the test has been completed in that test system is automatically conveyed to another test system, and the test is performed in another test system. Be executed.
Therefore, assuming that the test is executed in the order of the memory test and the logic test, when the IC under test is supplied to the memory test system, the memory test system tests the memory portion in the IC under test. The IC for which the test of the memory portion has been completed is sent to the logic test system by the automatic transport device, the test of the logic portion is executed in the logic test system, and the IC is discharged to the discharge side of the logic test system. At the time of discharging, the test result of the memory portion and the test result of the logic portion are managed on the tray on the discharging side, and sorting is performed on the tray on the discharging side according to the test result.

[0018]

FIG. 1 shows an embodiment of the present invention. The embodiment shown in FIG. 1 shows a case where a memory test system and a logic test system are juxtaposed in the same housing. Reference numeral 16 denotes a supply tray supplied to the memory test system. An IC under test 15 having a memory section and a logic section is mounted on the supply side tray 16 and supplied.

The IC under test 15 mounted and supplied to the supply side tray 16 is supplied to the XY transfer device 30 for memory test.
A (in this example, a case where the arm 32 is supported on the rail 31 in a cantilever structure) is transferred to the test head 12A constituting the memory test system. For example, 16 IC sockets are prepared in the memory test test head 12A constituting the memory test system.
The IC under test 15 is mounted on this IC socket, and electrically connected to the tester main body 13A for memory test through the cable 14, and the test of the memory portion is executed.

A number is assigned to the IC socket mounted on the test head 12A for the memory test, and the number of the IC mounted on the supply tray 16 and the number of the tested IC socket are stored. And each IC
The ICs tested in the socket are stored separately depending on whether the storage operation speed of the memory is, for example, high speed, medium speed, or low speed, and are classified into ICs requiring a retest, ICs whose memory portions are determined to be defective, and the like. Is stored.

In the present invention, an automatic transfer device 40 for automatically transferring ICs is installed between the memory test system and the logic test system, and the ICs that have been tested by the memory test system are sent to the logic test system by the automatic transfer device 40. It is characterized by having a structure. In the example shown in FIG. 1, a buffer portion 21 is provided between the memory test system and the logic test system,
A case is shown in which a buffer section 21 temporarily stores ICs whose memory sections have been tested, and the ICs are sent one by one from the buffer section 21 to the logic test system by the automatic transfer device 40.

In this example, the automatic transfer device 40 includes a rail 41 extending between the test heads 12A and 12B, an arm 42 supported by the rail 41 in a cantilever structure, and moving in the X direction along the arm 42. Moving head 43
And a vacuum suction head 44 mounted downward on the moving head 43. The buffer unit 21 has at least a capacity capable of accommodating an IC to be tested at one time in the memory test system.
The ICs stored in the IC are sequentially transferred one by one to the logic test test head 12B constituting the logic test system by the automatic transfer device 40, and are mounted on the IC socket provided in the logic test test head 12B, The tester 13B is electrically connected to the tester main body 13B and receives a test of a logic part.

In many cases, the testing of the logic portion can be performed in a relatively short time. On the other hand, the test time of the memory part is long. For this reason, for example, assuming that the test of the memory part takes 80 seconds (including the transport time of the IC) and that the test of the logic part requires only 5 seconds, the test of the logic test system at 5 seconds per chip takes 16 seconds.
It takes about 80 seconds for an individual. Therefore, in the memory test system, when the test of the next IC is completed, all the tests of the logic portion have been completed, and the buffer portion 21 can be emptied. When the test time is allocated as described above, the test can be executed with maximum efficiency.

The IC 15 after the completion of the logic test is conveyed to the discharge tray 17 by the logic test XY transfer device 30B on the logic test system side and stored in each storage section of the discharge tray 17. The respective storage positions correspond to, for example, the mounting address positions of the supply side tray 16, and the test results of the memory portion and the test results of the logic portion are stored for each IC stored at each address of the discharge side tray 17,
The paper is sorted from the discharge side tray 17 to another tray (other trays are prepared by the number of types to be sorted) according to the distinction between the non-defective product and the defective product, and the difference in the operation speed of the memory portion.

As described above, according to the present invention, the IC is delivered from the memory test system to the logic test system by the automatic transfer device 40. Therefore, the ICs that have been tested by the memory test system are manually transferred to the logic test system. Since it is not necessary to perform the above, it is possible to efficiently test the composite IC including the memory portion and the logic portion.

FIG. 2 shows another embodiment of the composite IC test system according to the present invention. This embodiment shows a case where the present invention is applied to an IC tester of a type for directly testing an IC chip formed on a wafer. In this embodiment, the wafers WF are pulled out one by one from the supply-side wafer container 19, and the wafers are transferred to an automatic transfer device 30 for memory test.
By A, the wafer is conveyed to a memory test test head 12A constituting a memory test system. The test head 12A for memory test is provided with a chuck 18A for sucking the wafer WF by a vacuum suction force.
At step A, the wafer WF is sucked and fixed. At the same time, a probe (not particularly shown) is inserted from the periphery of the chuck 18A, and the tip of the probe contacts terminal portions formed on a plurality of chips, and each chip is electrically connected to the memory tester main body 13A. I do. The example of FIG. 2 shows a case where eight hatched chips are connected to the memory tester main body 13A.

The wafer WF on which the memory portion in the chip has been tested is transferred to the logic test test head 12B of the logic test system by the automatic transfer device 40, and is attracted to the chuck 18B provided on the logic test head 12B. In the logic test system, the chips in the wafer are tested one by one, and when all the chips are tested, the XY transfer device 30 for the logic test is performed.
B stores it in the unloading side wafer container 20.

[0028]

As described above, according to the present invention, if the IC under test is supplied to one test system, in the above-described example, the memory test system, the IC for which the test of the memory portion has been completed is automatically made to the other test system. The test is conveyed to a test system (a logic test system in the above example), and all tests of a memory portion and a logic portion are automatically executed.
This can save the time and effort of transferring the test data from one test system to the other test system, so that there is an advantage that the test time can be reduced and labor can be saved.
The order of the test is not limited to the order described above, and it is easy to understand that a method of testing the logic part first can be considered. Also, all the transfer devices for transferring wafers are X
Although the description has been made with the -Y transport device, the structure of the automatic transport device is X-
It can be easily understood that not only the Y transport device but also a belt conveyor type transport device can be used.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining an embodiment of the present invention.

FIG. 2 is a plan view for explaining another embodiment of the present invention.

FIG. 3 is a plan view for explaining a conventional memory test system.

FIG. 4 is a plan view for explaining a conventional logic test system.

FIG. 5 is a plan view illustrating a conventional system for testing a memory formed on a wafer.

FIG. 6 is a plan view illustrating a conventional system for testing a logic circuit formed on a wafer.

[Explanation of symbols]

 11A Memory test handler 11B Logic test handler 12A Memory test test head 12B Logic test head 13A Memory test tester body 13B Logic test tester body 14 Cable 15 IC under test 16 Supply tray 17 Discharge tray 18 Chuck 19 Supply-side wafer container 20 Discharge-side wafer container 30A XY transfer device for memory test 30B XY transfer device for logic test 40 Automatic transfer device provided between test systems

Claims (2)

[Claims] An automatic transfer device for transferring an IC is provided,
An IC test system for automatically transporting an IC under test to a test head by the automatic transport device and testing the IC under test with the test head includes a memory test system for testing a memory and a logic test system for testing a logic circuit. ICs that have been juxtaposed and have been tested by one test system
Characterized in that it has a structure provided with an automatic transporting device for feeding the same to the other test system. 2. An automatic transfer device for transferring a wafer having a plurality of chips on which an integrated circuit is formed, a chuck for sucking and fixing the transferred wafer, and a method for fixing the wafer fixed by the chuck. An IC test system comprising a probe electrically connected to a terminal formed on each chip, comprising: a memory system for testing a memory portion formed in the chip; and a logic portion formed in the chip. And a logic test system for testing wafers, and an automatic transfer device for transferring wafers that have been tested by one test system to the other test system between them. system.