JPH10335825A - Multilayered wiring board and its manufacture - Google Patents

Multilayered wiring board and its manufacture

Info

Publication number
JPH10335825A
JPH10335825A JP15309697A JP15309697A JPH10335825A JP H10335825 A JPH10335825 A JP H10335825A JP 15309697 A JP15309697 A JP 15309697A JP 15309697 A JP15309697 A JP 15309697A JP H10335825 A JPH10335825 A JP H10335825A
Authority
JP
Japan
Prior art keywords
wiring board
hole
holes
layer
copper foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15309697A
Other languages
Japanese (ja)
Inventor
Keiichi Kishimoto
圭一 岸本
Masaki Uemae
昌己 上前
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Carbide Industries Co Inc
Original Assignee
Nippon Carbide Industries Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Carbide Industries Co Inc filed Critical Nippon Carbide Industries Co Inc
Priority to JP15309697A priority Critical patent/JPH10335825A/en
Publication of JPH10335825A publication Critical patent/JPH10335825A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To execute drilling with a prescribed condition by electrically connecting more than three conductor layers, without matching the relative positions of the adjacent conductor layers of a through-hole and/or via holes. SOLUTION: A wiring board constituted of a through-hole 1 and the circuit of a conductor layer 2 is generated in an insulating resin layer 1 and resin body with a copper foil 3 is stacked. Copper plating is executed on the surface of copper foil 5a and the inner wall side of the holes, and via holes 12 and 16 which electrically connect the conductor layers 5 and 2 are formed. A graphitization is executed on the surface of the copper foil of a conductor layer 6, holes are formed in positions which do not match with the positions of the via holes 12 and 16 formed by the irradiation with a laser, via holes 13 and 17 which electrically connect the conductor layers 6 and 5 are formed and a circuit pattern is formed. In a multilayered wiring board which is thus generated, drilling work is easy and the reliability of electrical connections is also high.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、多層配線板のスルホー
ル、ビアホールなどの形成に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of through holes, via holes and the like in a multilayer wiring board.

【0002】[0002]

【従来の技術】近年、電子機器の小型化に伴い、銅張り
の多層配線板の小型化、高密度化、軽量化などのために
多層配線板の導体幅、導体間隙、スルホール、ビアホー
ルなどの微細化、小径化などが求められている。これら
の要求のうちスルホール、ビアホールが積層された多層
配線板の表面から加工、形成されている。
2. Description of the Related Art In recent years, with the miniaturization of electronic equipment, the conductor width, conductor gap, through hole, via hole and the like of a multilayer wiring board have been developed in order to reduce the size, density, and weight of a copper-clad multilayer wiring board. Miniaturization and small diameter are required. Of these requirements, the through hole and the via hole are processed and formed from the surface of the multilayer wiring board on which the through hole is laminated.

【0003】たとえば、積層された多層配線板の表面か
らドリルにより貫通孔をあける、ドリルにより途中まで
孔あけする。積層された多層配線板の表面からレーザに
より貫通孔、非貫通孔を形成するなどである。
[0003] For example, a through hole is drilled from the surface of a laminated multilayer wiring board by a drill, and a hole is partially drilled by a drill. For example, through holes and non-through holes are formed by laser from the surface of the laminated multilayer wiring board.

【0004】[0004]

【発明が解決しようとする課題】上記のような従来の多
層配線板の孔あけ加工の方法では製造工程に問題があ
る。ドリルによる方法においては、孔径が大きい、絶縁
層が薄い多層配線板の厚さ方向の途中で孔あけを終了す
る孔あけ加工工程が非常に難しいなどの問題がある。レ
ーザによる方法においては、積層した導体層および絶縁
樹脂層並びに内装の導体層および内装の絶縁樹脂層の孔
あけ被材料の異種層に孔あけ加工工程のレーザの加工条
件コントロールが非常に困難である問題がある。これら
の孔あけ加工工程の困難さを解決することである。
However, the conventional method for forming a hole in a multilayer wiring board as described above has a problem in the manufacturing process. In the method using a drill, there are problems such as a very large hole diameter, and a very difficult drilling process for completing the drilling in the thickness direction of a multilayer wiring board having a thin insulating layer. In the method using a laser, it is very difficult to control the processing conditions of the laser in the drilling process for different layers of the material to be drilled for the laminated conductor layer and the insulating resin layer, and for the inner conductor layer and the interior insulating resin layer. There's a problem. It is an object of the present invention to solve the difficulties of these drilling steps.

【0005】[0005]

【課題を解決するための手段】本発明は、導体層間を接
続するスルホール、ビアホールを有する3層以上の導体
層より成る多層配線板およびその製造方法において、導
体層間Aを接続するスルホールおよび/またはビアホー
ル並びに導体層間Bを接続するスルホールおよび/また
はビアホールの隣接する該導体層間Aおよび該導体層間
Bにおける相対位置が一致していなく、3層以上の導体
層の間を電気接続することであり、最外層の導体層およ
び絶縁樹脂層を孔あけする工程の繰り返しのみであり一
定の条件で孔あけできるコントロールの安易な多層配線
板およびその製造方法を提供することである。
SUMMARY OF THE INVENTION The present invention relates to a multilayer wiring board comprising three or more conductive layers having through holes and via holes for connecting conductive layers, and a method of manufacturing the same. The via holes and / or the through holes connecting the conductive layers B and / or the via holes are adjacent to each other in the conductive layer A and the conductive layer B, and the relative positions of the conductive layers A and B are not the same, and electrical connection is made between three or more conductive layers; An object of the present invention is to provide a multi-layer wiring board which can be easily formed by only repeating a step of forming a hole in an outermost conductor layer and an insulating resin layer and can be formed under certain conditions, and a method of manufacturing the same.

【0006】以下、本発明に係る多層配線板およびその
製造方法について詳述する。図1は、本発明に係る多層
配線板およびその製造方法の一実施態様を示す工程別断
面図である。図1(a)はスルホールを形成した配線基
板の断面図である。図1(b)は配線基板に絶縁樹脂層
および導体層を積層する過程の断面図である。図1
(c)は(b)で積層した絶縁樹脂層および導体層にビ
アホールを形成した断面図である。図1(d)は(c)
に絶縁樹脂層および導体層を積層し、更にビアホールを
形成した断面図である。
Hereinafter, a multilayer wiring board and a method of manufacturing the same according to the present invention will be described in detail. FIG. 1 is a cross-sectional view illustrating a multilayer wiring board and a method for manufacturing the same according to an embodiment of the present invention. FIG. 1A is a cross-sectional view of a wiring board in which a through hole is formed. FIG. 1B is a cross-sectional view showing a process of laminating an insulating resin layer and a conductor layer on a wiring board. FIG.
(C) is a sectional view in which via holes are formed in the insulating resin layer and the conductor layer laminated in (b). FIG. 1 (d) is (c)
FIG. 4 is a cross-sectional view in which an insulating resin layer and a conductor layer are laminated on each other, and a via hole is further formed.

【0007】本発明に係る多層配線板およびその製造方
法は、図1に示す如くコア・ボードとなる配線基板の所
望に応じて孔あけを行い、サブトラクティブ方法、アデ
ィティブ方法などのそれ自体公知の方法で配線パターン
を形成し、該配線基板の片面または両面に絶縁樹脂層お
よび導体層をそれ自体公知の方法で積層し、該導体層お
よび該絶縁樹脂層に該配線基板のスルホールおよび/ま
たはビアホールの位置と一致ししていない位置に孔をレ
ーザを用いて孔あけ加工し(該絶縁樹脂層の下層に位置
する配線基板の導体層を孔あけすることなく)、該孔に
無電解メッキ方法、電解メッキ方法により導体層間を電
気接続するビアホールを形成し、エッチング方法により
配線パターンを形成して多層配線板を作成する。更に、
所望により絶縁樹脂層・導体層を積層し、隣接するスル
ホールおよび/またはビアホールと一致しない位置にレ
ーザによる孔あけを行い、電気接続を行い、配線パター
ンを形成して、より層数の多い多層配線基板を作成する
ことができる。尚、隣接しない離層に形成されるスルホ
ールおよび/またはビアホールの位置は一致するまたは
一致しないでもよい。
As shown in FIG. 1, a multilayer wiring board and a method of manufacturing the same according to the present invention perform perforation as required on a wiring board serving as a core board, and employ a known method such as a subtractive method or an additive method. A wiring pattern is formed by a method, an insulating resin layer and a conductor layer are laminated on one or both surfaces of the wiring board by a method known per se, and a through hole and / or a via hole of the wiring board are formed on the conductor layer and the insulating resin layer. Hole is formed by using a laser at a position that does not coincide with the position (without drilling a conductor layer of a wiring board located below the insulating resin layer), and an electroless plating method is applied to the hole. Then, a via hole for electrically connecting the conductive layers is formed by an electrolytic plating method, and a wiring pattern is formed by an etching method to form a multilayer wiring board. Furthermore,
If necessary, an insulating resin layer and a conductor layer are laminated, a hole is formed by laser at a position that does not coincide with an adjacent through hole and / or via hole, an electric connection is made, a wiring pattern is formed, and a multilayer wiring having a larger number of layers is formed. A substrate can be created. The positions of the through holes and / or via holes formed in the non-adjacent delamination layers may or may not match.

【0008】本発明に係る多層配線板およびその製造方
法における導体層は特に限定するものではないが銅、ス
テンレス、ニクロム、タングステン、アルミニウムなど
の金属箔が好ましい。更に好ましくは、銅、ステンレス
の金属箔である。特に好ましくは、圧延銅箔、電解銅箔
であり、電解銅箔は絶縁樹脂との接着・密着により優れ
ている。また金属箔の厚みを特に限定するものではない
が0.5〜50μmであることが好ましい。更に好まし
くは1〜40μmである。特に好ましくは3〜20μm
である。このような厚みの金属箔は、柔軟でレーザ加
工、食刻が容易である。
The conductor layer in the multilayer wiring board and the method of manufacturing the same according to the present invention is not particularly limited, but is preferably a metal foil such as copper, stainless steel, nichrome, tungsten and aluminum. More preferably, it is a metal foil of copper or stainless steel. Particularly preferred are a rolled copper foil and an electrolytic copper foil, and the electrolytic copper foil is more excellent in adhesion and adhesion to an insulating resin. The thickness of the metal foil is not particularly limited, but is preferably 0.5 to 50 μm. More preferably, it is 1 to 40 μm. Particularly preferably, 3 to 20 μm
It is. The metal foil having such a thickness is flexible and easily laser-processed and etched.

【0009】本発明に係る多層配線板およびその製造方
法における絶縁樹脂層は特に限定するものではないが好
ましくは、エポキシ、ポリイミド、ボリエステル、フェ
ノール、ポリフェニレンエーテル、ポリフェニレンオキ
シド、ビスマレイミド・トリアジンなどの少なくとも一
種類を主成分とする樹脂類である。また該絶縁樹脂層
は、ガラス、アラミド、紙、多孔質ポリテトラフルオロ
エチレン、クォーツなどの不織布、織布などに樹脂類を
含浸させた絶縁樹脂でもよい。また該絶縁樹脂層には樹
脂ビーズ、アルミナ粉、酸化チタン粉、炭酸カルシウム
粉などの有機、無機の充填剤が充填されていてもよい。
The insulating resin layer in the multilayer wiring board and the method of manufacturing the same according to the present invention is not particularly limited, but is preferably at least one of epoxy, polyimide, polyester, phenol, polyphenylene ether, polyphenylene oxide, bismaleimide triazine and the like. Resins mainly composed of one type. The insulating resin layer may be an insulating resin obtained by impregnating a nonwoven fabric such as glass, aramid, paper, porous polytetrafluoroethylene, or quartz, or a woven fabric with a resin. The insulating resin layer may be filled with an organic or inorganic filler such as resin beads, alumina powder, titanium oxide powder, and calcium carbonate powder.

【0010】本発明に係る多層配線板およびその製造方
法における積層した導体層及び絶縁樹脂層への孔の形成
は、隣接する層間において下層に形成されたスルホール
および/またはビアホールの位置と一致しない位置にレ
ーザにより溶融、気化、分解などして形成することであ
る。
[0010] In the multilayer wiring board and the method of manufacturing the same according to the present invention, the formation of holes in the laminated conductor layer and insulating resin layer does not coincide with the position of the through hole and / or via hole formed in the lower layer between adjacent layers. Is formed by melting, vaporizing, decomposing, etc. by laser.

【0011】形成されるランドの形状、寸法を特に限定
するものではないが、下層部のランドは少なくとも上層
部にあける孔以上であることである。好ましくは、少な
くとも接続する層のランド幅が孔径以上で孔径に1.5
mmを加えた寸法以下でありランドの長さが下層、上層
の孔径の和の寸法以上で孔径の和の寸法に2.0mmを
加えた寸法以下である円形、楕円形、方形、菱形、ティ
アドロップ、その他変形、などである。さらに好ましく
は、ランドの長さが下層、上層の孔径の和に0.05m
mを加えた寸法以上で孔径の和に2.0mmを加えた寸
法以下である上記形状などである。特に好ましくは、接
続する層のランド幅が孔径以上で孔径に0.6mmを加
えた寸法以下でありランドの長さが下層、上層の孔径の
和の寸法に0.05mmを加えた寸法以上で孔径の和の
寸法に1.0mmを加えた寸法以下である上記形状など
である。
Although the shape and dimensions of the land to be formed are not particularly limited, it is necessary that the land in the lower layer has at least holes formed in the upper layer. Preferably, at least the land width of the layer to be connected is equal to or larger than the hole diameter, and
Circular, elliptical, square, rhombic, and tiers whose dimensions are less than or equal to the sum of the hole diameters of the lower and upper layers and less than or equal to the sum of the hole diameters plus 2.0 mm. Drop, other deformation, etc. More preferably, the length of the land is 0.05 m in the sum of the hole diameters of the lower layer and the upper layer.
The above-mentioned shape or the like having a size equal to or larger than m and equal to or smaller than a size obtained by adding 2.0 mm to the sum of the hole diameters. Particularly preferably, the land width of the layer to be connected is equal to or larger than the hole diameter and equal to or smaller than 0.6 mm plus the hole diameter, and the length of the land is equal to or larger than the sum of the hole diameters of the lower layer and the upper layer plus 0.05 mm. The above-mentioned shape or the like having a size equal to or less than a size obtained by adding 1.0 mm to the sum of the hole diameters.

【0012】レーザにより孔あけする導体層の表面処理
を特に限定するものではないか、導体層の表面にレーザ
エネルギーの吸収率の高い処理を施すことがまたは、導
体層にあらかじめ孔をあけておくことが好ましい。特に
好ましくは、導体の表面にレーザエネルギーの吸収率の
高い処理を施すことである。レーザエネルギーの吸収率
の高い処理としては、酸化ニッケル、酸化銅、酸化鉄、
などを主成分とする金属酸化物による処理、コンゴーレ
ッド、メチルバイオレットなどの染料、カーボンなどの
顔料で被覆する処理が例示できる。
The surface treatment of the conductor layer to be perforated by a laser is not particularly limited, or the surface of the conductor layer may be subjected to a treatment having a high absorption rate of laser energy, or the conductor layer may be preliminarily perforated. Is preferred. Particularly preferably, the surface of the conductor is subjected to a treatment having a high laser energy absorption rate. Treatments with high laser energy absorption include nickel oxide, copper oxide, iron oxide,
Examples of such treatment include a treatment with a metal oxide whose main component is a dye, such as Congo Red and methyl violet, and a treatment with a pigment such as carbon.

【0013】レーザの種類としては、炭酸ガスレーザ、
Xeレーザ、エキシマノーザ、YAGレーザ、Arレー
ザ、紫外線レーザなどが例示できる。レーザエネルギー
としては、導体層及び絶縁樹脂層により変化させること
ができる。
As the type of laser, a carbon dioxide laser,
An Xe laser, an excimer laser, a YAG laser, an Ar laser, an ultraviolet laser and the like can be exemplified. Laser energy can be changed by the conductor layer and the insulating resin layer.

【0014】このように作成された本発明に係る多層配
線板およびその製造方法は、隣接する下層部のスルホー
ルおよび/またはビアホールの位置と一致しない位置に
スルホールおよび/またはビアホールを形成するためレ
ーザによる孔あけ加工工程が同一条件とすることがで
き、更に電気接続の信頼性が高い。
The multilayer wiring board and the method of manufacturing the same according to the present invention, which are manufactured as described above, use a laser to form a through hole and / or a via hole at a position that does not coincide with the position of a through hole and / or a via hole in an adjacent lower layer. The drilling process can be performed under the same conditions, and the reliability of the electrical connection is high.

【0015】[0015]

【実施例】以下、本発明に係る多層配線板およびその製
造方法の実施例を説明する。尚、本発明に係る多層配線
板およびその製造方法は以下の実施例に限られるもので
はない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a multilayer wiring board and a method of manufacturing the same according to the present invention will be described below. The multilayer wiring board and the method of manufacturing the same according to the present invention are not limited to the following embodiments.

【0016】(実施例1)先ず、エポキシ樹脂1の両面
に厚さ18μmの銅箔2aをラミネートした銅張り両面
板に貫通孔11を形成し、銅箔表面および貫通孔の内壁
面にメッキ銅2bを析出させ、フォトエッチング方法に
より回路パターンを形成して絶縁樹脂層1(エポキシ樹
脂1)にスルホール11および導体層2の回路より成る
配線基板を作成した。この後、該配線基板に黒化処理を
施し酸化銅層を形成後、該酸化銅層を金属銅に化学還元
する処理を施した。図1(a)
(Embodiment 1) First, a through hole 11 is formed in a copper-clad double-sided board in which an 18 μm-thick copper foil 2a is laminated on both sides of an epoxy resin 1, and plated copper is formed on the copper foil surface and the inner wall surface of the through hole. 2b was deposited, and a circuit pattern was formed by a photo-etching method to prepare a wiring board including the circuit of the through hole 11 and the conductor layer 2 in the insulating resin layer 1 (epoxy resin 1). Thereafter, the wiring substrate was subjected to a blackening process to form a copper oxide layer, and then subjected to a process of chemically reducing the copper oxide layer to metallic copper. FIG. 1 (a)

【0017】次に、銅箔付き樹脂体3(約50μmの絶
縁樹脂層4(エポキシ樹脂)を付着させた厚み約12μ
mの銅箔5a)を該配線基板に配置・位置合わせを行い
(図1(b))積層した(圧力25Kg、温度180
度、120分)。
Next, a resin body 3 with a copper foil (about 12 μm thick with an insulating resin layer 4 (epoxy resin) of about 50 μm attached)
m copper foil 5a) was placed and aligned on the wiring substrate (FIG. 1B) and laminated (pressure 25 kg, temperature 180).
Degree, 120 minutes).

【0018】次に、スルホール11と一致しない位置の
ビアホール12用およびビアホール16用の孔の形成位
置にレーザの照射径より20μm小さい円形状の黒化処
理を該銅箔5aの表面に形成した。
Next, a circular blackening process smaller than the laser irradiation diameter by 20 μm was formed on the surface of the copper foil 5a at the positions where the holes for the via holes 12 and the via holes 16 did not coincide with the through holes 11.

【0019】次に、炭酸ガスレーザ装置の加工テーブル
に多層配線板を位置決めセットし、レーザ(パルス幅2
5μs、周波数100Hz)を照射して、銅箔5aおよ
び絶縁樹脂層4に0.1mmの孔12および孔16を孔
あけ加工した。このように形成された該孔12および該
孔16は導体層2に達しており露出該導体層2の表面は
光沢があった。
Next, the multilayer wiring board is positioned and set on the processing table of the carbon dioxide laser apparatus, and the laser (pulse width 2) is set.
Irradiation (5 μs, frequency 100 Hz) was performed to form holes 12 and 16 of 0.1 mm in the copper foil 5 a and the insulating resin layer 4. The holes 12 and the holes 16 thus formed reached the conductor layer 2, and the surface of the exposed conductor layer 2 was glossy.

【0020】次に、過マンガン酸カリウム法により該孔
12および該孔16の内部のスミア処理を行い、該銅箔
5aの表面および該孔12および該孔16の内側壁面に
銅メッキを施して導体層5および導体層2とを電気接続
したビアホール12およびビアホール16を形成し、フ
ォトエッチング方法により回路パターンを形成した。
(図1(c)))
Next, the inside of the holes 12 and 16 is smeared by the potassium permanganate method, and the surface of the copper foil 5a and the inner wall surfaces of the holes 12 and 16 are plated with copper. Via holes 12 and 16 were formed by electrically connecting the conductor layer 5 and the conductor layer 2, and a circuit pattern was formed by a photoetching method.
(Fig. 1 (c))

【0021】次に、導体層5の表面に黒化処理を施し酸
化銅層を形成後、該酸化銅層を金属銅に化学還元する処
理を施し、銅箔付き樹脂体を更に積層した。
Next, after the surface of the conductor layer 5 was subjected to a blackening treatment to form a copper oxide layer, the copper oxide layer was subjected to a chemical reduction treatment to metallic copper, and a resin body with a copper foil was further laminated.

【0022】次に、導体層6の銅箔表面の全面に黒化処
理を施し、レーザの照射によりビアホール12およびビ
アホール16の位置と一致しない位置に0.1mmの孔
13および孔17を形成した。(孔12および孔13並
びに孔16および孔17の中心間距離を0.3mmとし
た。)次に、孔の内部のスミア処理を行い銅メッキを施
し導体層6および導体層5とを電気接続するビアホール
13およびビアホール17を形成し、フォトエッチング
方法により回路パターンを形成した。(図1(d))
Next, the entire surface of the copper foil of the conductive layer 6 was subjected to blackening treatment, and 0.1 mm holes 13 and 17 were formed at positions not coincident with the positions of the via holes 12 and 16 by laser irradiation. . (The distance between the centers of the holes 12 and 13 and the holes 16 and 17 was 0.3 mm.) Then, the inside of the holes was subjected to a smearing treatment and subjected to copper plating to electrically connect the conductor layers 6 and 5 to each other. Via holes 13 and 17 were formed, and a circuit pattern was formed by a photoetching method. (Fig. 1 (d))

【0023】次に、表面の配線導体を保護するレジスト
を半田付けの領域を除いて印刷・乾燥・硬化して多層配
線板を製作した。
Next, a resist for protecting the wiring conductor on the surface was printed, dried, and cured except for the soldered area, to produce a multilayer wiring board.

【0024】このように製作された該多層配線基板は、
同一条件でビアホールを形成するのみで孔あけ加工が容
易であり電気接続の信頼性も高い。また、孔11,孔1
2、孔13のように千鳥に孔が形成されるためスルホー
ルおよび/またはビアホールの占める面積が少なく配線
密度が高密度であった。
The multilayer wiring board thus manufactured is
Drilling is easy and the reliability of electrical connection is high only by forming via holes under the same conditions. Hole 11, hole 1
2. Since holes are formed in zigzag like holes 13, the area occupied by through holes and / or via holes is small and the wiring density is high.

【0025】[0025]

【発明の効果】本発明に係る多層配線板およびその製造
方法では、各々の層における製造工程での最外層の導体
層および絶縁樹脂層に孔あけすることでありコントロー
ルが安易であり、スルホール、ビアホール形成の加工工
程の困難さを除いた、また、配線密度が高密度な多層配
線板およびその製造方法を提供できる。
In the multilayer wiring board and the method of manufacturing the same according to the present invention, the outermost conductor layer and the insulating resin layer in the manufacturing process of each layer are perforated, control is easy, and the through hole, It is possible to provide a multilayer wiring board which eliminates the difficulty of a processing step of forming a via hole and has a high wiring density and a method of manufacturing the same.

【0026】[0026]

【図面の簡単な説明】[Brief description of the drawings]

図1(a)〜(d)は、本発明に係る多層配線板および
その製造方法の一実施態様を示す工程別の断面図であ
る。
1 (a) to 1 (d) are cross-sectional views showing steps of an embodiment of a multilayer wiring board and a method of manufacturing the same according to the present invention.

【0027】[0027]

【符号の説明】[Explanation of symbols]

1 絶縁樹脂層1 2 導体層2 2a 銅箔2a 2b メッキ銅2b 3 銅箔付き樹脂体 4 絶縁樹脂層4 5 導体層5 5a 銅箔5a 6 導体層6 11 スルホール11 12 ビアホール12 13 ビアホール13 16 ビアホール16 17 ビアホール17 A 導体層間A B 導体層間B REFERENCE SIGNS LIST 1 insulating resin layer 1 2 conductor layer 2 2a copper foil 2a 2b plated copper 2b 3 resin body with copper foil 4 insulating resin layer 4 5 conductor layer 5 5a copper foil 5a 6 conductor layer 6 11 through hole 11 12 via hole 12 13 via hole 13 16 Via hole 16 17 Via hole 17 A Conductor layer A B Conductor layer B

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 導体層間を接続するスルホール、ビアホ
ールを有する3層以上の導体層より成る多層配線板およ
びその製造方法において、導体層間Aを接続するスルホ
ールおよび/またはビアホール並びに導体層間Bを接続
するスルホールおよび/またはビアホールの隣接する該
導体層間Aおよび該導体層間Bにおける相対位置が一致
していなく、3層以上の導体層の間を電気接続すること
を特徴とする多層配線板およびその製造方法。
1. A multilayer wiring board comprising three or more conductor layers having through holes and via holes connecting between conductor layers and a method of manufacturing the same, wherein the through holes and / or via holes connecting the conductor layers A and the conductor layers B are connected. A multilayer wiring board and a method of manufacturing the same, characterized in that the relative positions of the through hole and / or via hole between the adjacent conductor layers (A) and (B) do not match, and three or more conductor layers are electrically connected. .
JP15309697A 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture Pending JPH10335825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15309697A JPH10335825A (en) 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15309697A JPH10335825A (en) 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture

Publications (1)

Publication Number Publication Date
JPH10335825A true JPH10335825A (en) 1998-12-18

Family

ID=15554894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15309697A Pending JPH10335825A (en) 1997-05-28 1997-05-28 Multilayered wiring board and its manufacture

Country Status (1)

Country Link
JP (1) JPH10335825A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245122A (en) * 2005-03-01 2006-09-14 Dainippon Printing Co Ltd Wiring member and method of manufacturing wiring member

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245122A (en) * 2005-03-01 2006-09-14 Dainippon Printing Co Ltd Wiring member and method of manufacturing wiring member

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