JPH10335526A - Circuit substrate and manufacture thereof - Google Patents

Circuit substrate and manufacture thereof

Info

Publication number
JPH10335526A
JPH10335526A JP14175997A JP14175997A JPH10335526A JP H10335526 A JPH10335526 A JP H10335526A JP 14175997 A JP14175997 A JP 14175997A JP 14175997 A JP14175997 A JP 14175997A JP H10335526 A JPH10335526 A JP H10335526A
Authority
JP
Japan
Prior art keywords
insulating layer
hole conductor
metal powder
organic resin
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14175997A
Other languages
Japanese (ja)
Other versions
JP3112258B2 (en
Inventor
Shuichi Tateno
周一 立野
Koyo Hiramatsu
幸洋 平松
Katsura Hayashi
桂 林
Akihiko Nishimoto
昭彦 西本
Shigeaki Fukumoto
重昭 福元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP14175997A priority Critical patent/JP3112258B2/en
Priority to US08/937,529 priority patent/US6143116A/en
Publication of JPH10335526A publication Critical patent/JPH10335526A/en
Application granted granted Critical
Publication of JP3112258B2 publication Critical patent/JP3112258B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates

Abstract

PROBLEM TO BE SOLVED: To accomplish the state of low resistance and the long-term stability of the via hole conductor in a circuit substrate where the via hole conductor, containing metal powder, is formed on an insulate layer containing organic resin. SOLUTION: This circuit substrate comprises an insulating layer 1 containing at least thermosetting organic resin, a multiple layer conductive circuit layer 2 formed between the insulating layer 1 and a via hole conductor 3 containing at least metal powder 4 and used to connect the upper and the lower circuit layers 2. In this manufacturing method, the filling rate of the metal powder 4 can be increased by 65% or higher by pressing and heating the conductive paste after it is filled in the via holes. The organic resin contained in the insulating layer 1 is impregnated into the gap between the metal powder 4 formed by removing the junction material and/or the solution contained in the conductive paste, and the resin 5 is filled in the above-mentioned gap.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、有機樹脂を含む絶
縁層に金属粉末を含む導体ペーストを充填して形成され
たビホアール導体を具備し、半導体収納用パッケージな
どに適した回路基板とその製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board which is provided with a bifocal conductor formed by filling a conductive paste containing a metal powder into an insulating layer containing an organic resin, and is suitable for a semiconductor housing package and the like, and its manufacture. It is about the method.

【0002】[0002]

【従来の技術】従来より、多層配線基板、たとえば、半
導体素子を収納するパッケージに使用される多層配線基
板として、高密度の配線が可能なセラミック多層配線基
板が多用されている。このセラミック多層配線基板は、
アルミナなどの絶縁基板と、その表面および/または内
部にWやMo等の高融点金属を含むペーストを印刷した
り、基板に形成したビアホール内にこのペーストを充填
して絶縁基板と同時に焼成して形成された配線導体を具
備するもので、この絶縁基板の一部に半導体素子を収納
する凹部が形成され蓋体によって凹部を気密に封止され
るものである。
2. Description of the Related Art Conventionally, a ceramic multilayer wiring board capable of high-density wiring has been widely used as a multilayer wiring board, for example, a multilayer wiring board used for a package containing a semiconductor element. This ceramic multilayer wiring board
An insulating substrate such as alumina and a paste containing a high melting point metal such as W or Mo are printed on the surface and / or inside thereof, or the paste is filled into via holes formed in the substrate and fired simultaneously with the insulating substrate. The semiconductor device includes the formed wiring conductor, and a recess for housing the semiconductor element is formed in a part of the insulating substrate, and the recess is hermetically sealed by a lid.

【0003】ところが、このような絶縁基板を構成する
セラミックスは、硬くて脆い性質を有することから、製
造工程又は搬送工程において、セラミックスの欠けや割
れ等が発生しやすく、半導体素子の気密封止が損なわれ
たり、製造過程が複雑であるために、製造歩留まりが低
い等の問題があった。
However, since the ceramics constituting such an insulating substrate has a hard and brittle property, chips or cracks of the ceramics are liable to be generated in a manufacturing process or a transporting process, and the hermetic sealing of the semiconductor element is difficult. There are problems such as a low manufacturing yield due to damage or a complicated manufacturing process.

【0004】また、セラミック多層配線基板において
は、焼結前のグリーンシートに導体ペーストを印刷して
焼結させる時に、焼成収縮が生じるために、得られる基
板に反り等の変形や寸法のばらつき等が発生しやすいと
いう問題があり、回路基板の超高密度化やフリップチッ
プ等のような基板の平坦度の厳しい要求に対して、十分
に対応できないという問題があった。
Further, in a ceramic multilayer wiring board, when a conductive paste is printed on a green sheet before sintering and then sintered, shrinkage occurs, so that the resulting board has deformation such as warpage and dimensional variation. There is a problem in that it is difficult to cope with strict requirements for flatness of the substrate such as ultra-high density circuit boards and flip chips.

【0005】そこで、最近では、銅箔を接着した有機樹
脂を含む絶縁基板表面にエッチング法により微細な回路
を形成し、しかる後にこの基板を積層して多層化したプ
リント基板や、銅などの金属粉末を含むペーストを絶縁
層に印刷して配線層を形成した後、これを積層し、ある
いは積層後に、所望位置にマイクロドリルやパンチング
等によりビアホールを形成し、そのホール内壁にメッキ
法により金属を付着させて上下の配線層の接続を行う多
層プリント配線基板が提案されている。
[0005] Therefore, recently, a fine circuit is formed by etching on the surface of an insulating substrate containing an organic resin to which a copper foil is adhered, and thereafter, this substrate is laminated to form a multilayer printed circuit board or a metal such as copper. After printing a paste containing powder on the insulating layer to form a wiring layer, and then laminating, or after lamination, form a via hole at a desired position by microdrilling or punching, etc., and apply metal to the inner wall of the hole by plating. 2. Description of the Related Art A multilayer printed wiring board has been proposed in which the upper and lower wiring layers are connected by being attached thereto.

【0006】また、最近では、プリント配線基板の多層
化、配線の微細化の要求に対応して、有機樹脂を含む絶
縁層の表面に銅などの低抵抗金属を含む導体ペーストで
回路を形成し、高密度に多層化された配線基板を製造す
る試みが行われている。
Recently, in response to demands for multilayer printed wiring boards and finer wiring, a circuit is formed on the surface of an insulating layer containing an organic resin using a conductive paste containing a low-resistance metal such as copper. Attempts have been made to manufacture high-density multilayered wiring boards.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、低抵抗
金属を含む導体ペースト中には、絶縁層への印刷性を高
めるとともに、金属粉末を互いに結合させるために結合
剤及び溶剤が配合されるため、金属粉末の周囲はこの結
合剤や溶剤で囲まれており金属粉末同士の接触が悪く、
通常の銅箔や銅メッキにより形成された導体回路よりも
抵抗値が高いという問題があった。
However, in a conductor paste containing a low-resistance metal, a binder and a solvent are compounded in order to enhance the printability on the insulating layer and to bind the metal powder to each other. The surroundings of the metal powder are surrounded by this binder and solvent, and the contact between the metal powders is poor,
There is a problem that the resistance value is higher than that of a conductor circuit formed by ordinary copper foil or copper plating.

【0008】そのため、導体ペーストを印刷した後に、
結合剤及び溶剤を加熱分解したり、印刷された配線層を
加圧して緻密化することが行われている。しかしなが
ら、このようにして得られた導体配線層中においても結
合剤や溶剤を完全に除去できず、抵抗率はせいぜい7×
10-4Ω・cm程度であり、低抵抗化が困難であるとい
う欠点を有していた。また、結合剤及び溶剤を完全に除
去できても低抵抗金属粒子間に隙間が形成されるため、
この間隙に外部から水分が侵入し、金属粉末が酸化した
り、基板の温度が上昇した時に基板が破裂するなどの問
題があった。
Therefore, after printing the conductor paste,
2. Description of the Related Art A binder and a solvent are thermally decomposed, and a printed wiring layer is pressed to be densified. However, even in the conductor wiring layer thus obtained, the binder and the solvent cannot be completely removed, and the resistivity is 7 × at most.
The resistance was about 10 −4 Ω · cm, and it was difficult to reduce the resistance. Further, even if the binder and the solvent can be completely removed, a gap is formed between the low-resistance metal particles,
There is a problem that moisture invades from the outside into the gap, oxidizes the metal powder, and ruptures the substrate when the temperature of the substrate increases.

【0009】そこで、本発明は、有機樹脂を含む絶縁層
に金属粉末を含有するビアホール導体が形成された回路
基板において、ビホアール導体の低抵抗化と、長期安定
性に優れた回路基板とその製造方法を提供することを目
的とする。
In view of the above, the present invention provides a circuit board in which a via-hole conductor containing a metal powder is formed on an insulating layer containing an organic resin, the circuit board having a low resistance of the bifocal conductor, and excellent long-term stability, and a method of manufacturing the same. The aim is to provide a method.

【0010】[0010]

【課題を解決しようとする手段】本発明者らは、上記の
課題に対して検討を重ねた結果、ビアホール内に金属粉
末と結合材および溶剤を含む導体ペーストを充填した後
に、一旦加熱処理して、ペースト中の結合剤および/ま
たは溶剤を除去すると、金属粉末間には必然的に間隙が
形成されるが、その後、最終的に絶縁層の熱硬化性樹脂
を完全硬化させる際に、高圧力を付与することにより、
金属粉末の充填率を高めるとともに、絶縁層中の有機樹
脂をビアホール導体に浸み出させて金属粉末間の間隙を
その有機樹脂によって充填させることにより、ビアホー
ル導体の低抵抗化と長期安定性に優れた回路基板を提供
できるとを見いだし、本発明に至った。
Means for Solving the Problems As a result of repeated studies on the above-mentioned problems, the present inventors have conducted a heat treatment after filling a conductive paste containing a metal powder, a binder and a solvent into a via hole. Thus, when the binder and / or solvent in the paste is removed, a gap is inevitably formed between the metal powders. By applying pressure,
By increasing the filling rate of the metal powder and leaching the organic resin in the insulating layer into the via-hole conductor to fill the gap between the metal powders with the organic resin, the via-hole conductor has low resistance and long-term stability. The inventors have found that an excellent circuit board can be provided, and have reached the present invention.

【0011】即ち、本発明の回路基板は、少なくとも有
機樹脂を含む複数の絶縁層が積層され、該絶縁層表面お
よび該絶縁層間に複数層の導体回路層が形成されるとと
もに、少なくとも金属粉末を含有し、上下の異なる層の
前記導体回路層を接続するためのビアホール導体を具備
する回路基板において、前記ビアホール導体における前
記金属粉末の充填率が65%以上であり、且つ前記ビア
ホール導体中の前記金属粉末間の間隙に前記絶縁層中に
含まれる有機樹脂が充填されてなることを特徴とするも
のである。
That is, the circuit board of the present invention has a structure in which a plurality of insulating layers containing at least an organic resin are laminated, a plurality of conductive circuit layers are formed on the surface of the insulating layer and between the insulating layers, and at least a metal powder is formed. A circuit board comprising a via hole conductor for connecting the conductive circuit layers of upper and lower different layers, wherein the filling rate of the metal powder in the via hole conductor is 65% or more; An organic resin contained in the insulating layer is filled in gaps between the metal powders.

【0012】また、かかる回路基板の製造方法として、
少なくとも有機樹脂を含有する非硬化状態の絶縁層にビ
アホール形成する工程と、該ビアホール内に、金属粉
末、結合材および溶剤を含む導体ペーストを充填してビ
アホール導体を形成する工程と、前記ビアホール導体を
形成した前記絶縁層の表面に導体回路層を形成する工程
と、前記導体回路を形成した複数の絶縁層を積層する工
程と、前記ビアホール導体が形成された前記絶縁層を加
熱して少なくとも前記導体ペースト中の前記結合材およ
び/または前記溶剤を除去する工程と、前記加熱処理後
の積層された絶縁層を加圧しながら加熱して、前記ビア
ホール導体における金属粉末の充填率を65%以上に高
めるとともに前記絶縁層中の有機樹脂を前記ビアホール
導体内に含浸させて前記金属粉末間の間隙に前記有機樹
脂を充填した後、前記絶縁層と前記ビアホール導体内の
前記熱硬化性樹脂を完全硬化させる工程を具備すること
を特徴とするものである。
Further, as a method of manufacturing such a circuit board,
A step of forming a via hole in an uncured insulating layer containing at least an organic resin, a step of filling the via hole with a conductive paste containing a metal powder, a binder and a solvent to form a via hole conductor; Forming a conductive circuit layer on the surface of the insulating layer on which the conductive circuit is formed, laminating a plurality of insulating layers on which the conductive circuit is formed, and heating the insulating layer on which the via-hole conductor is formed by at least the step of: A step of removing the binder and / or the solvent in the conductor paste; and heating the laminated insulating layer after the heat treatment while applying pressure so that the filling rate of the metal powder in the via-hole conductor is 65% or more. After filling the via hole conductor with the organic resin in the insulating layer and filling the gap between the metal powders with the organic resin, It is characterized in that it comprises the step of fully curing the thermosetting resin in the via-hole conductor and the insulating layer.

【0013】望ましくは、前記非硬化状態の絶縁層中に
含まれる有機樹脂が、100℃以下の温度で500ポイ
ズ以上の粘度を有し、最小粘度が100ポイズ以下の粘
度を有すること、前記導体回路層が、転写シートの表面
に導体回路を形成し、前記絶縁層に加圧転写して形成し
たことを特徴とするものである。
Preferably, the organic resin contained in the uncured insulating layer has a viscosity of not less than 500 poise at a temperature of 100 ° C. or less, and has a minimum viscosity of 100 poise or less. The circuit layer is formed by forming a conductive circuit on the surface of a transfer sheet and transferring the circuit to the insulating layer by pressure.

【0014】[0014]

【発明の実施の形態】本発明の回路基板は、図1の概略
断面図に示すように、少なくとも熱硬化性有機樹脂を含
む複数の絶縁層1が積層され、その絶縁層1の表面およ
び絶縁層1の層間に導体回路層2が形成され、導体回路
層2が多層にわたり形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in a schematic sectional view of FIG. 1, a circuit board according to the present invention has a plurality of insulating layers 1 containing at least a thermosetting organic resin laminated thereon, and a surface of the insulating layer 1 and an insulating layer. The conductor circuit layer 2 is formed between the layers 1, and the conductor circuit layer 2 is formed over multiple layers.

【0015】そして、層の異なる導体回路層2が、ビア
ホール導体3によって電気的に接続されている。
The conductor circuit layers 2 of different layers are electrically connected by via-hole conductors 3.

【0016】絶縁層1に含まれる熱硬化性有機樹脂とし
ては、例えば、エポキシ系樹脂、トリアジン系樹脂、ポ
リブタジエン系樹脂、フェノール樹脂、フッ素系樹脂、
ジアリルフタレート系樹脂、ポリイミド系樹脂など一般
に回路基板に使用される樹脂であればなんでもよい。
The thermosetting organic resin contained in the insulating layer 1 includes, for example, an epoxy resin, a triazine resin, a polybutadiene resin, a phenol resin, a fluorine resin,
Any resin generally used for circuit boards, such as diallyl phthalate resin and polyimide resin, may be used.

【0017】また、絶縁層1中には、基板全体の強度を
高めるために、樹脂に対してフィラーを複合させるのが
望ましい。樹脂と複合されるフィラーとしては、SiO
2 、Al2 3 、ZrO2 、AlN、SiC、Si3
4 、BaTiO3 、SrTiO3 、ゼオライト、CaT
iO3 、ほう酸アルミニウム粒子等が挙げられる。ま
た、絶縁層として、ガラス繊維に樹脂を含浸させたシー
ト(プリプレグ)、アラミド不織布や織布に樹脂を含浸
させたシートなども使用できる。
In the insulating layer 1, it is desirable to combine a filler with a resin in order to increase the strength of the entire substrate. As the filler to be combined with the resin, SiO
2 , Al 2 O 3 , ZrO 2 , AlN, SiC, Si 3 N
4 , BaTiO 3 , SrTiO 3 , zeolite, CaT
iO 3 and aluminum borate particles. Further, as the insulating layer, a sheet (prepreg) in which glass fiber is impregnated with a resin, a sheet in which aramid nonwoven fabric or woven fabric is impregnated with a resin, or the like can be used.

【0018】また、本発明の回路基板のビアホール導体
3は、導体回路層2間を電気的に接続するための導電路
を形成するもので、少なくとも金属粉末を含むものであ
る。
The via-hole conductor 3 of the circuit board of the present invention forms a conductive path for electrically connecting the conductive circuit layers 2 and contains at least a metal powder.

【0019】金属粉末は、例えば、銅、銀、アルミニウ
ムおよび金の群から選ばれる少なくとも1種又は2種以
上の合金を主体とする低抵抗金属、特に、銅又は銅を含
む合金が望ましい。また、場合によっては、導体組成物
として回路の抵抗調整のためにNi−Cr合金などの高
抵抗の金属を混合、又は合金化しても良い。更に低抵抗
化のために、前記低抵抗金属よりも低融点の金属、例え
ば、半田、錫等の低融点金属を導体組成物中に含んでも
よい。
The metal powder is preferably a low-resistance metal mainly composed of at least one or two or more alloys selected from the group consisting of copper, silver, aluminum and gold, particularly copper or an alloy containing copper. In some cases, a high-resistance metal such as a Ni—Cr alloy may be mixed or alloyed as a conductor composition for adjusting the resistance of the circuit. Further, in order to lower the resistance, a metal having a lower melting point than the low-resistance metal, for example, a low-melting metal such as solder or tin may be included in the conductor composition.

【0020】また、本発明によれば、上記ビアホール導
体は、ビアホール導体内における金属粉末の充填率が6
5%以上、特に70%以上であることも大きな特徴であ
る。
According to the present invention, the via-hole conductor has a filling rate of the metal powder in the via-hole conductor of 6%.
Another significant feature is that it is 5% or more, especially 70% or more.

【0021】この充填率は、ビアホール導体の抵抗率を
決める大きな要因であり、この充填率が65%よりも低
いと導体の抵抗率が低下する。
The filling factor is a major factor in determining the resistivity of the via-hole conductor. If the filling ratio is lower than 65%, the resistivity of the conductor decreases.

【0022】さらに、本発明におけるビアホール導体
は、図2に示すように、金属粉末4の間に絶縁層1中に
含まれる熱硬化性樹脂5が充填されていることが大きな
特徴である。この熱硬化性樹脂5の充填により、外部か
ら水分が侵入して金属粉末が酸化することがなく、ま
た、基板温度が上昇した場合に間隙の膨張によって基板
が破損することもない。
Further, as shown in FIG. 2, the via-hole conductor according to the present invention is characterized in that the thermosetting resin 5 contained in the insulating layer 1 is filled between the metal powders 4. By filling the thermosetting resin 5, moisture does not enter from the outside to oxidize the metal powder, and the substrate is not damaged by expansion of the gap when the substrate temperature increases.

【0023】次に、本発明の回路基板の製造方法につい
て説明する。まず、絶縁層として、前述したような熱硬
化性有機樹脂、または熱硬化性有機樹脂とフィラーから
なる組成物を混練機や3本ロールなどの手段によって十
分に混合し、これを圧延法、押し出し法、射出法、ドク
ターブレード法などによってシート状に成形した後、熱
硬化性樹脂を半硬化させる。半硬化には、樹脂が完全硬
化するに十分な温度よりもやや低い温度に加熱すればよ
い。
Next, a method of manufacturing a circuit board according to the present invention will be described. First, as an insulating layer, a thermosetting organic resin as described above, or a composition comprising a thermosetting organic resin and a filler is sufficiently mixed by means of a kneader, a three-roll mill, or the like. After molding into a sheet by a method, injection method, doctor blade method or the like, the thermosetting resin is semi-cured. For semi-curing, the resin may be heated to a temperature slightly lower than a temperature sufficient to completely cure the resin.

【0024】そして、この半硬化状態の絶縁層に対し
て、ビアホールを形成する。このビアホールの形成は、
ドリル、パンチング、サンドブラスト、あるいは炭酸ガ
スレーザ、YAGレーザ、及びエキシマレーザ等の照射
による加工など公知の方法が採用される。
Then, via holes are formed in the semi-cured insulating layer. The formation of this via hole
A known method such as drilling, punching, sandblasting, or processing by irradiation with a carbon dioxide gas laser, a YAG laser, an excimer laser, or the like is employed.

【0025】その後、そのビアホール内に導体ペースト
を充填してビアホール導体を形成する。導体ペースト
は、前述したような金属粉末に対して、結合剤および溶
剤を添加混合して調製される。ペースト中に添加される
結合剤としては、セルロース等の有機樹脂が用いられ、
溶剤としては、用いる結合剤が溶解可能な溶剤であれば
よく、例えば、イソプロピルアルコール、テルピネオー
ル、2−オクタノール、ブチルカルビトールアセテート
等が用いられる。
Thereafter, a conductive paste is filled into the via hole to form a via hole conductor. The conductor paste is prepared by adding and mixing a binder and a solvent to the metal powder as described above. As a binder added to the paste, an organic resin such as cellulose is used,
The solvent may be any solvent in which the binder used can be dissolved, and for example, isopropyl alcohol, terpineol, 2-octanol, butyl carbitol acetate and the like are used.

【0026】次に、ビアホール導体を形成した前記絶縁
層の表面に導体回路層を形成する。
Next, a conductive circuit layer is formed on the surface of the insulating layer on which the via-hole conductor has been formed.

【0027】導体回路層を形成する方法としては、銅等
の金属箔を絶縁層に接着剤で張りつけた後に、回路パタ
ーンのレジストを形成して酸等によって非レジスト領域
の金属をエッチング除去しレジストを除去する方法、予
め打ち抜きした金属箔を張りつける方法、絶縁層の表面
に、前記ビアホール中に充填したような導体ペーストを
用いて回路パターンにスクリーン印刷する方法、フィル
ム、ガラス、金属板などの転写媒体表面にメッキ法や金
属箔を接着して金属層を形成し、これをエッチングによ
り導体回路層を形成し、その後、転写媒体を絶縁層上に
加圧しながら導体回路層を転写する方法、などが採用さ
れる。そして、上記のようにしてビアホール導体および
導体回路層が形成された複数の絶縁層を位置合わせして
所望の枚数積層圧着する。
As a method of forming a conductive circuit layer, a metal foil such as copper is adhered to an insulating layer with an adhesive, a resist of a circuit pattern is formed, and a metal in a non-resist region is removed by etching with an acid or the like. , Method of attaching a pre-punched metal foil, method of screen-printing a circuit pattern on the surface of an insulating layer using a conductive paste filled in the via hole, transfer of film, glass, metal plate, etc. A metal layer is formed by plating or bonding a metal foil to the surface of the medium, a conductive circuit layer is formed by etching the metal layer, and then the conductive circuit layer is transferred while pressing the transfer medium onto the insulating layer. Is adopted. Then, the plurality of insulating layers on which the via-hole conductors and the conductive circuit layers are formed as described above are aligned, and a desired number of layers are laminated and pressed.

【0028】また、ビアホール導体を形成した絶縁層を
加熱して、ビアホール導体中の結合剤および/または溶
剤を分解除去する。この時の加熱温度は、結合剤および
溶剤の種類によって適宜調整されるが、絶縁層中の熱硬
化性樹脂が硬化しない温度で行われる。この処理によっ
て、ビアホール導体中の結合剤および/または溶剤が除
去される結果、ビアホール導体中の金属粉末間には間隙
が必然的に形成されることになる。
Further, the insulating layer on which the via-hole conductor is formed is heated to decompose and remove the binder and / or the solvent in the via-hole conductor. The heating temperature at this time is appropriately adjusted depending on the types of the binder and the solvent, but is performed at a temperature at which the thermosetting resin in the insulating layer is not cured. This treatment removes the binder and / or the solvent in the via-hole conductor, so that a gap is necessarily formed between the metal powders in the via-hole conductor.

【0029】なお、このビアホール導体中の結合剤およ
び/または溶剤を分解除去する工程は、導体ペーストを
絶縁層のビアホール内に充填した後、導体回路層を形成
する直前、または導体回路層およびビアホール導体が形
成された絶縁層を積層する直前に行ってもよい。
The step of decomposing and removing the binder and / or the solvent in the via-hole conductor is performed by filling the conductor paste into the via-hole of the insulating layer, immediately before forming the conductor circuit layer, or in the conductor circuit layer and the via-hole. This may be performed immediately before laminating the insulating layer on which the conductor is formed.

【0030】その後、上記処理後の積層体に対して、圧
力を印加した状態で、絶縁層中の熱硬化性樹脂が硬化す
るに十分な温度まで昇温する。この加熱加圧処理によっ
て、ビアホール導体における金属粉末の充填率を高める
とともに、ビアホール導体の側壁から熱硬化性樹脂をビ
アホール導体の金属粉末間の間隙に浸み出させて充填す
るとともに、硬化温度にてビアホール導体に充填された
熱硬化性樹脂と、絶縁層中の熱硬化性樹脂を完全硬化す
る。
Thereafter, the temperature of the laminated body after the above-mentioned treatment is raised to a temperature sufficient to cure the thermosetting resin in the insulating layer while applying pressure. By this heating and pressurizing treatment, the filling rate of the metal powder in the via-hole conductor is increased, and the thermosetting resin is leached from the side wall of the via-hole conductor into the gap between the metal powders of the via-hole conductor and filled, and the curing temperature is reduced. Then, the thermosetting resin filled in the via hole conductor and the thermosetting resin in the insulating layer are completely cured.

【0031】この時の加熱温度は、用いる有機樹脂によ
るが、150〜300℃の温度で行われる。また、この
時の積層体を加圧する時の圧力は、ビアホール導体への
金属粉末の充填率を高めるとともに、ビアホール導体内
の間隙へ絶縁層中の有機樹脂が浸み出して充填されるに
十分な圧力が付与され、望ましくは、20〜150kg
/cm2 の圧力が付与される。なお、この加熱加圧処理
によるビアホール導体内の金属粉末の充填率が65%以
上、特に70%以上とすることにより、ビアホール導体
を低抵抗化することができる。
The heating temperature at this time depends on the organic resin used, but the heating is performed at a temperature of 150 to 300 ° C. In addition, the pressure when pressing the laminate at this time is sufficient to increase the filling rate of the metal powder into the via-hole conductor and to allow the organic resin in the insulating layer to leach and fill the gap in the via-hole conductor. Pressure is applied, desirably 20 to 150 kg
/ Cm 2 is applied. By setting the filling rate of the metal powder in the via-hole conductor by the heating and pressurizing treatment to 65% or more, particularly 70% or more, the resistance of the via-hole conductor can be reduced.

【0032】本発明によれば、この加熱加圧処理により
ビアホール導体内の間隙への有機樹脂の充填性を高める
上で、この時の絶縁層中に含まれる熱硬化性樹脂の粘度
が、100℃以下で500ポイズ以上であること、さら
には、最小粘度が100ポイズ以下であることが望まし
い。
According to the present invention, in order to enhance the filling property of the organic resin into the gap in the via-hole conductor by the heating and pressurizing treatment, the viscosity of the thermosetting resin contained in the insulating layer at this time is set to 100. It is desirable that the temperature be 500 ° C. or less at a temperature of not more than 100 ° C.

【0033】これは、100℃以下での粘度が500ポ
イズよりも小さい場合、導体ペーストに含まれる結合剤
及び溶剤を除去する工程で絶縁層中の樹脂がビアホール
導体中に浸み出し、ビアホール導体中の金属粉末と金属
粉末との間まで侵入してしまう結果、金属粉末同士の接
続性を損ね、さらには、その後の加圧加熱による樹脂硬
化時に、ビアホール導体に間隙が存在しないためにビア
ホール導体に高圧力を印加しても、金属粉末の充填率を
高めることができず、抵抗率を下げることができない。
When the viscosity at 100 ° C. or less is less than 500 poise, the resin in the insulating layer oozes into the via-hole conductor in the step of removing the binder and the solvent contained in the conductor paste, and the via-hole conductor As a result, the metal powder invades between the metal powders, thereby deteriorating the connectivity between the metal powders.Furthermore, when the resin is cured by pressurizing and heating, there is no gap in the via hole conductor. However, even if a high pressure is applied, the filling rate of the metal powder cannot be increased, and the resistivity cannot be decreased.

【0034】また、最小粘度が100ポイズよりも高い
と、加圧しながら絶縁層中の熱硬化性樹脂の硬化温度ま
で昇温する過程で、絶縁層中の熱硬化性樹脂がビアホー
ル導体に侵入しにくくなり、金属粉末間の間隙を充填す
ることが難しくなるためである。また、加圧することな
く、硬化温度にて硬化させた場合においても、絶縁層中
の熱硬化性樹脂がビアホール導体に侵入しにくくなる。
If the minimum viscosity is higher than 100 poise, the thermosetting resin in the insulating layer penetrates into the via-hole conductor during the process of raising the temperature to the curing temperature of the thermosetting resin in the insulating layer while applying pressure. This is because it becomes difficult to fill the gap between the metal powders. Further, even when the resin is cured at a curing temperature without applying pressure, the thermosetting resin in the insulating layer does not easily enter the via-hole conductor.

【0035】また、この加熱加圧処理によりビアホール
導体内の間隙への有機樹脂の充填性を高める上で、ビア
ホール導体に接続する導体回路層を、金属箔によって形
成すること、とりわけ、転写シートの表面に金属箔から
なる導体回路層を形成し、前記絶縁層に加圧転写して形
成することにより、ビアホール導体周辺への加圧力を高
めることができ、金属粉末同士の接触力を高めるととも
にビアホール導体における金属粉末の充填率を高めビア
ホール導体の低抵抗化を図ることができる。
Further, in order to enhance the filling property of the organic resin into the gaps in the via-hole conductors by the heating and pressurizing treatment, the conductor circuit layer connected to the via-hole conductors is formed of a metal foil. By forming a conductive circuit layer made of a metal foil on the surface and pressing and transferring the conductive circuit layer to the insulating layer, it is possible to increase the pressure applied to the periphery of the via-hole conductor, thereby increasing the contact force between the metal powders and the via-hole. The filling rate of the metal powder in the conductor can be increased, and the resistance of the via-hole conductor can be reduced.

【0036】[0036]

【実施例】粘度特性が表1の各種ポリイミド樹脂に、フ
ィラーとしてSiO2 粉末を60体積%混合し、ドクタ
ーブレード法で厚み100μmのシート状に成形し絶縁
層を作製した。なお、試料No.3および10のポリイミ
ド樹脂の粘度と温度との関係を図3に示した。
EXAMPLE 60% by volume of SiO 2 powder as a filler was mixed with various polyimide resins having the viscosity characteristics shown in Table 1 as a filler, and formed into a sheet having a thickness of 100 μm by a doctor blade method to form an insulating layer. FIG. 3 shows the relationship between the viscosity and the temperature of the polyimide resins of Sample Nos. 3 and 10.

【0037】この絶縁層へ、ビーム径20μmのYAG
レーザ光を照射、走査し直径100μmのビアホールを
形成した。そして、形成したビアホールへ、平均粒径5
μmのAgとCuの合金粉末に結合剤としてエチルセル
ロースを1重量%、溶剤として2−オクタノールを6重
量%混合して作製した導体ペーストをスクリーン印刷法
にて充填した。
A 20 μm beam diameter YAG
Laser light irradiation and scanning were performed to form a via hole having a diameter of 100 μm. Then, an average particle size of 5
A conductor paste prepared by mixing 1% by weight of ethyl cellulose as a binder and 6% by weight of 2-octanol as a solvent was mixed with a μm Ag-Cu alloy powder by a screen printing method.

【0038】そして、PETフィルムからなる転写シー
トに厚さ12μmの銅箔を貼り付けた後、エッチング法
により導体回路層を形成し、絶縁層に100kg/cm
2 の圧力をかけて導体回路層を絶縁層に転写させた。そ
の後、同様にして作製した4枚の絶縁層を積層した。
Then, after a copper foil having a thickness of 12 μm is attached to a transfer sheet made of a PET film, a conductive circuit layer is formed by an etching method, and the insulating layer is formed to a thickness of 100 kg / cm.
The conductor circuit layer was transferred to the insulating layer by applying a pressure of 2 . Thereafter, four insulating layers produced in the same manner were laminated.

【0039】上記のようにして作製した積層体に対し
て、120℃で3時間、窒素中で加熱処理して、絶縁層
中の溶剤、およびビアホール導体中の結合剤と溶剤を除
去した。しかる後に、70kg/cm2 の圧力を印加し
ながら各樹脂の硬化温度まで昇温した後、硬化温度で2
時間保持し、熱硬化性樹脂を完全硬化させ、回路基板を
得た。
The laminate prepared as described above was subjected to heat treatment at 120 ° C. for 3 hours in nitrogen to remove the solvent in the insulating layer and the binder and the solvent in the via-hole conductor. Thereafter, the temperature was raised to the curing temperature of each resin while applying a pressure of 70 kg / cm 2 , and then the curing temperature was increased to 2 kg / cm 2.
After holding for a while, the thermosetting resin was completely cured to obtain a circuit board.

【0040】なお、上記の工程において、120℃での
熱処理後に、ビアホール導体中の金属粉末間の間隙の形
成の有無についてSEM写真により観察した。また、2
50℃での完全硬化後のビアホール導体の観察を行い、
金属粉末間の間隙への樹脂の充填の有無をSEM観察し
た。結果は、表1に示した。また、ビアホール導体にお
ける金属粉末の充填率を測定した。この充填率は、ビア
ホール導体の断面をSEM写真により観察して、ビアホ
ール導体中央部における金属粉末の面積占有率を画像解
析して求め、これを充填率とした。また、ビアホール導
体の完全硬化後の抵抗率を4端子法により測定した。さ
らに、ビアホール導体の長期安定性について、85℃、
湿度85%の雰囲気に168時間保持した後のビアホー
ル導体の抵抗率を測定しその結果を表1に示した。
In the above process, after heat treatment at 120 ° C., the presence or absence of the formation of the gap between the metal powders in the via-hole conductor was observed by an SEM photograph. Also, 2
Observe the via-hole conductor after complete curing at 50 ° C,
The presence or absence of resin filling in the gap between the metal powders was observed by SEM. The results are shown in Table 1. The filling rate of the metal powder in the via-hole conductor was measured. The filling rate was determined by observing the cross section of the via-hole conductor with an SEM photograph and analyzing the area occupancy of the metal powder in the central portion of the via-hole conductor by image analysis. The resistivity of the via-hole conductor after complete curing was measured by a four-terminal method. Further, regarding the long-term stability of the via-hole conductor,
The resistivity of the via-hole conductor after being kept in an atmosphere of 85% humidity for 168 hours was measured, and the results are shown in Table 1.

【0041】また、比較として、完全硬化時に加圧する
ことなく、250℃で完全硬化する以外は上記と全く同
様にして回路基板を作製し、上記と同様に評価を行っ
た。
For comparison, a circuit board was prepared in exactly the same manner as described above except that the circuit board was completely cured at 250 ° C. without applying pressure at the time of complete curing, and evaluated in the same manner as described above.

【0042】[0042]

【表1】 [Table 1]

【0043】表1によれば、本発明の請求範囲内の実施
例は、120℃処理後にビアホール導体中の金属粉末間
に間隙が形成されており、また、加圧加熱処理による最
終硬化後に導体金属粉末同士が強固に接触し金属粉末の
充填率が65%であり、また金属粉末間に存在していた
間隙に樹脂が充填されていることが確認された。その結
果、本発明によるビアホール導体は、初期抵抗率がいず
れも3×10-5Ω・cm以下であり、しかも、高温多湿
中に長期間保持されても、ビアホール導体中の金属粉末
が酸化することなく、抵抗変化がほとんどなく3×10
-5Ω・cm以下が達成されており、長期安定性に優れて
いることがわかった。
According to Table 1, in the examples within the scope of the present invention, a gap is formed between the metal powders in the via-hole conductor after the treatment at 120 ° C. It was confirmed that the metal powders were in strong contact with each other, the filling ratio of the metal powder was 65%, and that the gaps between the metal powders were filled with the resin. As a result, the via-hole conductor according to the present invention has an initial resistivity of not more than 3 × 10 −5 Ω · cm, and the metal powder in the via-hole conductor is oxidized even if it is kept in a high-temperature and high-humidity state for a long time. 3 × 10 with almost no change in resistance
-5 Ω · cm or less was achieved, and it was found to be excellent in long-term stability.

【0044】これに対して、絶縁層を構成する熱硬化性
樹脂として、非硬化状態の絶縁層中に含まれる有機樹脂
の100℃以下での粘度が500ポイズよりも小さい樹
脂を用いた試料No.1、2、3、4は、120℃処理
後、絶縁層中の樹脂がビアホール導体中に浸み出してお
り、また加圧加熱処理後においても金属粉末の充填率が
65%未満と小さく、その結果、ビアホール導体の抵抗
が大きいものであった。
On the other hand, as a thermosetting resin constituting the insulating layer, a sample No using a resin having a viscosity at 100 ° C. or less of less than 500 poise of the organic resin contained in the uncured insulating layer. .1, 2, 3, and 4 show that the resin in the insulating layer oozes into the via-hole conductor after the treatment at 120 ° C. As a result, the resistance of the via-hole conductor was large.

【0045】また、最小粘度が100ポイズよりも高い
試料No.13では、加圧加熱処理後、ビアホール導体中
の間隙に樹脂の充填が行われず、高温多湿雰囲気での熱
処理後に抵抗が増大しビアホール導体の抵抗が初期およ
び高温多湿雰囲気中での処理後において3×10-5Ω・
cm以下を達成できなかった。
In sample No. 13 having a minimum viscosity of more than 100 poise, no resin was filled in the via-hole conductor after pressurized heat treatment, and the resistance increased after heat treatment in a high-temperature and high-humidity atmosphere. The resistance of the conductor is 3.times.10.sup.- 5 .OMEGA.
cm or less could not be achieved.

【0046】さらに、完全硬化時に全く加圧処理を行わ
なかった試料No.14では、金属粉末の充填率が低く、
しかも、ビアホール導体内に間隙が残存しており、初期
抵抗が3×10-5Ω・cmを越え、しかも高温多湿中で
の処理により抵抗率はさらに増大した。
Further, in Sample No. 14 in which no pressure treatment was performed at the time of complete curing, the filling ratio of the metal powder was low,
In addition, a gap remains in the via-hole conductor, the initial resistance exceeds 3 × 10 −5 Ω · cm, and the resistivity is further increased by the treatment in a high-temperature and high-humidity environment.

【0047】[0047]

【発明の効果】以上詳述したように、本発明によれば、
ビアホール導体における金属粉末の充填率を高めるとと
もに、金属粉末間の間隙に絶縁層中の熱硬化性樹脂を充
填することにより、ビアホール導体の低抵抗化を実現す
るとともに、水分の侵入や基板が高温になったときの破
裂等のない信頼性の高い回路基板が提供できる。
As described in detail above, according to the present invention,
By increasing the filling rate of the metal powder in the via-hole conductor, and filling the gap between the metal powders with a thermosetting resin in the insulating layer, the resistance of the via-hole conductor is reduced, and the penetration of moisture and high temperature of the substrate Thus, a highly reliable circuit board free from rupture or the like can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の回路基板の構造の一例を示した概略断
面図である。
FIG. 1 is a schematic sectional view showing an example of the structure of a circuit board of the present invention.

【図2】本発明の回路基板におけるビアホール導体の組
織構造を説明するための図である。
FIG. 2 is a diagram for explaining a structure of a via-hole conductor in the circuit board of the present invention.

【図3】実施例において絶縁層に使用される熱硬化性樹
脂(No.3、No.10)の粘度と温度との関係を湿した
図である。
FIG. 3 is a diagram showing the relationship between viscosity and temperature of thermosetting resins (No. 3 and No. 10) used for an insulating layer in Examples;

【符号の説明】[Explanation of symbols]

1 絶縁層 2 導体回路層 3 ビアホール導体 4 金属粉末 5 熱硬化性樹脂 DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Conductor circuit layer 3 Via-hole conductor 4 Metal powder 5 Thermosetting resin

フロントページの続き (72)発明者 西本 昭彦 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内 (72)発明者 福元 重昭 鹿児島県国分市山下町1番4号 京セラ株 式会社総合研究所内Continuing from the front page (72) Inventor Akihiko Nishimoto 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Prefecture Inside the Kyocera Research Institute (72) Inventor Shigeaki Fukumoto 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Kyocera Corporation In the laboratory

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】少なくとも熱硬化性有機樹脂を含む絶縁層
と、該絶縁層表面および該絶縁層間に形成された複数層
の導体回路層と、少なくとも金属粉末を含有し、前記上
下の導体回路層を接続するためのビアホール導体を具備
する回路基板において、前記ビアホール導体における前
記金属粉末の充填率が65%以上であり、前記ビアホー
ル導体中の前記金属粉末間の間隙に前記絶縁層中に含ま
れる前記有機樹脂が充填されていることを特徴とする回
路基板。
An insulating layer containing at least a thermosetting organic resin, a plurality of conductive circuit layers formed on the surface of the insulating layer and between the insulating layers, and the upper and lower conductive circuit layers containing at least metal powder. In the circuit board having the via hole conductor for connecting the via holes, the filling rate of the metal powder in the via hole conductor is 65% or more, and the insulating layer is included in the gap between the metal powders in the via hole conductor. A circuit board filled with the organic resin.
【請求項2】少なくとも熱硬化性有機樹脂を含有する非
硬化状態の絶縁層にビアホール形成する工程と、該ビア
ホール内に、金属粉末、結合材および溶剤を含む導体ペ
ーストを充填してビアホール導体を形成する工程と、前
記ビアホール導体を形成した前記絶縁層の表面に導体回
路層を形成する工程と、前記導体回路および前記ビアホ
ール導体を形成した複数の絶縁層を積層する工程と、前
記絶縁層を加熱して少なくとも前記導体ペースト中の前
記結合材および/または前記溶剤を除去する工程と、前
記加熱処理後の積層された絶縁層を加圧しながら加熱し
て、前記ビアホール導体における金属粉末の充填率を6
5%以上に高めるとともに前記絶縁層中の前記熱硬化性
有機樹脂を前記ビアホール導体内に含浸させて前記金属
粉末間の間隙に前記有機樹脂を充填した後、前記絶縁層
と前記ビアホール導体内の前記熱硬化性樹脂を完全硬化
させる工程を具備することを特徴とする回路基板の製造
方法。
2. A step of forming a via hole in an uncured insulating layer containing at least a thermosetting organic resin, and filling the via hole with a conductive paste containing a metal powder, a binder and a solvent to form a via hole conductor. Forming, forming a conductive circuit layer on the surface of the insulating layer on which the via-hole conductor is formed, laminating a plurality of insulating layers on which the conductive circuit and the via-hole conductor are formed, and forming the insulating layer A step of heating to remove at least the binder and / or the solvent in the conductor paste; and heating the laminated insulating layer after the heat treatment while applying pressure to fill the via-hole conductor with the metal powder. 6
After increasing to 5% or more, the thermosetting organic resin in the insulating layer is impregnated in the via hole conductor to fill the gap between the metal powders with the organic resin, and then the insulating layer and the via hole conductor are filled. A method for manufacturing a circuit board, comprising a step of completely curing the thermosetting resin.
【請求項3】前記絶縁層中に含まれる有機樹脂の、非硬
化状態での100℃以下の粘度が500ポイズ以上であ
り、最小粘度が100ポイズ以下の粘度を有することを
特徴とする請求項2記載の回路基板の製造方法。
3. The organic resin contained in the insulating layer has a viscosity at 100 ° C. or less in an uncured state of 500 poise or more and a minimum viscosity of 100 poise or less. 3. The method for manufacturing a circuit board according to 2.
【請求項4】前記導体回路層が、転写シートの表面に導
体回路を形成し、前記絶縁層に加圧転写して形成したこ
とを特徴とする請求項2記載の回路基板の製造方法。
4. The method according to claim 2, wherein the conductive circuit layer is formed by forming a conductive circuit on a surface of a transfer sheet and transferring the conductive circuit to the insulating layer by pressure.
JP14175997A 1996-09-26 1997-05-30 Circuit board and its manufacturing method Expired - Fee Related JP3112258B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP14175997A JP3112258B2 (en) 1997-05-30 1997-05-30 Circuit board and its manufacturing method
US08/937,529 US6143116A (en) 1996-09-26 1997-09-25 Process for producing a multi-layer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14175997A JP3112258B2 (en) 1997-05-30 1997-05-30 Circuit board and its manufacturing method

Publications (2)

Publication Number Publication Date
JPH10335526A true JPH10335526A (en) 1998-12-18
JP3112258B2 JP3112258B2 (en) 2000-11-27

Family

ID=15299536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14175997A Expired - Fee Related JP3112258B2 (en) 1996-09-26 1997-05-30 Circuit board and its manufacturing method

Country Status (1)

Country Link
JP (1) JP3112258B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001039561A1 (en) * 1999-11-26 2001-05-31 Matsushita Electric Industrial Co., Ltd. Wiring board and production method thereof
JP2008198964A (en) * 2007-01-19 2008-08-28 Sumitomo Electric Ind Ltd Printed wiring board and method for manufacturing the same
KR101153492B1 (en) * 2010-08-24 2012-06-11 삼성전기주식회사 Manufacturing method for ceramic substrate for probe card and ceramic substrate for probe card
JPWO2015147219A1 (en) * 2014-03-27 2017-04-13 住友電気工業株式会社 Printed wiring board substrate, printed wiring board, and printed wiring board manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001039561A1 (en) * 1999-11-26 2001-05-31 Matsushita Electric Industrial Co., Ltd. Wiring board and production method thereof
US6774316B1 (en) 1999-11-26 2004-08-10 Matsushita Electric Industrial Co., Ltd. Wiring board and production method thereof
JP2008198964A (en) * 2007-01-19 2008-08-28 Sumitomo Electric Ind Ltd Printed wiring board and method for manufacturing the same
US8866027B2 (en) 2007-01-19 2014-10-21 Sumitomo Electric Industries, Ltd. Printed wiring board and method for manufacturing the same
TWI462666B (en) * 2007-01-19 2014-11-21 Sumitomo Electric Industries Printed circuit board and method for manufacturing the same
KR101153492B1 (en) * 2010-08-24 2012-06-11 삼성전기주식회사 Manufacturing method for ceramic substrate for probe card and ceramic substrate for probe card
JPWO2015147219A1 (en) * 2014-03-27 2017-04-13 住友電気工業株式会社 Printed wiring board substrate, printed wiring board, and printed wiring board manufacturing method

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