JPH103285A - Decoder circuit and liquid crystal driving circuit using the decoder circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoder circuit in which inputted digital data are decoded using fewer number of FETs and the voltages of output signals are boosted. SOLUTION: Sources S of NchFETs 4 and 7 are grounded and respective drains D of the FETs 4 and 7 are connected to respective sources S of NchFETs 5, 6, 8 and 9. Digital data IN2 and their inversion signals are inputted to gates G of the FETs 4 and 7 and digital data IN1 and their inversion signals are inputted to the gates G of the FETs 5, 8, 6 and 9. Moreover, a voltage VDDH are applied to sources S of PchFETs 10 to 21 and three of each drain D of PchFETs 10 to 21 are connected to drains D of the FETs 5, 6 and 8 and these connected points become the output terminals of decode signals Y1 to Y4. When the connected NchFETs are turned off, the FETs 10 to 21 supply the voltages VDDH to each output terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder circuit for decoding input digital data, and more particularly to a decoder circuit used for a driving circuit of a liquid crystal display.

[0002]

2. Description of the Related Art Conventionally, there are an analog type and a digital type as a gradation control method in a liquid crystal display.
In a liquid crystal display for automation) equipment, digital gradation control is generally performed. In this digital gradation control, different specific gradation voltages are prepared in advance by the number of gradations to be controlled in advance, and one of the specific gradation voltages is selected according to digital data input from the outside. Is applied to each liquid crystal cell constituting the liquid crystal display. Then, gradation control is performed by changing the angle of the liquid crystal molecules of the liquid crystal cell according to the applied voltage. Generally, in a driving circuit of a liquid crystal display that performs gradation control, selection of a specific gradation voltage based on input digital data is performed using a decoder circuit. Also, in this type of decoder circuit,
Mainly to improve the display speed of the liquid crystal display,
The high level voltage on the output side is boosted and output higher than that on the input side.

FIG. 9 shows an example of a conventional configuration of the above-described decoder circuit. In this figure, (a) is a connection diagram showing the configuration of the decoder circuit, and (b) is a truth table of the decoder circuit. In FIG. 9A, 100
Reference numerals a and 100b denote level shift circuits each having a non-inverting input terminal IN, an inverting input terminal * IN, a non-inverting output terminal OUT,
It has four inverted output terminals * OUT. here,
In digital data input to the level shift circuits 100a and 100b, "0" is represented by a ground potential, and "1" is represented by three.
It is represented by a voltage of V. This level shift circuit 10
0a and 100b are input signals IN1 or IN1, respectively.
When "2" is "1", "1" is supplied to the non-inverting input terminal IN, and inverters 101a and 101 are supplied to the inverting input terminal * IN.
When "0" is input through the input terminal 1b, the non-inverting output terminal O
"1" is output from the UT and "0" is output from the inverted output terminal * OUT.

Here, the level shift circuits 100a, 100
On the output side of 0b, "1" is boosted to a voltage of 10V, and "0" is represented by the ground potential as in the case of the input side. Then, “0” is input to the non-inverting input terminal IN,
When "1" is input to the inverting input terminal * IN, "0" changes from the non-inverting output terminal OUT to the inverting output terminal * OU.
T outputs “1” (10 V). The level shift circuits 100a and 100b include two N-channel field effect transistors (hereinafter, referred to as N
chFETs) 120 and 121 and four P-channel field-effect transistors (hereinafter referred to as PchFETs)
122, 123, 124, and 125, respectively.

Reference numerals 102 to 105 denote two-input NAND gates driven by a voltage of 10 V. The inputs of the respective NAND gates are connected to respective output terminals of the level shift circuits 100a and 100b as shown in FIG.
a, 100b, “0” is always output from one of the NAND gates and the other three NAs
"1" is output from the ND gate. 106-109
Denotes an inverter, which is driven by a voltage of 10 V like the NAND gates 102 to 105,
The logic of the signal output from 105 is inverted and output.

The operation of the above-described decoder circuit is shown in FIG.
As can be seen from the truth table of (b), the input 2-bit digital data IN1 (least significant bit), IN2
And outputs the result in positive logic. Further, the voltage of “1” output from the decoding circuit has been boosted to 10V. Then, a voltage of a specific gradation selected according to the above-described decoding result is applied to each liquid crystal cell of the liquid crystal display, thereby performing gradation control.

[0007]

The number of FETs used in the above-described decoder circuit is, for example, that each inverter is composed of two FETs and each NAND gate is 4 FETs.
In the case of a configuration with two FETs, a total of 2 × 6 (inverter) + 4 × 4 (NAND gate) + 6 × 2 (level shift circuit) = 40. Here, in order to display a full color (16,777,216 colors) on the liquid crystal display, it is necessary to perform 256 gradation control for each of red, green, and blue colors. Therefore, the number of bits of image data is one color. 8 bits per address. When this is realized by the above-described decoder circuit, the total number of FETs is 3 (red, green, blue) ×
{2 × 264 (inverter) + 4 × 256 (NAND gate) + 6 × 8 (level shift circuit)} = 4800.

The above-described decoder circuits are provided in a number corresponding to the resolution of the liquid crystal display. Further, circuits other than the decode circuits (for example, a circuit for generating a voltage of a specific gradation, If a switch circuit for applying a voltage of a specific gradation to the liquid crystal cell according to the result is included, the number of FETs of the drive circuit used in one liquid crystal display becomes enormous. For this reason, when the driving circuit of the liquid crystal display is formed into an LSI, there is a problem that the manufacturing process is complicated and the yield is reduced. In addition, in terms of miniaturization of liquid crystal displays,
The reduction in the area of the LSI chip is an important point, and the reduction in the number of FETs used in the drive circuit greatly contributes to this. Further, it goes without saying that the smaller the number of FETs is, the more advantageous in terms of power consumption. For this reason, when designing a drive circuit for a liquid crystal display, how to reduce the number of constituent FETs is one of the important issues.

The present invention has been made in view of such circumstances, and provides a decoding circuit that decodes input digital data and reduces the voltage of an output signal with a smaller number of FETs. It is an object.

[0010]

According to a first aspect of the present invention, there is provided a decoder circuit for decoding 2-bit digital data represented by "0" and "1".
First signal supply means for outputting "0" when one digital signal of the 2-bit digital data is "0"; and when the one digital signal of the 2-bit digital data is "1", A second signal supply means for outputting the "0" and the first and second signal supply means. The second signal supply means is turned on when the other digital signal of the 2-bit digital data is "1". And two first switch elements for passing the signals from the first and second signal supply means, and the first and second signal supply means are connected to the first and second signal supply means, respectively. Two second switch elements which are turned on when the other digital signal is "0" and allow signals from the first and second signal supply means to pass therethrough respectively; and the first and second switch elements Connected to all of When the connected switching element is turned off, a decoder circuit, characterized by comprising four third signal supply means for supplying a digital signal "1" to the output side of the switch element.

According to a second aspect of the present invention, in the decoder circuit of the first aspect, the level of the digital signal "1" supplied by the third signal supply means is the level of the digital data input to the decoder circuit. The level is higher than "1".

According to a third aspect of the present invention, in the n-bit decoder circuit for decoding n (n is a natural number of 3 or more) bits of digital data, the least significant bit and the least significant bit of the n bits of digital data are 2. The decoder circuit according to claim 1, wherein the digital data of the next bit is inputted, and the digital data of the n bits of digital data excluding the least significant bit and a bit next to the least significant bit are decoded. 2. A plurality of second decoder circuits, provided in accordance with the number of decode outputs of the second decoder circuit, and configured to pass a decode result of the decoder circuit according to claim 1 according to a decode result of the second decoder circuit. And a plurality of gate circuits are provided corresponding to each of the plurality of gate circuits, and the corresponding gate circuits are turned off. When Tsu, a n-bit decoder circuit comprising and a plurality of fourth signal supply means for supplying a digital signal "1" to the output side of the gate circuit.

According to a fourth aspect of the present invention, in the n-bit decoder circuit of the third aspect, the level of the digital signal "1" supplied by the third and fourth signal supply means is:
The digital data is at a level higher than the digital data "1" input to the n-bit decoder circuit.

According to a fifth aspect of the present invention, in the decoder circuit for decoding 3-bit digital data of a first level and converting the decoded result to a second level higher than the first level, A least significant bit of the three bits of digital data and digital data of a bit next to the least significant bit are input, the input digital data is decoded, and the result is output at the second level. A voltage conversion circuit for converting a digital signal of the most significant bit of the 3-bit digital data to the second level, and outputting an in-phase signal and an inverted signal thereof; A first gate circuit for passing an output of the voltage conversion decoder circuit in accordance with an in-phase signal output from the conversion circuit; A decoder circuit formed by and a second gate circuit for passing the output of the voltage conversion decoder circuit in accordance with the inverted signal output from the voltage conversion circuit.

According to a sixth aspect of the present invention, there is provided the first aspect of the present invention.
And a plurality of first switch means provided as many as the number of decode outputs of the decoder circuit according to the first aspect. 6. Two different voltages are respectively input to one switch means, and the two different voltages input from any one of the first switch means based on a decoding result of the decoder circuit according to the first claim. A plurality of first switch means for outputting a voltage, and a decoding result by the decoder according to the second claim,
Voltage dividing means for dividing a voltage output from the first plurality of analog switches, and applying the voltage divided by the voltage dividing means to a liquid crystal cell constituting a liquid crystal display. It is a liquid crystal drive circuit which is a feature.

According to a seventh aspect of the present invention, in the liquid crystal driving circuit according to the sixth aspect, the voltage dividing means includes a plurality of resistors, and is output from any one of the plurality of first switch means. A resistor array to which two different voltages are applied to both ends, and a plurality of second switch means to which respective voltages divided by the respective resistors of the resistor array are inputted respectively. Item 7. A plurality of second liquid crystal cells applying a voltage input from any one of the second switch means to the liquid crystal cell based on a decoding result of the decoder circuit according to Item 5.
And switch means.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a decoder circuit according to the present invention. The decoder circuit 1 shown in FIG.
N1 (least significant bit) and IN2 are decoded, and the result is output as output signals Y1 to Y4 in negative logic. Also,
In the digital signal on the input side of the illustrated decoder circuit, "1" is represented by a voltage VDDL and "0" is represented by a ground potential (hereinafter, this digital signal is referred to as a VDDL digital signal). In the digital signal on the output side, “1” is represented by a voltage VDDH (where VDDH> VDDL), and “0” is represented by a ground potential (hereinafter, this digital signal is referred to as a VDDH-based digital signal). That is, the illustrated decoding circuit shifts the level of a VDDL-based digital signal to a VDDH-based digital signal.

In this figure, reference numerals 2 and 3 denote inverters, an inverter 2 inverts input digital data IN1, and an inverter 3 inverts input digital data IN2. 4 to 9 are NchFETs, and the gate G is set to “0”
Becomes OFF when "1" is input, and becomes O when "1" is input.
It becomes N. Here, digital data IN2 is input to the gate G of the NchFET 4, the source S is grounded, and the drain D is connected to the sources S of the NchFETs 5 and 6. The digital data IN1 is input to the gate G of the NchFET 5, and the output signal of the inverter 2 is input to the gate G of the NchFET6.
On the other hand, the output signal of the inverter 3 is input to the gate G of the NchFET 7, the source S is grounded, and the drain D is connected to the sources S of the NchFETs 8 and 9. Digital data IN1 is input to the gate G of the NchFET 8, and the output signal of the inverter 2 is input to the gate G of the NchFET9.

PchFETs 10 to 21 are turned off when "1" is input to the gate G, and turned on when "0" is input. The voltage VDDH is supplied to each source S of the PchFETs 10 to 21. And
Each drain D of the PchFETs 10 to 12 is NchFE
It is connected to the drain D of T5, and the signal at this connection point becomes the output signal Y4. Similarly, PchFETs 13 to 1
5 is connected to the drain D of the NchFET 6, and the signal at this connection point becomes the output signal Y3. The drains D of the PchFETs 16 to 18 are:
Connected to the drain D of the NchFET 8, the signal at this connection point becomes the output signal Y2, and the PchFET 19
21 are the drains D of the NchFET 9
And the signal at this connection point is the output signal Y1
Becomes

Further, each gate G of the PchFETs 10, 17, 20 is connected to the drain D of the NchFET 6, and each gate G of the PchFETs 11, 14, 21 is
Connected to the drain D of chFET8, PchFET1
Each gate G of 2, 15, 18 is connected to the drain D of the NchFET 9, and each gate G of the PchFETs 13, 16, 19 is connected to the drain D of the NchFET5.

Next, the operation of the above-described decoder circuit will be described. First, the operation when "0" is input as the digital data IN1 and IN2 will be described. In this case, first, “0” is set to the gate G of the NchFET 4.
Is input and turned off, and the gate G of the NchFET 7 is turned off.
"1" is input to the input terminal and it is turned ON. Also, NchFET
“0” is input to the gate G of No. 8 and turned off, and N
“1” is input to the gate G of the chFET 9 to be turned ON. That is, since both the NchFETs 7 and 9 are turned on, the potential at the drain D of the NchFET 9 becomes almost the ground potential, and the output signal Y1 becomes “0”.

Thus, the PchFETs 12, 15, 1
Since "0" is input to the gate G of 8 and turned on, and at this time, the NchFETs 4, 5, and 8 are each turned off, so that the output signals Y2, Y3, and Y4 are each at the voltage VDDH, that is, the VDDH system. Digital signal "1"
Becomes Further, since the output signals Y2, Y3, and Y4 are each "1", the above-described PchFETs 12, 15,
All PchFETs other than 18 are turned off.

Next, "0" is set as digital data IN1.
However, the operation when "1" is input as the digital data IN2 will be described. In this case, first, NchF
"1" is input to the gate G of ET4 to be turned ON, and N
“0” is input to the gate G of the chFET 7 to be turned off. Further, “0” is input to the gate G of the NchFET 5 to turn it off, and “1” is input to the gate G of the NchFET 6 to turn it on. That is, NchFE
Since both T4 and T6 are turned on, the potential at the drain D of the NchFET 6 becomes almost the ground potential, and the output signal Y
3 becomes "0".

Thus, the PchFETs 10, 17, 2
"0" is input to the gate G of "0" and turned on. At this time, since the Nch FETs 5, 7, and 8 are turned off, the output signals Y1, Y2, and Y4 are respectively "1" of the VDDH system digital signal. Become. The output signals Y1, Y
2 and Y4 each become “1”, so that the above-described Pch
PchFETs other than FETs 10, 17, and 20 are all OF
It becomes F.

Similarly to the above-described operation, when "1" is input as digital data IN1 and "0" is input as IN2, only output signal Y2 is "0", and when both are "1". Becomes "0" only in the output signal Y4. When the above relationship between the input and output signals is summarized in a truth table, it becomes the same as the truth table shown in FIG. 9B, that is, it can be said that 2-bit digital data is decoded. Therefore, in the above-described decoding circuit,
When the inverters 2 and 3 are configured by two FETs, a decoder circuit that decodes 2-bit digital data into four outputs can be configured by a total of 22 FETs. That is, a 2-bit / 4-output decoder circuit can be configured with 18 fewer FETs than the conventional decoder circuit.

Next, using the decoder circuit 1 described above,
A decoder circuit for decoding n-bit (n is a natural number) digital data and level-shifting a VDDL-based digital signal to a VDDH-based digital signal will be described with reference to FIG. The decoder circuit shown in this figure is composed of n-bit VDDL input digital data X1 to X1.
Xn and decodes the result to output signals Yo1-Yo.
Output with negative logic as 2 ⁿ . When the output signals Y1 to Y4 of the decoder circuit 1 are used as a VDDH system, the digital data X3 to Xn excluding the least significant bit and the next least significant bit X1, X2 are used as a VDDH system.

In this figure, reference numeral 1 denotes the same as the above-mentioned decoder circuit 1, and the first (least significant) bit X1 and the second bit X2 of the above-mentioned input digital data X1 to Xn are inputted. . Next, 30-1 and 3
.., 30-n-2 are inverters for inverting the logic of the digital signals of the corresponding bits. FIG.
In this case, the inverter 30-1 outputs the logic of the digital signal X3 of the third bit, the inverter 30-2 outputs the digital signal X4 of the fourth bit, and the inverter 30-n-2 outputs the logical signal of the digital signal Xn of the nth bit (most significant bit). Is inverted. Here, the digital signal X5 of the fifth bit to the digital signal Xn-1 of the (n-1) th bit are not shown.

Each of 31-1, 31-2,..., And 31-2 ^n-2 is an AND gate having n-2 inputs, and the input terminal of each AND gate receives digital data from the third bit to the n-th bit. The digital signals X3 to Xn are decoded.
Or its inverted digital signal * X3 to * Xn
Has been input as appropriate. The decode result output from each AND gate is output in positive logic.
In the case of the ND gate 31-1, inverted digital signals * X3 to * Xn are input to the input terminals of the ND gate 31-1, and when the digital data X3 to Xn of the third to n-th bits are all "0", 1 "is output.

.., 32-2 ^n-2 are gate circuits, each of which includes four PchFETs and four NchFs.
It consists of ET. The sources S of the four NchFETs are respectively connected to the output signals Y1 to Y of the decoder circuit 1.
4 has been entered. And these four NchFE
The output signal of the AND gate corresponding to each gate circuit is input to the gate G of T, and when “1” is output from the corresponding AND gate, the four NchFETs are turned ON.
Thus, the output signals Y1 to Y4 of the level shift circuit 1 are passed.

A voltage VDDH is supplied to each source S of the four PchFETs, and each drain D is
Each is connected to each drain D of the above-mentioned NchFET. Further, the gates G of the four PchFETs are
As with the gate G of the NchFET described above, the corresponding AN
When the output signal from the D gate is input and “0” is output from the AND gate, each PchFET is turned ON,
Pass the voltage of VDDH. Therefore, according to the above-described gate circuit, when "1" is output from the corresponding AND gate, the output signals Y1 to Y from the decoder circuit 1 are output.
4 and “0” is output, the voltage VDDH
That is, "1" of the VDDH digital signal is output.

Next, the operation of the above-described decoding circuit will be described. For example, if the digital data X1 to Xn are 1
When 0 in base 0, that is, when all bits are “0”, since “0” and “0” are input to the decoder circuit 1 as digital data IN1 and IN2, the output signals Y1 and Y are output.
2, Y3, Y4 are VDDH-based digital signals "0", "1", "1", and "1", respectively. Also, AND
Since the inverted signals of the digital signals X3 to Xn are input to the gate 31-1, "1" is output from the output terminal of the AND gate 31-1, and the other AND gates 31-2 to 31-2 are output.
"-2" is output from "-2 ^n-2 ". As a result, only four NchFETs are ON and only four P
The chFET is turned off to allow the output signals Y1 to Y4 from the decoder circuit 1 to pass, and the other gate circuits 32-2 to 32-2 to
The output terminal of 32-2 ^n-2 outputs "1" of the VDDH system digital signal. As a result, the output signals Yo1 to Yo2 ⁿ of the decoder circuit in FIG. 2 become “0” for only Yo1, and all other output signals become “1”.

Next, when the digital data X1 to Xn are 10
In base 7, the input digital data is "0 ... 0"
In the case of "111", "1" and "1" are input to the decoder circuit 1, and the output signals Y1, Y2, Y3, and Y4 are "0", "0", "0", and "1", respectively. Become. Also,
"1" is output only from the AND gate 31-2, and "0" is output from the other AND gates. This allows
The output signals Y1 to Y4 of the decoder circuit 1
It would be outputted from 2-2, the output signal Yo1～Yo2 ⁿ decoder circuit of FIG. 2, Yo8 only "0", all output signals except it is "1" in the VDDH system digital signals.

When 8-bit digital data is decoded by the n-bit decoder circuit shown in FIG. 2, the number of FETs is 2 (inverters) × 6 + 6.
(AND gate) × 64 + 8 (gate circuit) × 64 + 2
2 (decoder circuits) = 930. On the other hand, when 8-bit decoding (negative logic output) is performed by using the decoder circuit shown in FIG. 9A, 1600-2 (inverters) × 256 = 1108 FETs are required.
According to the decoder circuit of the present embodiment, the FET
The number can be reduced by about 15%.

Next, using the decoder circuit 1 shown in FIG. 1 and the conventional level shift circuit 100 shown in FIG.
Decodes 3-bit digital data and outputs VDD
A decoder circuit for level-shifting an L-system digital signal to a VDDH-system digital signal will be described with reference to FIG. The decoder circuit in FIG.
The input digital data X1 to X3 of the DDL system are decoded, and the results are output as output signals Yo1 to Yo8 in negative logic. In this figure, 1 is the decoder circuit shown in FIG. 1, and 35-1 and 35-2 are gate circuits. The gate circuits 35-1 and 35-2 are composed of four FET groups 36-1, 36-2, 37-1, and four N-channel FETs, respectively.
37-2, of which each FET group 36-1, 36-
2 is connected to each output signal Y1 of the decoder circuit 1.
To Y4, respectively, and the drain D is the output terminal Yo1 to Yo8 of the decoder circuit in FIG. Further, the inverted output signal * OUT of the level shift circuit 100 is input to the gate G of the FET group 36-1.
The output signal OUT of the level shift circuit 100 is input to the gate G of the FET group 36-2.

Further, a voltage VDDH is applied to each drain D of the FET groups 37-1, 37-2, and each source S is connected to the corresponding drain D of the FET groups 36-1, 36-2, that is, the output terminal. It is connected to the. Then, the FET group 37
−1 gate G is connected to the level shift circuit 100
, And an inverted output signal * OUT of the level shift circuit 100 is input to the gate G of the FET group 37-2.

Next, the operation of the above-described decoder circuit will be described. First, for example, when the 3-bit digital data X1 to X3 are 0 in decimal, that is, when the digital signals of all bits are "0", the decoder circuit 1 supplies the first (least significant) bit X1 and the second bit X2 to the decoder circuit 1. Is entered,
Since these signals are both "0", only the output signal Y1 becomes "0", and the output signals Y2 to Y4 become "1" of the VDDH system digital signal. These output signals Y1 to Y4 are supplied to gate circuits 35-1, 35-2, respectively.
Is input to

On the other hand, since "0" is input to the level shift circuit 100 as the most significant bit X3, the output terminal O
"0" from UT, "1" from inverted output terminal * OUT
Is output. As a result, the FET group 36-1 is turned ON,
Since the FET group 37-1 is turned off, the gate circuit 35
The output signals Y1 to Y4 of the decoder circuit 1 are output from −1. At this time, the FET group 36-2 is OFF and the FET group 3
Since 7-2 is ON, "1" of the VDDH system digital signal is output from all the output terminals of the gate circuit 35-2. Therefore, the output signals Yo1 to Yo8 of the decoder circuit of FIG.
The output signals Yo2 to Yo8 are “1”.

Next, when the input digital data is 6 in decimal, that is, the digital signal X 1,
When X2 and X3 are "0", "1" and "1" respectively,
In each of the output signals Y1 to Y4 of the decoder circuit 1, only Y3 becomes "1", and Y1, Y2 and Y4 become "0". Further, since “1” is input to the level shift circuit 100, “1” is output from the output terminal OUT, and the inverted output terminal * OUT
Outputs "0". Thereby, the FET group 36-
1 is OFF, the FET group 37-1 is ON, and "1" is output from all the output terminals of the gate circuit 35-1. The FET group 36-2 is ON, and the FET group 37-2 is OF.
Since it is F, the output signals Y1 to Y4 of the decoder circuit 1 are output from the gate circuit 35-2. Therefore, the output signals Yo1 to Yo8 of the decoder circuit of FIG.
Only the output signal Yo7 becomes “0”, and the output signals Yo1 to
o6 and Yo8 are “1”.

As described above, in the decoder circuit shown in FIG. 3, of the 3-bit digital data,
The (lowest) bit and the second bit are decoded by the decoder circuit 1, and the result is level-shifted to a VDDH-based digital signal.
Depending on the bit, the decoding result is output to the gate circuit 35-
Output from either 1 or 35-2.

In the case of the decoder circuit shown in FIG.
The T number is 2 (inverter) × 1 + 8 (gate circuit) × 2
+22 (decoder circuit) x 1 + 6 (level shift circuit)
× 1 = 46. On the other hand, when the decoder circuit shown in FIG. 9A realizes a 3-bit decoding function (negative logic output), 2 (inverter) × 3 + 4 (NAND gate)
× 8 + 6 (level shift circuit) × 8 = 86. Therefore, according to the decoder circuit shown in FIG. 3, the number of FETs can be reduced by about 47% as compared with the related art.

Next, the decoder circuit shown in FIG.
A liquid crystal drive circuit that performs the gradation control of 64 gradations using the level shift circuit shown in FIG. 1 will be described with reference to FIGS. The liquid crystal driving circuits shown in these figures decode 6-bit digital data (grayscale control data) D0 to D5, and based on the decoding result, add 64 bits to a liquid crystal cell (not shown).
One of the types of specific gradation voltages is applied.

In FIG. 4, 1a is the decoder circuit shown in FIG. 1, 100a is the level shift circuit shown in FIG.
1a is an inverter. Numerals 40a to 40c denote data latch circuits which, among the 6-bit grayscale control data D0 to D5 input from the outside, store 3-bit grayscale control data D3, D4 and D5 including the most significant bit D5. Latch at a predetermined timing. 41 to 44 are four Nch
The FET group is composed of FETs, and each FET group is composed of four NchFETs. Also,
For the individual NchFETs that make up each FET group,
Subscripts a to d are added after each code. Here, as shown in FIG. 4, the respective sources S of the FET groups 41 and 42 are connected to the respective output terminals Y1 to Y4 of the decoder circuit 1a. Further, the inverted output signal * OUT of the level shift circuit 100a is supplied to each gate G of the FET group 41,
The output signal OUT of the level shift circuit 100a is input to each of the gates G.

The drains D of the FET groups 41 and 42 are connected to the sources S of the FET groups 43 and 44, respectively. Further, a voltage VDDH is applied to each of the drains D of the FET groups 43 and 44, and the output signal OUT of the level shift circuit 100 a is applied to each of the gates G of the FET group 43 and each of the gates G of the FET group 44. Represents an inverted output signal * OUT of the level shift circuit 100a. Also, each drain D of the FET group 41
And the connection point of each source S of the FET group 43 is connected to the corresponding on / off control terminal of the corresponding 2-input 2-output analog switch 49a-49d. Similarly, a connection point between each drain D of the FET group 42 and each source S of the FET group 44 is connected to on / off control terminals of corresponding two-input / two-output analog switches 49e to 49h.

The above-described analog switches 49a to 49h
Have different voltages V1 to V1 as shown in FIG.
V9 (where V1 <V2 <... <V9), the voltage Vn
And voltage Vn + 1 (n = 1, 2,..., 8) are sequentially input. The analog switches 49a to 49h are turned on when a VDDH digital signal "0" is output from the corresponding FET group, and the input voltage Vn and Vn + 1 are respectively turned on by a resistor array 50 described later.
(See FIG. 5). When "1" is output, the signal is turned off. In this case, Vn and Vn + 1 are not output from the analog switch.

Next, in FIG. 5, 1b is the decoder circuit shown in FIG. 1, 100b is the level shift circuit shown in FIG. 10, and 101b is an inverter. Also, 40d-40
f is the same data latch circuit as the data latch circuits 40d to 40f described above, and is the least significant bit D0 of 6-bit grayscale control data D0 to D5 input from the outside.
Is latched at a predetermined timing with the 3-bit gradation control data D0, D1, and D2. 45 to 48 are FET groups 4
FET groups similar to the FET groups 1 to 44;
Are connected to the respective output terminals of the decoder circuit 1b. The inverted output signal * OUT of the level shift circuit 100b is connected to each gate G of the FET group 45.
However, each gate G of the FET group 46 has a level shift circuit 1
00b is input.

The drains D of the FET groups 45 and 46 are connected to the sources S of the FET groups 47 and 48, respectively. Further, a voltage VDDH is applied to each of the drains D of the FET groups 47 and 48, and the output signal OUT of the level shift circuit 100b is applied to each of the gates G of the FET group 47 and to each of the gates G of the FET group 48. Are the inverted output signals * OUT of the level shift circuit 100b, respectively. Also, each drain D of the FET group 45
And the connection point of each source S of the FET group 47 is connected to the on / off control terminals of the corresponding one-input / one-output analog switches 51a to 51d. Similarly, a connection point between each drain D of the FET group 46 and each source S of the FET group 48 is connected to the corresponding one-input / one-output analog switch 51e to 51h.

The resistor array 50 is formed by connecting eight resistors each having the same resistance value R in series.
It is connected to each output on the voltage Vn + 1 side of 49h, and is connected to each output on the voltage Vn side at the other point i. The input terminals of the analog switches 51b to 51h are connected to the points a to h of the resistor array 56, respectively, and the output terminals of the analog switches 51b to 51h are connected at one point to a liquid crystal cell (not shown). The gray scale voltage Vgrd is applied. In addition, when the VDDH-based digital signal “0” is output from the corresponding FET group, the signal is turned on, and when “1” is output, the signal is turned off.

Next, the operation of the above-described liquid crystal drive circuit will be described. First, the grayscale control data D latched at a predetermined timing by the data latch circuits 40a to 40f.
0 to D5 are the decoder circuit 1a, the level shift circuit 10
0a and the FET groups 41 to 44 decode the higher-order three-bit gradation control data D3, D4, D5.
As a result, one of the analog switches 49a to 49h is turned on, and the potential difference between the voltage Vn + 1 and the voltage Vn applied to the turned on analog switch is applied to both ends of the resistor array 50.

For example, in FIG. 4, when the fourth bit D3 and the fifth bit D4 are both "0" and the sixth (most significant) bit D5 is "1", the output signal of the decoder circuit 1a is Y1 Only "0" and the result is NchFE
Passes T42a. Therefore, the analog switch 4
9e is turned on, and the other analog switches 49a-4
9d, 49f to 49h are turned off. As a result, a potential difference V6-V5 is applied between the points a and i of the resistor array 50.

Similarly, the lower 3 bits D of the gradation control data
0, D1, and D2 are decoded by the decoder circuit 1b, the level shift circuit 100b, and the FET groups 45 to 48. As a result, one of the analog switches 51a to 51h is turned on, and one of the eight voltages divided by the resistor array 50 is selected according to the turned on analog switch, and the gray scale voltage Vgrd is selected. Is applied to the liquid crystal cell. For example, if the first (least significant) bit D0 and the third bit D2 are both "0" and the second bit D1 is "1", the output signal of the decoder circuit 1a becomes "0" only in Y3, The result is NchFET
Pass through 45c. Therefore, the analog switch 51
Only c is turned on, and 3/8 of the voltage applied to both ends of the resistor array 50 is applied to a liquid crystal cell (not shown) as a gradation voltage Vgrd.

As described above, the gradation control data D0 to D2 and D3 to D5 are supplied to the decoder circuit 1a, the level shift circuit 1
00a and the FET groups 41 to 44 and the decoder circuit 1
b, level shift circuit 100b and FET groups 45 to 4
8 and the gray scale control data D3 to D5 of the upper three bits.
9 out of 8 potential differences applied to 9a to 49h
And the lower three bits of gradation control data D0 to D2
Selects one of the eight divided voltages by the resistor array 50. Therefore, the voltage Vgrd finally output as the gradation voltage has 8 × 8 patterns,
Therefore, 64 gradation control can be performed by the gradation control data D0 to D5.

Here, the number of FETs required to configure the drive circuits of FIGS. 4 and 5 is 22 (decoder circuit) × 2 +
6 (level shift circuit) × 2 + 4 (FET group) × 8 + 4
(1 input 1 output analog switch) × 8 + 8 (2 input 2
Output analog switch) x 8 + 2 (inverter) x 2 =
It becomes 156 pieces.

Next, a driving circuit for a color liquid crystal display using the liquid crystal driving circuit shown in FIGS. 4 and 5 will be described.
FIG. 6 shows a driving circuit for a color liquid crystal display.
Pixels P11, P12, arranged in row n column (m and n are integers)
... consisting of Pmn. Each pixel is composed of three liquid crystal cells CR, CG, and CB for displaying red, green, and blue, respectively, and transistors TR, T for each liquid crystal cell.
G and TB are connected.

Reference numeral 61 denotes a source driver for sequentially applying a voltage to each transistor connected to each liquid crystal cell based on gray scale control data inputted from the outside. It is composed of a liquid crystal drive circuit. 62 is a shift register,
Each of the data latches 63 has the same number of output terminals as the number (n × 3) of all liquid crystal cells in one pixel row, and shifts an externally input latch pulse according to a clock signal CK1 also input from the outside. -1, 63-2, ..., 63-n
Sequentially output latch pulses.

Data latches 63-1, 63-2,..., 6
3-n are latch circuits 71, 72, 7 as shown in FIG.
3 of the color liquid crystal display 60.
n. The latch circuit 71,
Reference numerals 72 and 73 are connected to the data bus 64, respectively, and individually latch the gradation control data according to the latch pulse output from the shift register 62.

Each of the liquid crystal driving circuits 65, 65,... Shown in FIG. 4 and FIG.
Three data latches 63-1, 63-2, ...,
The gray scale control data output from the memory cells 63-n are latched according to a set signal Sset, and a voltage generated based on the latched gray scale control data is applied to a corresponding liquid crystal cell. A gate driver 66 has an output terminal corresponding to each of the pixel rows 1 to m of the color liquid crystal display 60, and shifts a gate pulse input from the outside based on a clock signal CK2 input from the outside. Gate pulses are sequentially output to the output terminal.

Next, the operation of the above-described liquid crystal display driving circuit will be described with reference to a timing chart shown in FIG. In FIG. 8, D0 to D5 indicate gradation control data output to the data bus 64, and the gradation control data for each liquid crystal cell of each pixel is sequentially output in the order of red, green, and blue. Here, in the figure, P11CR, P11
CG, P11CB,... Mean gradation control data for a certain liquid crystal cell in a certain pixel.
11CR indicates the gradation control data for the liquid crystal cell for controlling the gradation of red of the pixel in the first row and first column of the color liquid crystal display 60.

T1r, t1g, t1b, t2r, t2g, t2b,
.., Tnr, tng, and tnb indicate the timings of the latch pulses output from the shift register 62, respectively. further,
Sset indicates the timing of the set signal described above, and G1 indicates the timing of the gate pulse output from the gate driver 66 to the gates of all the transistors connected to each pixel row of the first row.

As shown in FIG. 8, the data bus 64
From the gradation control data for the pixel P11, gradation control data for each liquid crystal cell of each pixel is sequentially output in the order of red, green, and blue. Then, the latch pulse is sequentially shifted and output from the shift register 62 in accordance with each of the gradation control data. Thereby, the data latches 63-1,
63-n individually latch the gradation control data for the red, green, and blue liquid crystal cells of each pixel.

When all the gradation control data for the pixels in the first row and the nth column are latched, the set signal Sse
t is output, and in the liquid crystal drive circuits 65, 65,.
The grayscale control data respectively latched by the corresponding data latches are used for data latch circuits 40a to 40a to 40g shown in FIGS.
Latch by 40f. Thereby, each liquid crystal drive circuit generates a voltage based on the gradation control data,
Applied to the corresponding liquid crystal cell. Also, the set signal Sset
Output from the gate driver 66 and the gate pulse G
1 is output, and the color LCD 6
The display is performed on the pixels in the first row of 0.

Next, the gradation control data for each liquid crystal cell of each pixel in the second row output to the data bus 64 is transferred to the latch pulses t1r and t1 output from the shift register 62.
g, t1b, ..., the data latches 63-1, 63-2.
,..., 63-n, and when all the gradation control data for the pixels in the second row and the nth column are latched, a set signal Sset is output, and the liquid crystal driving circuit 65,
At 65,..., A voltage based on the gradation control data latched by the corresponding data latch is generated and applied to the corresponding liquid crystal cell. At the same time, a gate pulse G2 (not shown) is output from the gate driver 66 to the gates of all the transistors connected to each pixel row of the second row. The display is performed on the pixel of the eye.

Thereafter, when the above operation is repeated up to the m-th row, an image for one frame is displayed on the color liquid crystal display 60. As described above, in the driving circuit of the liquid crystal display of FIG. 6, an image is displayed by repeatedly applying a voltage based on the gradation control data to the liquid crystal cells arranged in each column and displaying each row. doing.

[0063]

As described above, according to the decoder circuit of the present invention, the number of FETs required when configuring a driving circuit for controlling the gradation of a liquid crystal display is greatly reduced as compared with the prior art. Since the manufacturing process of the driving circuit of the liquid crystal display can be facilitated and the yield can be improved as well as the power consumption can be reduced, the liquid crystal of the portable electronic device operated by the battery can be reduced. It is very useful as a display driving circuit. Further, since the area of the LSI chip can be significantly reduced, downsizing of the liquid crystal display can be promoted.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a configuration of a decoder circuit according to the present invention.

FIG. 2 is a connection diagram illustrating a configuration of a decoder circuit that decodes n-bit digital data using the decoder circuit of FIG. 1;

FIG. 3 is a connection diagram showing a configuration of a decoder circuit for decoding 3-bit digital data using the decoder circuit of FIG. 1;

FIG. 4 is a connection diagram illustrating a part of a configuration of a liquid crystal driving circuit using the decoder circuit of FIG. 1;

FIG. 5 is a connection diagram illustrating a part of a configuration of a liquid crystal drive circuit using the decoder circuit of FIG. 1;

FIG. 6 is a connection diagram when a driving circuit for a color liquid crystal display is configured using the liquid crystal driving circuit.

FIG. 7 is a connection diagram showing a configuration of a data latch used in a drive circuit of the color liquid crystal display.

FIG. 8 is a timing chart showing timings of various control signals of a drive circuit of the color liquid crystal display.

FIG. 9 shows a two-bit signal using a conventional level shift circuit.
FIG. 4 is a connection diagram when a four-output decoder is configured.

FIG. 10 is a connection diagram when a conventional level shift circuit is configured.

[Explanation of symbols]

1, 1a, 1b... Decoder circuit, 2, 3, 30-1 to
30-n-2: inverter, 4 to 9: NchFET,
10-21... PchFET, 31-1 to 31-2 ^n-2 .
... AND gate, 32-1 to 32-2 ^n-2 , 35-1,3
5-2 ... gate circuit, 36-1, 36-2, 37-1
, 37-2, 41 (ad) to 48 (ad)... F
ET group, 49a to 49h... Analog switch (two inputs and two outputs), 50... Resistor array, 51a to 51h... Analog switches (one input and one output).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Chen Xiao Xiang, 1-5-1, Taito, Taito-ku, Tokyo Letterpress Printing Co., Ltd. (72) Inventor: Shigeru Yamada 3500 Matsuoka, Oita, Oita Prefecture Toshiba Corporation Inside the Oita Plant (72) Inventor Tokutaro Takaku Inside the Toshiba Semiconductor System Technology Center, No. 580, Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture

Claims (7)

[Claims] 1. The two represented by "0" and "1"
A decoder circuit for decoding bit digital data, a first signal supply means for outputting "0" when one digital signal of the 2-bit digital data is "0"; When one of the digital signals is "1", the second signal supply means for outputting the "0" is connected to the first and second signal supply means.
Two first switch elements that are turned on when the other digital signal of the bit digital data is “1” and pass the signal from the first and second signal supply means; 2 signal supply means, respectively,
Two second switch elements that are turned on when the other digital signal of the bit digital data is “0” and pass signals from the first and second signal supply means, respectively, Four third signal supply means connected to all of the second switch elements and supplying a digital signal "1" to an output side of the switch element when the connected switch element is turned off. A decoder circuit characterized in that: 2. The digital signal “1” supplied by said third signal supply means has a higher level than digital data “1” inputted to said decoder circuit. 2. The decoder circuit according to 1. 3. An n-bit decoder circuit for decoding n (n is a natural number not less than 3) bits of digital data, comprising: a least significant bit of the n bits of digital data and a digital signal of a bit next to the least significant bit. 2. The decoder circuit according to claim 1, wherein data is input; and a second decoder circuit that decodes digital data of the n-bit digital data excluding the least significant bit and a bit next to the least significant bit. Provided in accordance with the number of decoding outputs of the second decoder circuit, and according to the decoding result of the second decoder circuit,
A plurality of gate circuits for passing a decoding result by the decoder circuit according to claim 1, and a plurality of gate circuits provided corresponding to each of the plurality of gate circuits, wherein the corresponding gate circuit is turned off when the corresponding gate circuit is turned off. An n-bit decoder circuit comprising: a plurality of fourth signal supply means for supplying a digital signal "1" to an output side. 4. The level of the digital signal “1” supplied by the third and fourth signal supply means is higher than the level of digital data “1” input to the n-bit decoder circuit. The n-bit decoder circuit according to claim 3, wherein 5. Decoding first-level 3-bit digital data, and decoding the decoded result to the first level.
A second level higher than the second level, wherein the least significant bit and the digital data of the bit next to the least significant bit among the three bits of digital data are inputted, and the inputted digital data is 3. The decoder circuit according to claim 2, which decodes and outputs the result at the second level, and converts a digital signal of the most significant bit of the 3-bit digital data into the second level. A voltage conversion circuit that outputs an in-phase signal and an inverted signal; a first gate circuit that passes an output of the voltage conversion decoder circuit in accordance with the in-phase signal output from the voltage conversion circuit; and a voltage output from the voltage conversion circuit. A second gate circuit for passing the output of the voltage conversion decoder circuit in accordance with the inverted signal. Coder circuit. 6. A decoder circuit according to claim 1, a decoder circuit according to claim 2, and a plurality of decoder circuits provided as many as the number of decode outputs of the decoder circuit according to claim 1. First switch means,
6. The two different voltages input to each of the first switch means, respectively, and the two types of voltages input from any one of the first switch means based on a decoding result of the decoder circuit according to the first embodiment. A plurality of first switch means for outputting different voltages, and a voltage dividing means for dividing a voltage output from the first plurality of analog switches based on a decoding result by the decoder according to the second claim. A liquid crystal driving circuit for applying a voltage divided by the voltage dividing means to a liquid crystal cell constituting a liquid crystal display. 7. A resistor array comprising a plurality of resistors, wherein two different voltages output from any one of the plurality of first switch means are applied to both ends of the resistor array, 6. A plurality of second switch means to which respective voltages divided by the respective resistors of the resistance array are respectively inputted, wherein any one of the second switch means is selected based on a decoding result of the decoder circuit according to the second claim 5. 7. The liquid crystal drive circuit according to claim 6, comprising a plurality of second switch means for applying a voltage input from the second switch means to the liquid crystal cell.