JPH10327053A - Duty factor control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust a duty factor (pulse width) and to perform a stable operation even at a low voltage by constituting a transistor column with two stages. SOLUTION: This circuit is provided with a CMOS inverter constituted of a P channel MOS transistor (Pch transistor) M1 for turning input signals to gate input and a Pch transistor M2 serially connected between power sources VDD and VSS, the Pch transistor M3 parallelly connected to the Pch transistor M1, a switch SW1 for switching and connecting the gate of the Pch transistor M1 to the input signals or the power supply VDD by control signals and an output inverter F1. Then, by switching the gate connection of the Pch transistor by the switch SW1, the duty is varied. Also, since constitution is performed by transistor vertically connected two stages, even when a power supply voltage is lowered, the more stablilized opration is made possible than with a conventional circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a duty control circuit, and more particularly to a duty control circuit using a MOS type semiconductor integrated circuit.

[0002]

2. Description of the Related Art An example of a conventional duty (pulse width) control circuit is shown in FIG. FIG. 8 is a timing waveform chart for explaining the operation principle of the duty control circuit shown in FIG. In FIG. 7, reference numeral 10 denotes a P-channel MOS transistor (referred to as a "Pch transistor"), and reference numeral 11 denotes an N-channel MOS transistor (referred to as an "Nch transistor"). Reference numeral 14 denotes a Pch transistor whose gate is connected to the input terminal, whose drain is connected to the drain of the Nch transistor 11, and which is connected to the output node 1 of the duty adjustment circuit. A Pch transistor 15 has a source connected to the VDD power supply, a drain connected to the source of the Pch transistor 14, and a gate connected to a control signal.

A control signal is set to "H" level (VDD)
At this time, the Pch transistor 15 is turned off, the VDD power is not supplied to the Pch transistor 14, and the Pch transistor 14 does not operate. Therefore, the input signal from the input terminal is the Pch transistor 10 and the Nch transistor 1
And 1 is inverted and amplified. At this time, if the driving capabilities of the Pch transistor 10 and the Nch transistor 11 are equal, they are amplified with a waveform centered at the 1/2 VDD level. That is, the duty at the level of (VDD + VSS) / 2 is 50%.

Next, when the duty control terminal 9 is set to “L” level (VSS level), the Pch transistor 16 is turned on, and VDD power is supplied to the Pch transistor 14. Therefore, the input signal from the input terminal is inverted and amplified by the Pch transistors 10 and 14 and the Nch transistor 11. At this time, the driving capability of the Pch transistor becomes N
Since the driving capability of the channel transistor is exceeded, the center level of the waveform output from the output node 1 is shifted to the VDD side.

Since this signal is inverted and amplified by the output buffer F1, the output waveform outputted to the outside has a center level shifted to the VSS power supply side. That is, (VDD
The duty becomes 50% at a voltage lower than (+ VSS) / 2.

[0006] A CMOS is used as the duty adjustment circuit.
For a configuration in which two stages of Pch transistors are vertically stacked between the output node of the inverter and the power supply VDD, and the gate terminal of the Pch transistor on the power supply side supplies a duty control terminal voltage, see, for example, the description in JP-A-4-335714. Is done.

[0007]

However, in the conventional duty control circuit shown in FIG.
4 and 15 are stacked vertically, there is a problem that if the power supply voltage VDD is lowered, a drain-source voltage during operation is not secured and the operation becomes unstable.

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a duty adjustment circuit which operates well at a low voltage.

[0009]

In order to achieve the above object, a duty control circuit according to the present invention has a source connected to a high potential side power supply,
A P-channel transistor having a gate connected to the input terminal; a drain connected to the drain of the P-channel transistor; a source connected to the lower potential power supply; an N-channel transistor having a gate connected to the input terminal; And one or a plurality of P-channel transistors connected to the gate and the gates of the one or more P-channel transistors connected in parallel, and the control signal connects the gate to the input terminal or the high potential side power supply. And an output inverter having an input terminal connected to the drains of the plurality of P-channel transistors and the N-channel transistor.

Further, according to the present invention, a P-channel transistor having a source connected to a high potential side power supply, a gate connected to an input terminal, a drain connected to a drain of the P-channel transistor, a source connected to a low potential side power supply, and a gate connected to a low potential side power supply. An N-channel transistor connected to the input terminal, one or more N-channel transistors connected in parallel to the N-channel transistor, and a gate connected to one or more N-channel transistors connected in parallel to control One or more switches for switching the gate to the input terminal or the low-potential side power supply according to a signal;
A channel transistor and an output inverter connected to drains of the plurality of N-channel transistors.

Further, in the present invention, a P-channel transistor having a source connected to the high potential side power supply, a gate connected to the input terminal, a drain connected to the drain of the P-channel transistor, a source connected to the low potential side power supply, and a gate connected to the low potential side power supply. Is connected to an input terminal, and the P-channel transistor
One or more P-channel transistors connected in parallel to the channel transistor, and one or more P-channel transistors connected in parallel to the gate of the P-channel transistor;
The control signal is connected to one or more first switches for switching and connecting the gate to the input terminal or the high-potential-side power supply, and to the gates of the one or more N-channel transistors connected in parallel. One or more second switches for switching the gate to the input terminal or the low-potential-side power supply, and an output inverter having an input terminal connected to the drains of the plurality of P-channel transistors and the plurality of N-channel transistors. , Comprising.

[0012]

Embodiments of the present invention will be described below. Embodiments of the present invention preferably include a first P-channel MOS transistor (referred to as a “Pch transistor”) having a source connected to VDD (positive voltage source) and a gate connected to an input terminal, and a first Pch transistor. Are connected, the gate is connected to the input terminal,
An inverter section including a first N-channel MOS transistor (referred to as an “Nch transistor”) having a source connected to VSS (negative voltage source); a drain and a drain of the first Pch transistor; Pch
One or more Pchs connected to the source of the transistor
A transistor, a duty variable unit including a drain of the first Nch transistor and one or a plurality of Nch transistors whose sources are connected to the source of the first Nch transistor, and individual Pch transistors of the duty variable unit And / or one or more switches connecting the gates of the Nch transistors to VSS or the input terminal, and / or one or more switches connecting the gates of the individual Nch transistors to the VSS or the input terminal.
A transistor and an inverter having the drain of the first Nch transistor as an input.
By switching the gate connection of the h and Nch transistors, the duty can be varied.

The duty is changed by controlling each switch to change the driving capability (threshold) of the inverting amplifier.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[Embodiment 1] FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention, and is a diagram constituted by CMOS transistors.

Referring to FIG. 1, a duty control circuit according to the present embodiment includes a CMOS inverter which is connected in series between a power supply VDD and VSS and includes a Pch transistor M1 and an Nch transistor M2 having an input signal as a gate input; Pch connected in parallel to Pch transistor M1
A transistor M3, a switch SW1 for switching the gate of the Pch transistor M1 to an input signal or a power supply VDD by a control signal, and an output inverter F1.
And is provided.

FIG. 2 shows a timing waveform chart of the first embodiment of the present invention. The operation of the present embodiment will be described with reference to FIGS.

When the control signal is at "L" level, the gate of the Pch transistor M3 is connected to the power supply VDD by the switch SW1. At this time, the Pch transistor M
The gate-source voltage of No. 3 is 0 V, so that it does not operate irrespective of the drain voltage of the Pch transistor M3 (non-conductive state).

Therefore, the Pch transistors M1 and N
If the driving capability of the channel transistor M2 is made equal,
When the level of (VDD + VSS) / 2 is input, the voltage of the node 1 becomes the level of (VDD + VSS) / 2.

At this time, the voltage of the node 1 is inverted and amplified by the output inverter F1. That is, an output with a duty of 50% is obtained.

On the other hand, when the control signal is at "H" level, the gate of the Pch transistor M3 is connected to the input signal side by the switch SW1. At this time, the driving capability of the Pch transistor M3 and the Pch transistor M1 is Nc
h, since the driving capability of the transistor M2 is exceeded, (VDD
When the (+ VSS) / 2 level is input, the voltage of the node 1 has a value shifted to the VDD side.

When the potential of the node 1 is inverted and amplified by the output inverter F1, the output becomes "L", and an output with a duty of 50% or less is obtained (see the arrow in FIG. 2).

When a plurality of Pch transistors are connected in parallel to the Pch transistor M1, Pc
The driving capability of the h transistor exceeds the driving capability of the Nch transistor M2, and the duty is further reduced.

In the embodiment of the present invention, two stages of transistors are vertically connected.
It can operate more stably than conventional circuits.

[Embodiment 2] FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention, and is a diagram composed of CMOS transistors. FIG. 4 is a timing waveform chart for explaining the operation of the second embodiment of the present invention.

In FIG. 3, the duty control circuit
An inverter configured by a channel transistor M1 and an Nch transistor M2, an Nch transistor M4 connected in parallel to M2, a switch SW2, and an output inverter F1.

Next, the operation of the second embodiment of the present invention will be described. When the gate of the Nch transistor M4 is connected to VSS by the switch SW2, the voltage between the gate and the source of the Nch transistor M4 becomes 0 V, and the Nch transistor M4 does not operate regardless of the drain voltage. Therefore, the Pch transistor M1 and the Nch transistor M2
Are equal, the driving capability of (VDD + VSS) /
When two levels are input, the voltage of the node 1 becomes (VDD)
+ VSS) / 2 level. The voltage at the node 1 is inverted and amplified by the output inverter F1. That is, an output with a duty of 50% is obtained.

The control voltage is set to "H" and the switch S
When the gate of the Nch transistor M4 is connected to the input by W2, the driving capability of the Nch transistor M4 and the Nch transistor M2 exceeds the driving capability of the Pch transistor M1, so that when (VDD + VSS) / 2 level is input, the node 1 The voltage has a value shifted to the VSS side. When the output is inverted and amplified by the output inverter F1,
The output becomes "H", and an output with a duty of 50% or more is obtained.

When a plurality of Nch transistors are connected in parallel with the Nch transistor M2, the driving capability of the Nch transistor exceeds the driving capability of the Pch transistor M1, and the duty is further increased.

In the embodiment of the present invention, two stages of transistors are vertically connected, so that stable operation can be performed even at a low voltage.

[Embodiment 3] FIG. 5 is a diagram showing a circuit configuration of a third embodiment of the present invention, and is a diagram composed of CMOS transistors. FIG. 6 is a timing waveform chart for explaining the operation of the third embodiment of the present invention. In FIG. 5, the duty control circuit includes a Pch transistor M
1, a CMOS inverter composed of an Nch transistor M2, a plurality of Pch transistors connected in parallel to the Pch transistor M1, a plurality of Nch transistors connected in parallel to the Nch transistor M2, switch groups SW1 and SW2, and an output inverter F1.

Next, the operation of the third embodiment of the present invention will be described. By the switch SW1, the gates of all the Pch transistors whose gates are connected to the switch are connected to the power supply voltage V.
DD, Nc whose gate is connected to the switch SW2.
When all the gates of the h transistor are connected to VSS,
The gate-source voltages of all the transistors whose gates are connected to the switches SW1 and SW2 are 0 V and do not operate.

Therefore, the Pch transistors M1 and N
If the driving capability of the channel transistor M2 is made equal,
When the level of (VDD + VSS) / 2 is input, the voltage of the node 1 becomes the level of (VDD + VSS) / 2. At this time, the voltage of the node 1 is inverted and amplified by the output inverter F1. That is, an output with a duty of 50% is obtained.

When the gate of the Pch transistor connected in parallel to the Pch transistor M1 is connected to the input terminal by the switch SW1, the driving capability of the Pch transistor exceeds the driving capability of the Nch transistor, and (VDD + V
SS) / 2 level is input, the voltage of the node 1 becomes V
The value is shifted to the DD side. The output is inverted and amplified by the output inverter F1, and an output with a duty of 50% or less is obtained.

When the gate of the Nch transistor connected in parallel with the Nch transistor M2 is connected to the input by the switch SW2, the driving capability of the Nch transistor becomes Pc
h, which exceeds the drive capability of the transistor, and (VDD + VS
S) / 2 level is input, the voltage of the node 1 becomes VS
The value is shifted to the S side. The voltage of the node 1 is inverted and amplified by the output inverter F1, and an output with a duty of 50% or more is obtained. The duty can be adjusted to “+” or “−”.

If the driving capabilities of the Pch transistor and the Nch transistor whose gates are connected to the switches SW1 and SW2 are shifted, fine adjustments can be made by combination.

In this embodiment, since the transistors are vertically stacked in up to two stages, stable operation is possible even at a low voltage.

[0038]

As described above, according to the present invention,
There is an effect that the duty (pulse width) can be adjusted and the operation can be performed even at a low voltage.

The reason is that, in the present invention, since transistors are vertically stacked in two stages, stable operation can be performed even at a low voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the third embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a circuit configuration according to the related art.

FIG. 8 is a timing chart for explaining the operation of the conventional technique.

[Explanation of symbols]

 M1 Pch transistor 1 M2 Nch transistor 1 M3 Pch transistor 2 M4 Nch transistor 2 M5 Pch transistor 3 M6 Nch transistor 3 M7 Pch transistor 4 M8 Nch transistor 4 F1 Inverter SW1 Switch1 SW2 Switch2 1 Input terminal of output inverter F1 10 Pch transistor 5 11 Nch transistor 5 14 Pch transistor 6 15 Pch transistor 7

Claims (3)

[Claims] 1. A P-channel transistor having a source connected to a high potential side power supply, a gate connected to an input terminal, a drain connected to a drain of the P-channel transistor,
An N-channel transistor having a source connected to the low potential side power supply, a gate connected to the input terminal, one or more P-channel transistors connected in parallel to the P-channel transistor, and one or more connected in parallel And one or more switches that are connected to the gates of the P-channel transistors respectively and switch the gate to the input terminal or the high-potential-side power supply according to a control signal. And an output inverter connected to the drain of the channel transistor. 2. A P-channel transistor having a source connected to the high potential side power supply, a gate connected to the input terminal, a drain connected to the drain of the P-channel transistor,
An N-channel transistor having a source connected to the low-potential-side power supply, a gate connected to the input terminal, one or more N-channel transistors connected in parallel to the N-channel transistor, and one or more connected in parallel And one or more switches for switching the gate to the input terminal or the low-potential-side power supply according to a control signal, and having an input terminal connected to the P-channel transistor and the plurality of N-channel transistors. And an output inverter connected to the drain of the channel transistor. 3. A P-channel transistor having a source connected to the high potential side power supply, a gate connected to the input terminal, a drain connected to the drain of the P-channel transistor,
An N-channel transistor having a source connected to the low potential side power supply, a gate connected to the input terminal, one or more P-channel transistors connected in parallel to the P-channel transistor, and one or more P-channel transistors connected in parallel to the P-channel transistor One or more first switches connected to the gate of a P-channel transistor for switching the gate to the input terminal or the high-potential-side power supply according to a control signal; and one or more N-channel transistors connected in parallel And one or more second switches for switching the gate to the input terminal or the low-potential-side power supply according to a control signal; and an input terminal having the plurality of P-channel transistors and the plurality of N-channel transistors. And an output inverter connected to the drain of the duty control circuit.