JPH10294662A - Output buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the deterioration of transistors to be a minimum when a voltage level higher than operation voltage in LSI is outputted outside by providing an intermediate potential generation circuit controlling the gate voltage of the transistors in an output circuit and a level shift circuit. SOLUTION: In the intermediate potential generation circuit 2, the number of connections of Pch enhancement-type transistor (Pch transistors) 9-13 which are diode-connected is varied and the voltage VPM of an intermediate level degree between high voltage power source VDDH and a GND level is generated. Voltage VPM is applied to the gates of the Pch transistors 21, 23 and 31 of the level shift circuit 3 and the output circuit 4. Thus, gate with stand voltage can sufficiently be improved and the deterioration of the Pch transistors 20, 22 and 30 can be prevented by setting the gate voltage of the Pch transistors 20, 22 and 30 using the high voltage power source VDDH to be VPM+ | the threshold VPM+ | the there shift of the Pch transistor | of the Pch transistor |at the least.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to an output buffer circuit.

[0002]

2. Description of the Related Art FIG. 4 shows an example of the configuration of a conventional output buffer circuit. Referring to FIG. 4, a conventional output buffer circuit includes an inverter gate 6 receiving a control signal EN, a NAND gate 7 receiving an input signal DATA and a control signal EN, an output of the inverter gate 6, and an input signal DATA. And a level shift circuit 43, 44 for converting the voltage level of the input signal DATA from a low voltage to a high voltage.
A P-channel enhancement transistor (hereinafter also referred to as a “Pch transistor”) 46 having a source connected to the high power supply voltage and a gate connected to the output of the level shift circuit 43, and a source connected to GND and a gate connected to the level shift circuit 44. And an output circuit 45 comprising an N-channel enhancement type transistor (hereinafter also referred to as “Nch transistor”) 47 connected to the output of the Pch transistor 46 and connected to the output terminal 5 by connecting the drain to the drain of the Pch transistor 46. .

When a voltage level higher than the operating voltage inside the LSI is output from the output terminal 5 to the outside of the LSI, the above-described level shift circuit 43 is used to increase the gate breakdown voltage by increasing the gate oxide film of the transistor. The LSI 44 and the output circuit 45 are manufactured by using a high withstand voltage process separately from the internal process.

For example, when the internal operating voltage of the LSI is 3 V and a voltage of 5 V is externally output, the high voltage power supply VDDH of the output circuit 45 is set to 5 V, and an output buffer is provided for the control signal EN of the control circuit 1. 3V to activate
(“H” level) is input, and 3 is input to the input signal DATA.
V (“H” level) is input.

Since both the input signal DATA and the control signal EN are at "H" level, the output of the NAND gate 7 is 0V
(“L” level), the output of the NOR gate 8 is 0V
(“L” level), and these output voltage levels are
The level is converted by the level shift circuits 43 and 44,
The “H” level changes from 3V to 5V.

After the level conversion, 0 V (“L” level) is input to the gate of the Pch transistor 46 of the output circuit 45 to be turned on, and 0 V (“L” level) is input to the gate of the Nch transistor 47 and turned off. State
The output terminal 5 outputs the potential 5 V (“H” level) of the high voltage power supply VDDH of the output circuit 45. The same operation can be used to output a voltage level of 0 V.

Here, if a high withstand voltage process is not used for the level shift circuit and the output circuit, a voltage higher than the maximum value of the internal operating voltage is applied between the gate and source of the transistor of the output circuit. Deteriorates and L
The reliability of the SI decreases.

In order to solve such a problem, for example, Japanese Patent Application Laid-Open No. Hei 4-236516 discloses an output buffer circuit having a high breakdown voltage without changing the manufacturing process or sacrificing the operating characteristics of the transistor. As a circuit configuration for improving reliability, an input circuit, an NMOS drive circuit,
A first signal which is constituted by a PMOS drive circuit, a bias circuit, and an output circuit and whose amplitude is smaller than the ground level GND to the power supply voltage VDD but whose minimum level is the same as the ground level; A second signal that is less than the voltage VDD but whose highest level is the same as the power supply voltage VDD;
The maximum value of the voltage applied between any two terminals of all the MOS transistors constituting the output buffer circuit is | VDD
-The threshold voltage | of the MOS transistor, and the amplitude of the finally output signal is set to the ground level Gnd to the ground level Gnd based on the first and second signals.
The power supply voltage VDD is set, and the effective withstand voltage is improved without increasing the thickness of the gate oxide film.
There has been proposed an output buffer circuit capable of forming a high-voltage output buffer without using a high withstand voltage process.

[0009]

However, the conventional output buffer circuit proposed in Japanese Patent Application Laid-Open No. Hei 4-236516 discloses a conventional output buffer circuit having two MOS transistors.
The maximum value of the voltage applied between the terminals is | VDD-MOS
Since the threshold voltage | of the transistor is set, the withstand voltage of the transistor is substantially increased by one threshold voltage.

For this reason, in the conventional output buffer circuit described above, depending on the voltage used, a voltage higher than the maximum operating voltage inside the LSI may be applied between the gate and source of the transistor of the output buffer circuit. However, there is a problem that deterioration of the transistor cannot be sufficiently prevented.

Further, when the process conditions at the time of manufacturing change in the direction in which the threshold value of the transistor decreases, the potential difference between any two terminals increases, which acts in the direction in which the breakdown voltage of the transistor decreases. There is also a problem.

Therefore, the present invention has been made in view of the above problems, and has as its object to output a voltage level higher than the operating voltage inside an LSI to the outside.
To provide a high-voltage output buffer circuit without increasing manufacturing costs due to additional manufacturing process steps, and to provide an output buffer circuit that minimizes transistor deterioration and reduces LSI power consumption. is there.

[0013]

In order to achieve the above object, an output buffer circuit according to the present invention comprises: an output terminal; an output circuit comprising a Pch transistor and an Nch transistor connected to the output terminal; A level shift circuit that converts the voltage level of the output voltage from a low voltage to a high voltage, a control circuit that controls the state of the output buffer, and an intermediate potential generation circuit that controls the gate voltage of the transistor of the output circuit and the level shift circuit. The voltage generated by the intermediate potential generating circuit can be easily changed by switching the wiring, and the current flowing to the ground (GND) is cut off by a control signal during standby or when the high-voltage output buffer is not used. .

[0014]

Embodiments of the present invention will be described below. In a preferred embodiment of the output buffer circuit of the present invention, the intermediate potential generation circuit (2 in FIG. 1)
, A voltage VPM of an intermediate level between the high voltage power supply (VDDH) and the GND level is generated, and the voltage is applied to the level shift circuit (see FIG. 13) of the output buffer circuit and the transistors of the output circuit (4 in FIG. 1). , The gate voltage of the Pch enhancement type transistor using VDDH is at least VPM + | VTP |
(VTP is the threshold voltage of the Pch enhancement type transistor), it is possible to sufficiently improve the gate breakdown voltage and prevent the transistor from being deteriorated.

The output voltage VPM of the intermediate potential generating circuit (2 in FIG. 1) varies the number of diode-connected Pch enhancement type transistors easily by switching the wiring, and sets the voltage according to the capacity of the output buffer. In addition, when a standby state or a high-voltage output buffer is not used, the power consumption can be reduced by cutting off a current outflow path to GND by a control signal (STOP).

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing a configuration of an output buffer circuit according to a first embodiment of the present invention. Referring to FIG. 1, the output buffer circuit according to the present embodiment includes a control circuit 1, an intermediate potential generating circuit 2, a level shift circuit 3, and an output circuit 4, which are a total of four circuit blocks.

Next, a control circuit 1, an intermediate potential generating circuit 2,
The detailed configuration of the four blocks of the level shift circuit 3 and the output circuit 4 will be described.

The control circuit 1 is a circuit for controlling whether the output buffer circuit is activated or deactivated by a control signal EN. An inverter gate 6 to which the control signal EN is input, and an input signal DATA And a control signal EN as inputs, and a NOR gate 8 as an input which receives the output of the inverter gate 6 and the input signal DATA.
It is composed of

In this circuit, when the EN signal is at "H" level, the output buffer circuit is activated and the input signal D
The state of ATA is transmitted to output terminal 5 via output circuit 4. When the EN signal is at the “L” level, the output buffer circuit is inactive, the output terminal 5 is in a high impedance state, and the state (logic level) of the input signal DATA is not transmitted to the output terminal 5.

The intermediate potential generation circuit 2 is a circuit for generating a voltage input to the gates of the P-channel enhancement type transistors of the level shift circuit 3 and the output circuit 4. This circuit includes a high voltage power supply VDDH and a low voltage power supply V
DDL is used.

The intermediate potential generating circuit 2 includes a high voltage power supply VDD
On the H side, a plurality of diode-connected P-channel enhancement type transistors (referred to as “Pch transistors”) 9 to 13 are connected in series, and a resistor 14 and an N-channel enhancement type transistor (referred to as “Nch transistor”) are connected in series. ) 15 is connected.

An N-channel non-doped transistor 18 is connected to the low-voltage power supply VDDL, and a gate of the N-channel non-doped transistor 18 is a connection point (node G) between the diode-connected Pch transistor row and the resistor 14.
Is connected. In FIG. 1, the potential of the node G is diode-connected from the high-voltage power supply potential VDDH and is lower by a threshold voltage of three stages of the Pch transistors 9, 10, and 11 (the gate-drain connection point of the Pch transistor 11). (Potential of the node C).

An Nch transistor 16 is connected in series with the N-channel non-doped transistor 18, and its gate is connected to the N-channel transistor 15 in common.
4 and the connection point of the Nch transistor 15, the transistors 15 and 16 constitute a current mirror circuit.

An Nch transistor 1 is connected to the GND side.
Nc between the commonly connected sources 5 and 16 and GND
h transistor 17 and a control signal S
Connect the inverted signal of TOP, and input the “H” level to the control signal STOP to turn off the intermediate potential generating circuit 2 during standby or when the high-voltage output buffer circuit is not used.
State (the transistor 17 is turned off to cut off the current path), and the current outflow to the GND side is cut off.

A signal VPM is extracted from a connection point between the N-channel non-doped transistor 18 and the enhancement type Nch transistor 16 and supplied to the level shift circuit 3 and the output circuit 4.

The level shift circuit 3 converts the highest voltage level of the signal input to the output buffer circuit from the low voltage power supply potential VDDL to the high voltage power supply potential VDDH, and the lowest voltage level is VPM + | VTP |, ( Where V
TP is a circuit for generating a signal of the threshold voltage of the Pch transistor.

The Pch transistors 20, 21 connected in series to the high voltage power supply VDDH side and the Nch transistors 24, 25 connected in series to the GND side are connected. Similarly, connected between the high voltage power supply VDDH and GND,
Another set of Pch transistors 22 and 23 and Nch transistors 26 and 27 is provided.

The gates of the Pch transistors 20 and 22 are connected to each other with a cross. The gates of the Pch transistors 21 and 23 are made common, and are connected to the signal VPM generated by the intermediate potential generation circuit 2.

N enhancement type transistor 24,
26 has a common gate, and receives a low-voltage power supply potential VDDL.

H and K signals are generated from the signal A from the control circuit 1 via two inverter gates 28 and 29 and input to the gates of the Nch transistors 25 and 27, respectively.

From the connection point (node P) of the Pch transistors 22 and 23, the highest voltage level is higher than the high voltage power supply potential V
A signal having a minimum voltage level of VPM + | VTP | at DDH is extracted and input to the output circuit 4.

The output circuit 4 comprises Pch transistors 30 and 31 and N enhancement type transistors 32 and 33 connected in series between VDDH and GND.

An output signal Y is extracted from a connection point between the Pch transistor 31 and the Nch transistor 32 and connected to the output terminal 5.

The gate of the Pch transistor 30 receives a signal P (potential at the node P) from the level shift circuit 3, and the gate of the Pch transistor 31 receives a signal VPM from the intermediate potential generating circuit 2.

The low voltage power supply potential VDDL is input to the gate of the Nch transistor 32, and the Nch transistor 3
The signal B from the control circuit 1 is input to 3.

Next, the operation of the output buffer circuit of the present embodiment configured as described above will be described with reference to the timing chart of FIG.

First, assuming that VDDH> VDDL, at time t
1, the EN signal of the control circuit 1 is “H” (VDD
L), the STOP signal of the intermediate potential generating circuit 2 becomes “L” (G
ND), the output buffer circuit is activated, and the operation of transmitting the state of the input signal DATA to the output terminal 5 becomes possible.

When the input signal DATA is at the "H" level (VDD
L), the output A of the control circuit 1 becomes “L” (GND) and the output B becomes “L” (GND) via the NAND gate 7 and the NOR gate 8, and the level shift circuit 3 and the output circuit 4 respectively. Is entered.

Since the signal STOP is at "L" level (GND), the intermediate potential generating circuit 2 is activated,
Diode-connected Pch transistor array and resistor 14
Is determined by VDDH, the threshold value of the Pch transistor and the value of the resistor 14,
The value is substantially lower than VDDH by the threshold value | VTP | of the diode-connected Pch transistor.

For example, when the Pch transistor has three diode connections, the potential at the node G is VDDH-3 × | VTP |.

The potential at the node G becomes the gate voltage of the N-channel non-noop transistor 18, and the voltage VPM between the N-channel non-noop transistor 18 and the Nch transistor 16 becomes VDDH−3 × which is almost the same potential as the node G. |
VTP |.

The voltage VPM changes in conjunction with the value of VDDH, and the fluctuation range is VDDL ≧ VPM ≧ VDDH−3 × | VTP |.

The potential at the node G can be changed by switching wiring between CD and EF.

For example, when the wiring between the CDs is cut off, the potential of the node G becomes VDDH−4 × | VTP |, and when the wiring between the EFs is also cut off, the potential of the node G becomes VDDH−5 × | VTP | Can be

As described above, since the voltage VPM also changes in conjunction with the potential of the node G, the voltage VPM can be adjusted to an appropriate level according to the capacity of the output buffer.

"L" (GND) of the output A of the control circuit 1 is input to the level shift circuit 3, and the inverter gate 2
8 and 29, the node H becomes the “H” level (VDD)
L), the node K becomes the “L” level (GND), and Nch
Transistor 25 is OFF, Nch transistor 2
7 is turned on, and the potential of the node M (source of the transistor 26) becomes GND.

Since the gate voltages of the Nch transistors 24 and 26 are VDDL, the potential of the node L (the source of the transistor 24) is VDDL-VTN.

Here, VTN is the threshold voltage of the Nch transistor.

When the Nch transistor 25 is in the OFF state, N
Since the channel transistor 27 is in the ON state, the potential of the node P is pulled down to the GND side and lowers, and acts to turn the Pch transistor 20 on.

When the Pch transistor 20 is turned on, the node N (the drain of the transistor 20)
Is pulled toward VDDH and becomes higher, and Pc
It works to turn off the h transistor 22.

Since the gate voltages of the Pch transistors 21 and 23 are the voltage VPM generated by the intermediate potential generating circuit 2, the potential of the node N is finally VDDH, and the potential of the node P is more than that of the Pch transistor. VPM + | VTP | which is higher by the threshold voltage | VTP |

On the other hand, the Nch transistor 3 of the output circuit 4
The gate voltage of the Nch transistor 3 is the node potential of the output B of the control circuit 1 and is GND.
3 is in the OFF state.

The gate voltage of the Nch transistor 32 is V
Since the potential of the node S (the source of the transistor 32) is higher than that of the VDDL,
VDDL-VTN lower by the threshold voltage VTN of
Becomes

Since the gate voltage of the Pch transistor 30 is VPM + | VTP | and the source voltage is VDDH, the Pch transistor 30 is turned on, and the potential of the node R becomes VDDH.

Since the gate voltage of the Pch transistor 31 is the voltage VPM from the intermediate potential generating circuit 2,
The transistor 31 is turned on, and the potential of the node Y becomes V
DDH. Therefore, the VDDH level is output to the output terminal 5.

Similarly, the operation can be described when the input signal DATA of the control circuit 1 is "L" (GND) at time t2. In this case, the Nch transistor 33
Is turned ON because the gate voltage is VDDL at the node B, and the potential of the node S becomes GND. The gate voltage of the Nch transistor 32 is also VDDL, and the Nch transistor 32 is turned on. The gate voltage of the Pch transistor 30 is
, And becomes an OFF state. Also, Pc
Since the gate voltage of the h transistor 31 is VPM,
The potential of the node R is higher than VPM by the threshold voltage | VTP | of the Pch transistor 31 by the voltage VPM + | VT.
P |. Therefore, the GND level is output to the output terminal 5.

At times t3 and t4, the EN signal goes to the "L" level (GND), the node B goes to the "L" level (GND), and the point P goes to the "H" level (VDDH). It becomes a high impedance state. Therefore, the state of the input signal DATA is not transmitted to the output terminal.

In this manner, the amplitude is changed from GND to VDDL.
, An output signal having an amplitude of GND to VDDH can be output to the output terminal.

In the output buffer circuit of this embodiment, first, in the intermediate potential generating circuit 2, a voltage VPM sufficiently lower than VDDH determined by the threshold voltage | VTP | of the Pch transistor is generated, and the voltage and VPM + | VTP | Is applied to the terminals of arbitrary Pch transistors of the level shift circuit 3 and the output circuit 4, and VDDL and VDDL-VT
Since the configuration is such that the voltage of N is applied to the terminal of an arbitrary Nch transistor, a high voltage can be output while the gate breakdown voltage of each transistor is sufficiently maintained.

The intermediate potential generating circuit 2 can be realized with a low current consumption of several μA by employing a current mirror configuration. By providing the control signal STOP, the control signal can be controlled during standby or when the output buffer is not used. "H" level (VDDL) is input to STOP and Nc
By turning off the h transistor 17, current outflow to GND can be cut off. At this time, from VDDH to VD
Although a very small current flows through the DL, it is effectively used for reducing the power supply current of the VDDL use circuit.

Since the voltage VPM when the intermediate potential generating circuit 2 is in the OFF state is lower than the VDDL level by the threshold voltage of the N-channel non-doped transistor, there is no particular problem in operation.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a diagram showing the configuration of the second embodiment of the present invention.

Referring to FIG. 3, the gates of Nch transistors of level shift circuit 3 and output circuit 4 are connected to VDDL
Is the voltage VNM generated by the intermediate potential generating circuit 34.

The configuration of the intermediate potential generating circuit 34 is such that several Nch transistors diode-connected to the GND side are connected in series, and a resistor 36 and a Pch transistor 35 are connected to the VDDL side in series with these diode-connected Nch transistors. The signal VNM is taken out from between the connected and diode-connected Nch transistor array and the resistor 36.

The control signal STOP is input to the gate of the Pch transistor 35, and the Pch transistor is turned off during standby or when the output buffer is not used, and
Reduce the current consumption of DDL.

In this embodiment, the intermediate potential generating circuit 34
Is higher than the GND level by the threshold voltage of the diode-connected Nch transistor, and there is no particular problem in operation.

When the output buffer circuit is active, the voltage V
Although NM is determined by the threshold voltage VTN of the Nch transistor and the value of the resistor 36, the threshold voltage VTN of the diode-connected Nch transistor is substantially smaller than that of GND.
The voltage becomes higher by the minute.

For example, when the number of diode connections of the Nch transistor is four, it becomes GND + 4 × VTN.

The voltage VNM slightly changes depending on the value of VDDL, and the fluctuation range is VDDL ≧ VNM ≧ GND + 4 × VTN.

The operation of the second embodiment of the present invention is basically the same as the operation of the first embodiment. However, in the first embodiment, the Nch transistors of the level shift circuit 3 and the output circuit 4 are used. The voltage VDDN is inputted to the gate at the time, the voltage becomes VNM, and the potential of each contact at the time of operation is VDDL−
What has been VTN is replaced with VNM-VTN.

Further, similarly to the intermediate potential generating circuit 2, the voltage V
NM is changed by changing the wiring between the nodes TU and VW.
The voltage can be changed to GND + 5 × VTN and GND + 6 × VTN, and the voltage VNM can be changed according to the capacity of the output buffer.

According to the output buffer circuit of the present invention, VPM = VDDH− (the number of diode-connected Pch transistors) × | VTP |
VNM = GND + (the number of diode-connected Nch transistors) × VTN is generated, and VPM or VPM + | VTP | is applied to the gate terminal of an arbitrary Pch transistor.
, Or VDDL (or VNM) or に VDDL to the terminal of an arbitrary Nch transistor.
By applying a voltage of (or VNM) -VTN}, the potential difference between any two terminals of the Pch transistor can be maximized by | (the number of diode-connected Pch transistors).
× VTP |, and the voltage between any two terminals of the Nch transistor is set to | VDDH- (N
(the number of channel transistors) × VTN | (however, if VDDL is larger than | VDDH− (the number of diode-connected Nch transistors) × VTN |, VDDL), the gate withstand voltage of the transistor is sufficiently secured. Thus, an output signal having an amplitude of GND to VDDH can be output to the output terminal.

[0074]

As described above, according to the output buffer circuit of the present invention, the potential difference between any two terminals of the Pch transistor can be maximized by the intermediate potential generation circuit, |
(Number of diode-connected Pch transistors) × VTP |
And the maximum voltage between any two terminals of the Nch transistor is | VDDH− (the number of diode-connected Nch transistors) × VTN | (where VDDL is | VDD.
H− (number of diode-connected Nch transistors) × VT
If it is larger than N |, it can be VDDL).
An output signal having an amplitude of GND to VDDH can be output to the output terminal after sufficiently securing the gate breakdown voltage of the transistor.

The reason is that the intermediate potential generating circuit
A voltage of PM = VDDH− (number of diode-connected Pch transistors) × | VTP | and VNM = GND + (number of diode-connected Nch transistors) × VTN is generated, and VPM or VPM + | VTP is applied to a terminal of an arbitrary Pch transistor. | Voltage or any Nch
By applying a voltage of VDDL (or VNM) or VDDL (or VNM) -VTN to the terminal of the transistor, the potential difference between any two terminals of the Pch transistor can be maximized by | (the number of diode-connected Pch transistors) × VTP | And the voltage between any two terminals of the Nch transistor is | VDDH− (the number of diode-connected Nch transistors) × VTN | (where VD
When DL is larger than | VDDH− (the number of diode-connected Nch transistors) × VTN |, VDD
L).

Therefore, according to the present invention, it is possible to configure a high-voltage output buffer circuit that prevents an increase in manufacturing cost due to the addition of a manufacturing process step and that eliminates deterioration of a transistor due to insufficient gate breakdown voltage.

Further, according to the present invention, the intermediate potential generating circuit has a current mirror connection configuration, thereby enabling low current consumption operation, and interrupting the current outflow to GND by the control signal, thereby enabling the standby state of the LSI during standby. In addition to reducing unnecessary current consumption when the high-voltage output buffer circuit is not used, the current consumption of the low-voltage power supply VDDL can be effectively used, and a low-power-consumption LSI can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of an output buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of each unit of the output buffer circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a circuit configuration of an output buffer circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional output buffer circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 control circuit 2 intermediate potential generation circuit 3 level shift circuit 4 output circuit 5 output terminal 6, 19, 28, 29 inverter gate 7 NAND gate 8 NOR gate 9 to 13 Pch enhancement transistor 15 to 17 Nch enhancement transistor 18 Nch non-doped transistor 20 -23 Pch enhancement transistor 24-27 Nch enhancement transistor 31 Pch enhancement transistor 32, 33 Nch enhancement transistor 34 Intermediate potential generation circuit 35 Pch enhancement transistor 36 Resistance 37-42 Nch enhancement transistor 44 Level shift circuit 45 Output circuit 46 Pch enhancement transistor 47 Nch Enhancement Transis

Claims (7)

[Claims] An output terminal and a P terminal connected to the output terminal.
An output circuit including a channel transistor and an n-channel transistor; and a level shift circuit for converting a voltage level of an input signal to limit a gate voltage input to the p-channel transistor and the n-channel transistor of the output circuit. When a gate voltage to be input to the transistors of the output circuit and the level shift circuit is generated, and a high voltage output buffer is not used by a control signal, a ground (GN)
D) an intermediate potential generating circuit for blocking outflow of current to the side, and an output buffer circuit comprising: 2. An output circuit for outputting a high-voltage power supply level from an output terminal, and a level conversion of a voltage level of an input signal of an internal circuit for low-voltage power supply operation, which is input to P-channel transistors and N-channel transistors of the output circuit. And an intermediate potential generating circuit for generating an intermediate level voltage (VPM) between the high voltage power supply and the ground level, and a voltage (VPM) output from the intermediate potential generating circuit.
Is applied to the transistors of the level shift circuit and the output circuit, and the voltage supplied to the gate of the P-channel transistor connected to the high-voltage power supply is at least VPM + | P-channel transistor. An output buffer circuit characterized in that the threshold voltage | 3. The output voltage of the intermediate potential generating circuit can be variably set by changing the number of connected diode-connected P-channel transistors. Output buffer circuit. 4. The circuit according to claim 1, wherein the intermediate potential generating circuit includes means for interrupting a current outflow path to the ground side by a value of a control signal in a standby state or when a high-voltage output buffer is not used.
3. The output buffer circuit according to claim 2, wherein: 5. An output circuit for outputting a high-voltage power supply level from an output terminal, and a voltage level of a signal from an internal circuit for low-voltage power supply operation being level-converted and input to a P-channel transistor and an N-channel transistor of the output circuit. Level shift circuit, and an intermediate potential generating circuit for generating a voltage of an intermediate level between the high voltage power supply and the ground level, wherein the intermediate potential generating circuit is diode-connected to the high voltage power supply potential VDDH. Absolute value of the threshold value of the P-channel transistor | VTP |
M) and supplies the same to the level shift circuit and the P-channel transistor of the output circuit. The level shift circuit changes the maximum voltage level of the input signal from the low voltage power supply potential VDDL to the high voltage power supply potential VDL.
DDH and the minimum voltage level is VPM
An output buffer circuit, which supplies + | VTP | to a gate of a P-channel transistor of the output circuit. 6. An output circuit for outputting a high-voltage power supply level from an output terminal, and a voltage level of a signal from an internal circuit for low-voltage power supply operation being level-converted and input to a P-channel transistor and an N-channel transistor of the output circuit. Level shift circuit, and an intermediate potential generating circuit for generating a voltage of an intermediate level between the high voltage power supply and the ground level, the number of stages in which the intermediate potential generating circuit is diode-connected to the high voltage power supply potential VDDH. And outputs a voltage (VPM) lower by the absolute value | VTP | of the threshold value VTP of the P-channel transistor to the level shift circuit and the P-channel transistor of the output circuit. From the low voltage power supply potential VDDL to the high voltage power supply potential VDL.
DDH and the minimum voltage level is VPM
+ | VTP | to the gate of the P-channel transistor of the output circuit, and the voltage between two terminals of the level shift circuit and the P-channel transistor forming the output circuit is diode-connected to the intermediate potential generation circuit. An output buffer circuit, wherein the number of stages is N, and the output buffer circuit is configured not to exceed (high voltage power supply potential VDDH) −N × | VTP |. 7. The intermediate potential generating circuit outputs a voltage (VNM) that is higher than a ground level by a threshold value of the number of stages of diode-connected N-channel transistors, and outputs an N level of the level shift circuit and the output circuit. Voltage to the gate of the N-channel transistor of the output circuit.
NM- (VTN is the threshold value of the N-channel transistor)
7. The output buffer circuit according to claim 6, wherein