JPH1032565A - Detection circuit for excess/missing clock signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detection circuit for excess/missing clock signal that detects an excess/missing state of clock signals with a small configuration scale even when the number of clock signals configuring a frame is large. SOLUTION: This detection circuit is a circuit that detects an excess state of clock signals where an 'H' is inserted between 'Hs' of a clock signal CLK and detects a missing state of clock signals where an 'H' is missing between 'Hs' of a clock signal CLK. A 1/2 frequency divider circuit 101 applies 1/2 frequency division to the clock signal CLK and a latch circuit 102 is used to generate a pulse for a prescribed period each of the clock signal CLK to latch 1/2 frequency division data of the 1/2 frequency divider circuit 101 with the reception of a frame pulse signal FP denoting one frame between pulses. Then the latch circuit 102 outputs latched when data 1/2 frequency division data on the occurrence of add number bit excess/missing state in a preceding frame are latched by a pulse input of this frame as excess missing state detection data ERR and a reset generating circuit 103 is used to reset the 1/2 frequency divider circuit 101 when the pulse and the detection data ERR are inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock surplus / extraction detection circuit. In the signal transmission system, the clock surplus / extraction detection circuit uses a clock signal that alternates between the “L” level and the “H” level transmitted from the transmission device and received by the reception device, for example, “..., H, H,
… ”And“ H ”continue,“…, H, L, L,
L, H,... And "H" are missing, and a circuit as small as possible is demanded.

[0002]

2. Description of the Related Art A conventional clock surplus / extraction detection circuit includes:
A frame pulse signal synchronized with a clock signal that generates a pulse every n cycles of the clock signal is input to a frame counter to count, and a carry-out signal output when the frame counter counts up and a previous input signal By comparing the phase with the frame pulse signal and detecting that both phases are shifted, the surplus / extracted state of the clock signal is detected.

[0003]

In the above-mentioned conventional clock surplus / extraction detection circuit, a frame counter for counting the number of clock signals in one frame, which is the pulse interval of the frame pulse signal, is required. There has been a problem that as the number of clock signals constituting one frame is larger, the counter for counting the number is larger and the entire circuit becomes larger.

The present invention has been made in view of such a point, and even when the number of clock signals constituting one frame is large, it is possible to detect the surplus / extracted state of the clock signal with a small-scale configuration. It is an object to provide a clock surplus / extraction detection circuit.

[0005]

FIG. 1 shows the principle of the present invention. The clock surplus / missing detection circuit shown in FIG. 3 detects a surplus state in which the “H” level is inserted between the “H” levels of the clock signal CLK and a missing state in which the “H” level is omitted. A divide-by-two circuit 101 that divides the frequency of the clock signal CLK by two, and a divide-by-two circuit 101 that generates a pulse at regular intervals of the clock signal CLK and receives a pulse of a frame pulse signal FP whose pulse interval indicates one frame The divided data is retained, and the retained data obtained when the surplus / extraction state of the odd-numbered bits occurred in the previous frame when the surplus / extraction state occurred in the previous frame is retained as the surplus / extraction state detection data ERR. Holding circuit 10 that outputs as
2 and a divide-by-2 circuit 1 when the detection data ERR is input.
And a reset generation circuit 103 for resetting 01.

According to such a configuration, when a surplus / extraction state of an odd number of bits occurs in the previous frame, when the pulse indicating the head of the current frame is input to the holding circuit 102, the pulse is output from the divide-by-2 circuit. Since the output divide-by-2 data is at a level opposite to the normal state in which no surplus / extraction state occurs, the holding circuit 102 holds the opposite level, so that the detection data of the normal level and the opposite level is detected. Will be output.

At this time, the divide-by-2 circuit 101 is reset by the reset generation circuit 103.
Even if a tooth extraction state occurs, it can be detected.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing the configuration of the clock surplus / extraction detection circuit according to the first embodiment of the present invention. In the first embodiment shown in FIG. 2, portions corresponding to the respective portions in the principle diagram shown in FIG. 1 are denoted by the same reference numerals.

In FIG. 2, reference numeral 101 denotes a flip-flop (F) constituting a divide-by-2 circuit indicated by the same reference numeral 1 in FIG.
F), and the data inversion output terminal XQ and the data input terminal D are connected. Reference numeral 102 denotes an FF which constitutes a holding circuit indicated by the same reference numeral 102 in FIG. 1. The data input terminal D is connected to the data inversion output terminal XQ of the FF 101, the frame pulse signal FP is input to the clock terminal CK, and the data output The end Q outputs an error signal ERR indicating a surplus / extracted state of the clock signal CLK.

Reference numeral 103 denotes a NAND circuit which constitutes a reset generation circuit denoted by the same reference numeral 103 in FIG. 1, and has one input terminal connected to the data output terminal Q of the FF 102 and the other input terminal receiving the frame pulse signal FP. , And the output end is FF
101 is connected to the inverting reset terminal XR.

The clock surplus / extraction detection circuit of the first embodiment having the above-described configuration is provided with a clock signal CLK in a normal state.
The operation in the case where is input will be described with reference to FIG. However, as shown in FIG. 3, the "H" level pulse of the frame pulse signal FP is synchronized with the falling edge of the clock signal CLK, and
It is generated every period (ten). Also, a numerical value indicating the number of the clock signal CLK is given at the "H" position.

That is, the frame pulse signal FP becomes "H" at the falling edge of the first clock signal CLK, becomes "L" at the second falling edge, and becomes "H" at the eleventh falling edge. , "L" at the twelfth falling edge, "H" at the twenty-first falling edge, ...

When the first rising edge of the clock signal CLK is input to the clock terminal CK of the FF 101, the output data D1 of the FF 101 becomes "L" and the frame pulse signal is generated at the timing of the first falling edge. When the FP rises to “H”, the “L” of the data D1 is held in the FF 102, and the output data D2 of the FF 102 remains “L”.

Since "L" of the data D2 is supplied to one input terminal of the NAND circuit 103, the NAND circuit 10
3 remains at "H". Thereafter, the rising edge of the second or subsequent clock signal CLK is F
Each time the data is input to F101, the output data D1 becomes “L”,
Repeat "H".

At the eleventh falling edge, the frame pulse signal FP indicates "H" indicating the beginning of the second frame.
However, at this time, since "L" of the data D1 is supplied to the data input terminal D of the FF 102, the data D2 remains "L" and the data D3 remains "H" as in the first frame. . Thereafter, the same operation is repeated.

Next, the operation when the clock signal CLK in the 1-bit missing state is input will be described with reference to FIG. However, in FIG. 4, portions corresponding to the respective portions in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the fifth and seventeenth clock signals CLK shown in FIG. 4 are in a state of missing one bit, ie, a state where "H" is missing. Up to the fourth data is the same as the normal state shown in FIG. 3, but since the fifth “H” is missing, the output data D1 of the FF101 is output until the sixth rising edge is input. It remains at "H". That is,
The data D1 becomes "L" at the sixth rising edge, and thereafter, "H" and "L" are repeated for each rising edge sequentially input to the eleventh.

Here, when the level of the data D1 that changes from the sixth rising edge is compared with the normal state in FIG. 3, it can be seen that the level is inverted. This is because the omission occurred in the fifth frame. For this reason, “H” of the frame pulse signal FP indicating the beginning of the second frame is set to FF.
When the FF 102 is input to the FF 102, the 11th level at this time is “H”, so “H” is held in the FF 102.

As a result, the output data D2 of the FF 102
Becomes "H", that is, the error signal ERR becomes "H" which indicates that the clock signal CLK of the first frame is missing. Also, when the data D2 becomes “H”, the frame pulse signal FP is also “H”, so the output data D3 of the NAND circuit 103 becomes “L”, and this “L” is supplied to the inverting reset terminal XR of the FF101. FF10
1 is reset, and even if the twelfth rising edge is input to the FF 101, the output data D1 is "H".
Will remain.

Thereafter, when the frame pulse signal FP becomes "L" at the twelfth falling edge, the NAND circuit 1
03 output data D3 becomes “H”. After that, when the thirteenth rising edge is input to the FF101, the output data D1 becomes “L”.
"H" and "L" are repeated for each rising edge sequentially input.

Next, since the 17th "H" is missing, the output data D1 of the FF 101 remains "H" until the 18th rising edge is input. That is,
The data D1 becomes "L" at the eighteenth rising edge, and thereafter, "H" and "L" are repeated for each of the sequentially input rising edges until the twenty-first data.

Here, when the level of the data D1 changing from the eighteenth rising edge is compared with the normal state shown in FIG. 3, it can be seen that the level is inverted. This is 1
This is due to the omission of the seventh frame. For this reason, when "H" of the frame pulse signal FP indicating the beginning of the three frames is input to the FF 102, the 31st level at this point becomes "H". Therefore, “H” is held in the FF 102.

As a result, the output data D2 of the FF 102
Becomes "H", that is, the error signal ERR becomes "H" indicating that the clock signal CLK of the third frame is missing. In the example shown in FIG. 4, the number of missing bits in one frame is one, but if the number of missing bits in the previous frame is an odd number, the frame pulse signal F
When P rises to "H" indicating the beginning of the next frame, the output data D1 of the data inversion output terminal XQ of the FF 101 becomes the opposite level to the normal state, and this inverted level becomes F
It is held in F102 and output as an error signal ERR.

In the case where the clock signal CLK is in a surplus state, it can be detected in the same manner as in the case where the clock signal CLK is missing. For example, in FIG. 4, when one “H” is excessively added between the fourth and fifth “H” of the clock signal CLK, the level state of the output data D1 of the FF 101 becomes the fifth Is in the same state as in the case where "H" is missing.

According to the first embodiment described above, even if the number of clock signals in one frame is large, the surplus / extraction state of the clock signal is detected by a small-scale clock extra / extraction detection circuit. be able to.

Next, a second embodiment will be described with reference to FIG. However, in each part of the second embodiment shown in FIG. 5, the same parts as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 5, reference numeral 111 denotes a divide-by-2 circuit using an FF, and a data inversion output terminal XQ of the FF 111
And the data input terminal D are connected. Reference numeral 112 denotes a selector circuit using a two-input type selector. One input terminal A of the selector 112 is connected to the data output terminal Q of the FF 111, and the other input terminal B is connected to the data inversion output terminal XQ of the FF 111. .

Reference numeral 113 denotes a holding circuit using an FF.
A data input terminal D of F113 is connected to a data output terminal Q of the selector 112, a frame pulse signal FP is input to a clock terminal CK, and output data D16 of the data output terminal Q is an error signal ERR. It is supposed to be.

Reference numeral 114 denotes an AND circuit 115 and a selector 11
6 and a selector signal generating circuit using the FF 117. One input terminal of the AND circuit 115 is connected to the data output terminal Q of the FF 113, and the frame pulse signal F
P is to be input. Also, the selector 116
One input terminal A is connected to the data output terminal Q of the FF 117, the other input terminal B is connected to the data inversion output terminal XQ of the FF 116, and the selection control terminal S is connected to the output terminal of the AND circuit 115. Further, the data input terminal D of the FF 117 is connected to the data output terminal Q of the selector 116, the clock signal CLK is input to the clock terminal CK, and the data output terminal Q
Is connected to the selection control terminal S of the selector 112.

The clock surplus / extraction detection circuit of the second embodiment having the above-described configuration is provided with a clock signal CLK in a normal state.
The operation in the case where is input will be described with reference to FIG. The first rising edge of the clock signal CLK is FF
When the data is input to the clock terminal CK of the flip-flop 111, the output data D13 of the data output terminal Q of the FF 111 becomes "L" and the output data D14 of the data inversion output terminal XQ becomes "H". Inversion is repeated at the rising edge of the clock signal CLK at the opposite level.

When "L" of the output data D18 of the FF 117 is supplied to the selection control terminal S, the selector 112 selects the supply data D13 of one input terminal A and selects the FF 113
To the data input terminal D, and output data D18 at "H"
Is supplied to the selection control terminal S, the supply data D14 of the other input terminal B is selected and the data input terminal D of the FF 113 is selected.
Output to Here, since the data D18 remains "L", the data D13 is selected, and this is set as F15 as data D15.
Output to F113.

The FF 113 holds the data D15 at each rising edge of the clock signal CLK, and transfers the data D15 to the data D15.
Since the data D15 is output as "16", the data D15 is "L" at the timing of the rising edge, so that the state becomes "L" constant.

The AND circuit 115 takes the logical product of the data D16 and the frame pulse signal FP and outputs the result as data D17. Here, since the data D16 is "L", the data D17 is also in the "L" constant state.

The selector 116 sets "L" of the data D17.
Is supplied to the selection control terminal S, the supply data D18 of one input terminal A is selected, and the data input terminal D of the FF 117 is selected.
When the “H” of the data D17 is supplied to the selection control terminal S, the supply data D19 of the other input terminal B is selected and output to the data input terminal D of the FF 117. Here, since the data D17 remains at "L", the data D18 is selected and output to the FF 117.

Since the FF 117 holds the output data of the selector 116 in response to the clock signal CLK, the FF 117 holds "L" of the output data D18 of the selector 116, whereby the output data D19 of the data inversion output terminal XQ becomes "L". H ”is constant.

Next, the operation when the clock signal CLK in the 1-bit missing state is input will be described with reference to FIG. However, in FIG. 7, portions corresponding to the respective portions in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the fifth and seventeenth clock signals CLK shown in FIG. 7 are in a state where one bit is missing, that is, a state where "H" is missing. Up to the fourth data is the same as the normal state shown in FIG. 6, but since the fifth “H” is missing, the output data D13 of the FF 111 is output until the sixth rising edge is input. It remains at "H", and the output data D14 remains at "L".

That is, the data D13 becomes "L" at the sixth rising edge, and thereafter, "H" and "L" are repeated for each sequentially input rising edge up to the eleventh.
The data D14 becomes "H", and thereafter, "L" and "H" are repeated for each of the rising edges sequentially inputted up to the eleventh.

Here, when the levels of the data D13 and D14 that change from the sixth rising edge are compared with the normal state in FIG. 6, it can be seen that the levels are inverted.
Since the data D18 is "L" for the eleventh data, the selector 112 selects the data D13,
Is output to the FF 113.

When the frame pulse signal FP rises to "H" at the eleventh falling edge, the FF 113 holds the data D15 at "H". As a result, the data D
16 becomes "H". That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the first frame is missing.

Since the AND circuit 115 takes the logical product of "H" of the data D16 and "H" of the frame pulse signal FP, the output data D17 becomes "H". The selector 116 supplied with this “H” to the selection control terminal S selects “H” of the data D19 supplied to the other input terminal B and outputs it to the FF 117, and the “H” is the twelfth rising edge. Output data D of the FF 117
18 is "H" and the output data D19 is "L".

Further, when the data D18 is "H", the selector 112 sets the input data D1 of the other input terminal B to "H".
Since 4 is selected, the data D15 becomes "H" from the eleventh rising edge to the thirteenth rising edge, and thereafter becomes equal to the level of the data D14.

Next, since the 17th "H" is missing, the output data D13 of the FF 111 remains "L" until the 18th rising edge is input, and the data D14 becomes "H". Will remain. That is, the data D13 becomes “H” at the 18th rising edge, and 21
"L" and "H" are repeated for each sequentially input rising edge until the data becomes "L" in the data D14, and "H" and "L" are sequentially obtained for each sequentially input rising edge until the 21st data. "repeat.

Here, since the data D18 is "H" up to the 22nd, the selector 112 selects the data D14,
This is output to the FF 113 as data D15. 21
When the frame pulse signal FP rises to “H” at the second falling edge, the FF 113 holds “H” of the data D15. As a result, the data D16 becomes "H".
Becomes That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the second frame is missing.

Further, since the AND circuit 115 takes the logical product of "H" of the data D16 and "H" of the frame pulse signal FP, the output data D17 thereof becomes "H". The selector 116 supplied with this “H” to the selection control terminal S selects “L” of the data D19 supplied to the other input terminal B and outputs it to the FF 117, and the “L” is the 22nd rising edge Output data D of the FF 117
18 is "L" and the output data D19 is "H".

In the example shown in FIG. 7, the number of missing bits in one frame is one. If the number of missing bits in a frame is odd, the head of the next frame is also indicated. At the time of rising to "H", the missing tooth state can be detected.

In the case where the clock signal CLK is in a surplus state, it can be detected in the same manner as in the case where the clock signal CLK is missing. For example, in FIG. 7, when one “H” is excessively added between the fourth and fifth “H” of the clock signal CLK, the level state of the output data of the FF 111 becomes the fifth Since the state is the same as the case where "H" is missing, it can be detected in the same manner as the 1-bit missing state.

In the second embodiment described above, the first
The same effect as in the embodiment can be obtained. Next, a third embodiment will be described with reference to FIG. However, in each part of the third embodiment shown in FIG. 8, the same parts as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 8, reference numeral 121 denotes a first frequency-dividing circuit using an FF, which is connected to a data inversion output terminal XQ and a data input terminal D of the FF 121, and has a frame pulse signal connected to a clock terminal CK. FP is input.

Reference numeral 122 denotes a second divide-by-2 circuit using an FF. The data inversion output terminal XQ of the FF 122 is connected to the data input terminal D, and the data output terminal Q of the FF 121 is connected to the inversion reset terminal XR. The clock signal CLK is input to the clock terminal CK.

Reference numeral 123 denotes a third divide-by-2 circuit using FFs. The inverted data output terminal XQ of the FF 123 is connected to the data input terminal D, and the inverted data output terminal XQ of the FF 121 is connected to the inverted reset terminal XR. Clock end C
The clock signal CLK is input to K.

Reference numeral 124 denotes a holding circuit using an FF.
The data input terminal D of F124 is connected to the data inversion output terminal XQ of FF122, and the frame pulse signal FP is input to the clock terminal CK.

Reference numeral 125 denotes a holding circuit using an FF.
The data input terminal D of F125 is connected to the data output terminal Q of FF123, and the frame pulse signal F is applied to the clock terminal CK.
P is to be input.

Reference numeral 126 denotes an OR circuit, one input terminal of which is FF
124 is connected to the data output terminal Q and the other input terminal is FF1
25, and the output data D28 is used as an error signal ERR.

The clock surplus / tooth extraction detection circuit of the third embodiment having such a configuration is provided with a clock signal CLK in a normal state.
The operation in the case where is input will be described with reference to FIG. F
Each time the rising edge of the frame pulse signal FP is input to the clock terminal CK of F121, its data output terminal Q
Output data D23 repeats "H" and "L". Also, “H” of the data D23 is the inverted reset terminal X of the FF122.
While the FF 122 is supplied to the clock signal CL.
K is divided by two, and as a result, the output data D24 is inverted every rising edge of the clock signal CLK. At this time, the data D23 is applied to the inverted reset terminal XR of the other FF123.
Is supplied, so that the output data D25 becomes "L" due to the reset state.

The FF 124 holds "L" of the data D24 at the rising edge of the first frame pulse signal FP, so that the output data D26 becomes "L", and the FF 125 outputs the rising edge of the first frame pulse signal FP. Holds the "L" of the data D25, so that the output data D27 becomes "L", and the OR circuit 1 outputs the logical sum of the two data D26 and D27 and outputs the result.
The output data D28 of "26" becomes "L".

When the data D23 is inverted to "L" at the second rising edge of the frame pulse signal FP, the FF 122 is reset to output data D2.
3 is “L”, and the FF 123 repeats inversion at the rising edge of the clock signal CLK.

Next, the operation when the clock signal CLK in the 1-bit missing state is input will be described with reference to FIG. However, in FIG. 10, parts corresponding to the respective parts in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the fifth and seventeenth clock signals CLK shown in FIG. 10 are missing one bit, that is, "H" is missing. Up to the fourth data is the same as the normal state shown in FIG. 9, but since the fifth “H” is missing, the output data D24 of the FF 123 is output until the sixth rising edge is input. It remains at "H".

That is, the data D24 becomes "L" at the sixth rising edge, and "H" and "L" are repeated for each rising edge sequentially inputted up to the eleventh.
Here, it can be seen that the level of the data D24 that changes from the sixth rising edge is inverted when compared with the normal state in FIG.

When the frame pulse signal FP rises to "H" at the eleventh falling edge, the FF 124 holds "H" of the data D24, and thereby the data D2
6 becomes "H", and the FF 125 holds "L" of the data D25, whereby the data D27 becomes "L". As a result, the output data D28 of the OR circuit 126 becomes "H". That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the first frame is missing.

When the frame pulse signal FP rises to "H" at the eleventh falling edge, the data D23 goes to "L", so that the FF 122 is reset, whereby the data D24 goes to "L". Becomes
Further, the other FF 123 enters a state of dividing the clock signal CLK by two.

Next, since the seventeenth "H" is missing, the output data D25 of the FF 123 remains "H" until the eighteenth rising edge is input. That is, the data D25 becomes "L" at the eighteenth rising edge, and thereafter, "H" and "L" are repeated for each of the sequentially input rising edges until the twenty-first data.

When the frame pulse signal FP rises to "H" at the twenty-first falling edge, the FF 125 holds "H" of the data D25, and thereby the data D2
7 becomes "H", and as a result, the output data D28 of the OR circuit 126 becomes "H". That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the second frame is missing.

When the frame pulse signal FP rises to "H" at the 21st falling edge, the data D23 becomes "H", so that the FF 123 is in the reset state, whereby the data D25 becomes "L". Becomes
Further, the other FF 122 enters a state of dividing the frequency of the clock signal CLK by two.

In the third embodiment described above, the same effect as in the first embodiment can be obtained. If the number of missing bits in a frame is an odd number, the missing state can be detected when the frame pulse signal FP indicating the beginning of the next frame rises to "H". In the case of a surplus state, it is possible to detect it in the same way as in the toothless state.

Next, a fourth embodiment will be described with reference to FIG. However, in each part of the fourth embodiment shown in FIG. 11, the same parts as those of the third embodiment shown in FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 11, reference numeral 136 denotes a selector circuit using a two-input type selector.
36, one input terminal A is a data inversion output terminal XQ of the FF 122
And the other input terminal B is connected to the data output terminal Q of the FF123.
And the selection control terminal S is connected to the data input terminal D of the FF 121.

Reference numeral 137 denotes a holding circuit using an FF.
The data input terminal D of F137 is the data output terminal Q of the selector.
And the frame pulse signal FP is applied to the clock terminal CK.
, And the output data D37 becomes an error signal ERR.

The clock surplus / extraction detection circuit of the fourth embodiment having the above-described configuration is provided with a clock signal CLK in a normal state.
The operation in the case where is input will be described with reference to FIG.
The selector 136 selects the input data D24 of one input terminal A when the data 23 is "H", selects the input data D25 of the other input terminal B when the data 23 is "L", and outputs the selected data as data D36. .

The FF 137 holds the data D36 at the rising edge of the frame pulse signal FP, and outputs the held data D37 as an error signal ERR.
In this case, "L" of the data D36 is held at the leading rising edge of the frame pulse signal FP, and the data D3
7 is "L", "L" is held at the next rising edge, and the data D37 becomes "L".

Next, an operation when a clock signal CLK in a 1-bit missing state is input will be described with reference to FIG. However, in FIG. 13, parts corresponding to the respective parts in FIG. 12 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the fifth and seventeenth clock signals CLK shown in FIG. 13 are in a state where one bit is missing, that is, a state where "H" is missing. In this case, data D24 and D24
5 becomes the data D36, and when the frame pulse signal FP rises to “H” at the eleven falling edges of the clock signal CLK, the FF 137 holds the “H” of the data D24 (data D36). Data D
37 becomes “H”. That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the first frame is missing.

When the frame pulse signal FP rises to “H” at the 21st falling edge, the FF 13
7 holds “H” of data D25 (data D36),
As a result, the data D37 becomes “H”. That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the second frame is missing.

In the fourth embodiment described above, the same effects as in the third embodiment can be obtained. If the number of missing bits in a frame is an odd number, the missing state can be detected when the frame pulse signal FP indicating the beginning of the next frame rises to "H". In the case of a surplus state, it is possible to detect it in the same way as in the toothless state.

Next, a fifth embodiment will be described with reference to FIG. However, in each part of the fifth embodiment shown in FIG. 14, the same parts as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 14, reference numeral 141 denotes a 2 ^n- ary counter. In this case, a quaternary counter 141 is used. The frame pulse signal FP is input to the load terminal LO via the inverter 144, and the clock terminal CK is supplied to the load terminal LO. Clock signal CLK is input.

Reference numeral 142 denotes a coincidence detection circuit using a two-input type selector. Reference numeral 143 denotes a holding circuit using an FF. One input terminal A of the selector 142 is connected to the data output terminal Q of the FF 143, and the other input terminal. End B is inverter 145
Is connected to the carry-out terminal CO of the quaternary counter 141, the data output terminal Q is connected to the data input terminal D of the FF 143, and the frame pulse signal FP is input to the selection control terminal S. . Also, FF143
The clock signal CLK is input to a clock terminal CK of the clock signal CK. The output data D46 of the data output terminal Q of the FF 143 becomes the error signal ERR.

The clock surplus / extraction detection circuit of the fifth embodiment having the above-described configuration is provided with a clock signal CLK in a normal state.
The operation in the case where is input will be described with reference to FIG.
However, as shown in FIG. 15, the “H” level pulse of the frame pulse signal FP is synchronized with the rising edge of the clock signal CLK, and
It is generated every four periods (n + 4).
Also, a numerical value indicating the number of the clock signal CLK is given at the "H" position.

That is, the frame pulse signal FP becomes “H” at the rising edge of the first clock signal CLK, becomes “L” at the second rising edge, “H” at the (n + 5) th rising edge, and n + 6. "L",... At the second rising edge.

When the frame pulse signal FP rises at the first rising edge of the clock signal CLK, the output data D43 at the carry-out end CO becomes "H",
Output data D44 of inverter 145 is “L”.

The selector 142 selects "L" of the input data D44 of the other input terminal B when the frame pulse signal FP is "H". "L" of this selection data D45 is F
In F143, the signal is held at the rising edge of the clock signal CLK, and thereby the output data D46 becomes "L".

Further, the quaternary counter 141 sets the “L” of the frame pulse signal FP to “H” via the inverter 144.
While the clock signal CLK is supplied to the load end LO, the counting operation is performed by the rising edge of the clock signal CLK.
Thereby, the output data D43 of the carry-out end CO is output.
Becomes “H” every four bits.

Next, the operation when the clock signal CLK in the 1-bit missing state is input will be described with reference to FIG. However, in FIG. 16, the portions corresponding to the respective portions in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the fifth clock signal CLK shown in FIG. 16 is in a 1-bit missing state, that is, a state where "H" is missing. In this case, since the counting operation of the quaternary counter 141 is delayed by one bit from the normal state at the fifth position, the carry-out end CO is detected at the sixth rising edge.
Output data D43 becomes “H”. Thereafter, the counting operation is performed in the same manner as in the normal state, and the data D43 becomes “H” every four bits.

When the frame pulse signal FP rises at the (n + 5) th rising edge of the clock signal CLK,
The selector 142 selects “H” of the data D44, and the selected data D45 becomes “H”, and the next n
FF143 is data D4 at the + 6th rising edge
When “H” of No. 3 is held, the data D46 becomes “H”. That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the first frame is missing.

In the fifth embodiment described above, the same effects as in the first embodiment can be obtained. If the number of missing bits in a frame is within 2 ⁿ -1 bits, the missing state can be detected when the frame pulse signal FP indicating the beginning of the next frame rises to "H". In a case where the clock signal CLK is in a surplus state, it can be detected in the same manner as in the case where the tooth is missing.

Next, a sixth embodiment will be described with reference to FIG. However, in each part of the sixth embodiment shown in FIG. 17, the same parts as those of the fifth embodiment shown in FIG. 14 are denoted by the same reference numerals, and the description thereof will be omitted. In FIG.
51 is a decoder, both input terminals of which are inverting terminals,
An AND circuit 152 to which the first and second output terminals of the quaternary counter 141 are connected, an input terminal to be an inverting terminal, another input terminal to be connected to the first bit of the quaternary counter 141, and two bits An AND circuit 153 having an inverting end connected to the output end of the quaternary counter 141; an inverting end connected to the first bit of the quaternary counter 141; and an other input end connected to the second bit output end And an AND circuit 154 connected thereto.

The match detection circuit 142 is provided with the selector 1
55, 156, and 157. The holding circuit 143 includes FFs 158, 159, and 160. One input terminal A of the selector 155 is connected to the data output terminal Q of the FF 158.
, And the other input terminal B is connected to the output terminal of the AND circuit 152. One input terminal A of the selector 156 is FF1
The other input terminal B is connected to the output terminal of the AND circuit 153. Selector 157
One input terminal A is connected to the data output terminal Q of the FF 160, and the other input terminal B is connected to the output terminal of the AND circuit 154.

The selectors 155, 156, 157
The frame pulse signal FP is input to the selection control terminal S, and the clock signal CLK is input to the clock terminal CK of each of the FFs 158, 159, and 160. Furthermore, each FF15
The output data D59 of 8, 159 and 160 is an error signal ERR3 indicating a 3-bit missing state, and the output data D61 is an error signal ERR indicating a 2-bit missing state.
2, and the output data D63 is an error signal ERR1 indicating a 1-bit missing state.

The clock surplus / extraction detection circuit of the sixth embodiment having the above-described configuration is provided with the clock signal CLK in the normal state.
The operation in the case where is input will be described with reference to FIG.
The output data D53 of the first bit of the quaternary counter 141 is inverted at every rising edge of the clock signal CLK.
The data becomes frequency-divided data, and the output data D54 of the second bit becomes frequency-divided data that is inverted every falling edge of the data D53.

The output data D55 of the decoder 151
Is "H" when both data D53 and D54 are "L", and output data D56 is "H" when data D53 is "H" and data D54 is "L",
The output data D57 is such that the data D53 is “L” and the data D
It becomes “H” when 54 is “H”. Thereafter, in this normal state, the data D58 to D63 become "L".

Next, the operation when the clock signal CLK in the 1-bit missing state is input will be described with reference to FIG. However, in FIG. 19, parts corresponding to the respective parts in FIG. 18 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the fifth clock signal CLK shown in FIG. 19 is in a state where one bit is missing, that is, "H" is missing. In this case, the "L" of the first bit output data D53 of the quaternary counter 141 is one bit longer than the normal state at the fifth bit, and becomes "H" at the sixth rising edge. Output data D of the bit
54 is also extended by one bit, and the output data D55, D56, and D57 of the decoder 151 are shifted by one bit "H" from the normal state.

Thereafter, 4 from the seventh falling edge
Data D5 of the 1st and 2nd bits of the binary counter 141
3, D54 is in the same level state as in the normal state. Then, a frame pulse signal FP indicating the head of the second frame
Rises at the (n + 5) th, the “H” of the data D57 having the same timing as the phase of this “H” becomes the selector 1
57, the selected data D62 becomes "H", and this "H" is held by the FF 160 at the (n + 6) th rising edge, and the held data D63 becomes "H". That is, the error signal ERR1 becomes “H” indicating that the 1-bit clock signal CLK has missed one bit.

In the sixth embodiment described above, the same effects as in the fifth embodiment can be obtained. The number of missing bits in the frame is 1 to 2 ⁿ -1 bits.
The number of missing bits can be detected, and the surplus state of the clock signal CLK can be detected similarly to the missing state.

Next, a seventh embodiment will be described with reference to FIG. However, in each part of the seventh embodiment shown in FIG. 20, the same parts as those in the fifth embodiment shown in FIG. 14 are denoted by the same reference numerals, and the description thereof will be omitted.

The seventh embodiment shown in FIG. 20 is different from the fifth embodiment shown in FIG. 14 in that a spare clock extra / dropout detection circuit having the same configuration as the fifth embodiment is added. is there. However, the clock signal C described in the fifth embodiment
Let LK be CLK0 and let the backup clock signal used in the seventh embodiment be CLK1. Clock signal CL
It is assumed that K0 and CLK1 are synchronized.

In FIG. 20, reference numeral 171 denotes a quaternary counter, to which a frame pulse signal FP is input to a load terminal LO via an inverter 174, and a clock terminal CK.
Is supplied with a clock signal CLK1.

Reference numeral 172 denotes a match detection circuit using a two-input type EXOR circuit (exclusive OR circuit).
One input terminal of the R circuit 172 is connected to the carry-out terminal CO of the quaternary counter 141, and the other input terminal is connected to the carry-out terminal CO of the other quaternary counter 171.

Reference numeral 173 denotes a holding circuit using an FF whose data input terminal D is fixed at "H".
It is connected to the output terminal of the XOR circuit, and the frame pulse signal FP is input to the reset terminal R.

An OR circuit 175 has one input terminal connected to the data output terminal Q of the FF 143, the other input terminal connected to the data output terminal Q of the FF 173, and the output data D.
74 becomes the error signal ERR.

The clock surplus / extraction detection circuit of the seventh embodiment having the above-described configuration is supplied with the clock signal CLK in the normal state.
The operation in the case where is input will be described with reference to FIG.
However, description of the same portions as those in FIG. 15 of the operation explanation timing chart of the fifth embodiment is omitted.

In this case, the output data D71 of the carry-out end CO of the quaternary counter 171 is at the same level as the output data D43 of the carry-out end CO of the other quaternary counter 141, so that the output data D72 of the EXOR circuit 172 is output. Is "L", FF output data D73, OR circuit 1
The 75 output data D74 also becomes “L”.

Next, the operation when the clock signal CLK0 in the 4-bit missing state is input will be described with reference to FIG. However, in FIG. 22, parts corresponding to the respective parts in FIG. 21 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the third to sixth four bits of the clock signal CLK shown in FIG.
In this case, since the counting operation of the quaternary counter 141 is delayed by 4 bits, the output data D43 of the carry-out end CO becomes “H” at the ninth rising edge. Thereafter, the counting operation is performed in the same manner as in the normal state, and the data D43 becomes 4
It becomes "H" for each bit.

On the other hand, since the other quaternary counter 171 normally performs the counting operation, the output data D71 becomes “H” at the first, fifth, and ninth rising edges. When the fifth data D71 becomes "H", the other data D43 is "L", so the EXOR circuit 172
Output data D72 becomes “H”, which is FF173
, The output data D73 of the FF 173 becomes “H” and the output data D74 of the OR circuit 175 becomes “H”.

Therefore, in this case, the missing state occurring in one frame can be detected in the same frame. When the frame pulse signal FP rises in the second frame, the FF 173 is reset. Therefore, the output data D73 is “L” and the output data D7 of the OR circuit 175 is “L”.
4 becomes “L”.

In the seventh embodiment described above, the same effects as in the fifth embodiment can be obtained. In addition, even ^{if the} number of missing bits in the frame is 2 ⁿ bits, the missing state can be detected, and the surplus state of the clock signal CLK can be detected similarly to the missing state. Further, by using the clock signal CLK1 of another system, a surplus / extraction detection circuit is added, so that the detection accuracy can be improved.

Next, an eighth embodiment will be described with reference to FIG. However, in each part of the eighth embodiment shown in FIG. 23, the same parts as those in the first embodiment shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 23, reference numeral 181 denotes a first divide-by-2 circuit using an FF. The data inversion output terminal XQ and the data input terminal D of the FF 181 are connected to each other, and the clock terminal C is connected.
The clock signal CLK is input to K. 182 is a delay circuit, which is a clock signal CLK.
186 for delaying a half cycle of the
And an inverter 187 that inverts the clock signal CLK delayed by the clock signal CLK.

Reference numeral 183 denotes a second frequency-dividing circuit using an FF, which is connected to the data inverting output terminal XQ and the data input terminal D of the FF 183, and connected to the clock terminal CK by an inverter 187.
The output data D87 is input.

Reference numeral 184 denotes a coincidence detection circuit using a two-input type EXNOR circuit. One input terminal of the EXNOR circuit 184 is connected to the data output terminal Q of the FF 183, and the other input terminal is connected to the data output terminal Q of the FF 181. Have been.

Reference numeral 185 denotes a holding circuit, and FFs 188 and 1
89, and the data input terminal D of the FF188 is E
The clock terminal C is connected to the output terminal of the XNOR circuit 184.
K, the clock signal CLK is input, the data output terminal Q is connected to the clock terminal CK of the FF189,
9, the frame pulse signal FP is input to the reset terminal R, and the output data D89 of the data output terminal Q is output as the error signal E.
It is configured to be RR.

The clock surplus / extraction detection circuit of the eighth embodiment having the above-described configuration is supplied with the clock signal CLK in the normal state.
Will be described with reference to FIG.
However, as shown in FIG. 24, the “H” level pulse of the frame pulse signal FP is synchronized with the rising edge of the clock signal CLK, and n +
It is generated every four periods (n + 4).
Also, a numerical value indicating the number of the clock signal CLK is given at the "H" position.

That is, the frame pulse signal FP becomes “H” at the rising edge of the first clock signal CLK, becomes “L” at the second rising edge, “H” at the (n + 5) th rising edge, and n + 6. "L",... At the second rising edge.

In the FF 181, the level of the output data D83 is inverted every time the rising edge of the clock signal CLK is input. Further, the clock signal CLK is delayed by a half cycle by the delay 186, and thereafter, the inverter 187
The clock signal CLK (data D85) input to the clock terminal CK of the FF 183 is
This is delayed by one bit from the clock signal CLK input to F181.

Since the EXNOR circuit 184 takes the negative logic of the exclusive OR of the data D83 and D86, when the levels of the input data D83 and D86 are different, the output data D87 becomes "L". . This "L"
Is held by the FF 188 at the rising edge of the frame pulse signal FP, and the held data D88 is “L”.
Becomes Data D88 is applied to the clock terminal CK of the FF189.
Is output, the output data D89 (error signal ERR) also becomes "L".

Next, the operation in the case where the clock signal CLK in the 1-bit missing state is input will be described with reference to FIG. However, in FIG. 25, portions corresponding to the respective portions in FIG. 24 are denoted by the same reference numerals, and description thereof will be omitted.

It is assumed that the sixth clock signal CLK shown in FIG. 25 is in a 1-bit missing state. in this case,
Since the sixth “H” is missing, the output data D83 of the FF 181 remains “H” until the seventh rising edge is input.

That is, the data D83 becomes "L" at the seventh rising edge, and "H" and "L" are repeated for each successively input rising edge. Here, when the level of the data D83 that changes from the seventh rising edge is compared with the normal state in FIG. 24, it is found that the level is inverted.

The output data D84 of the delay 186
Also, since the sixth "H" is missing, it remains at "L" until the seventh falling edge is input, and the seventh falling edge is also input to the inverted data D85. Until "H" is reached.

Thereafter, every time the seventh falling edge is sequentially input, "H", like the clock signal CLK,
Repeat "L". Further, such data D85 is 2
The output data D86 of the FF 183 to be frequency-divided is
The output data D83 has a waveform delayed by one bit.

Here, the data D extended by the sixth missing tooth
Since “H” of 83 and D86 overlap at the same timing by one bit, the output data D87 of the EXNOR circuit 184 becomes “H” at this overlapping portion, and this “H” is held in the FF 188 at the seventh rising edge. The rising edge of “H” of the held data D88 is input to the clock terminal CK of the FF189, so that the output data D8
9 becomes “H”. That is, the error signal ERR becomes “H” indicating that the clock signal CLK of the first frame is missing.

Thereafter, when the frame pulse signal FP of the second frame rises, the FF 189 is reset and the error signal ERR becomes "L". In the eighth embodiment described above, the same effect as in the first embodiment can be obtained. If the number of missing bits in the frame is n, the missing state can be detected in the same manner, and the surplus state of the clock signal CLK can be detected in the same manner as the missing state.

[0126]

As described above, according to the clock surplus / extraction detection circuit of the present invention, even if the number of clock signals constituting one frame is large, the surplus / extraction state of the clock signal can be reduced in a small-scale configuration. There is an effect that can be detected.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram illustrating a configuration of a clock surplus / extraction detection circuit according to the first embodiment of the present invention.

FIG. 3 shows the clock surplus / clock according to the first embodiment shown in FIG. 2;
6 is a timing chart for describing an operation when a clock signal in a normal state is input to the tooth extraction detection circuit.

FIG. 4 shows the clock surplus / clock according to the first embodiment shown in FIG. 2;
6 is a timing chart for explaining an operation when a clock signal in a 1-bit missing state is input to the tooth extraction detecting circuit.

FIG. 5 is a diagram illustrating a configuration of a clock surplus / extraction detection circuit according to a second embodiment of the present invention.

FIG. 6 shows a clock surplus / second signal according to the second embodiment shown in FIG. 5;
6 is a timing chart for describing an operation when a clock signal in a normal state is input to the tooth extraction detection circuit.

FIG. 7 shows the clock surplus / second signal according to the second embodiment shown in FIG. 5;
6 is a timing chart for explaining an operation when a clock signal in a 1-bit missing state is input to the tooth extraction detecting circuit.

FIG. 8 is a diagram showing a configuration of a clock surplus / extraction detection circuit according to a third embodiment of the present invention.

FIG. 9 shows a clock surplus / second signal according to the third embodiment shown in FIG. 8;
6 is a timing chart for describing an operation when a clock signal in a normal state is input to the tooth extraction detection circuit.

FIG. 10 is a timing chart for explaining an operation when a 1-bit missing clock signal is input to the clock surplus / extraction detection circuit according to the third embodiment shown in FIG. 8;

FIG. 11 shows the clock surplus /
It is a figure showing composition of a tooth extraction detection circuit.

FIG. 12 is a timing chart for explaining an operation when a clock signal in a normal state is input to the clock surplus / extraction detection circuit according to the fourth embodiment shown in FIG. 11;

FIG. 13 is a timing chart for explaining an operation when a clock signal in a 1-bit missing state is input to the clock surplus / extraction detection circuit according to the fourth embodiment shown in FIG. 11;

FIG. 14 shows a clock surplus / five according to a fifth embodiment of the present invention.
It is a figure showing composition of a tooth extraction detection circuit.

FIG. 15 is a timing chart for explaining an operation when a clock signal in a normal state is input to the clock surplus / tooth extraction detection circuit according to the fifth embodiment shown in FIG. 14;

FIG. 16 is a timing chart for explaining an operation when a clock signal in a 1-bit missing state is input to the clock surplus / extraction detection circuit according to the fifth embodiment shown in FIG. 14;

FIG. 17 shows the clock surplus / according to the sixth embodiment of the present invention;
It is a figure showing composition of a tooth extraction detection circuit.

FIG. 18 is a timing chart for explaining an operation when a clock signal in a normal state is input to the clock surplus / extraction detection circuit according to the sixth embodiment shown in FIG. 17;

FIG. 19 is a timing chart for explaining an operation when a clock signal in a 1-bit missing state is input to the clock surplus / extraction detection circuit according to the sixth embodiment shown in FIG. 17;

FIG. 20 shows the clock surplus / according to the seventh embodiment of the present invention.
It is a figure showing composition of a tooth extraction detection circuit.

FIG. 21 is a timing chart for describing an operation when a clock signal in a normal state is input to the clock surplus / tooth extraction detection circuit according to the seventh embodiment shown in FIG. 20;

FIG. 22 is a timing chart for explaining an operation when a clock signal in a 4-bit missing state is input to the clock surplus / extraction detection circuit according to the seventh embodiment shown in FIG. 20;

FIG. 23 shows the clock surplus / according to the eighth embodiment of the present invention.
It is a figure showing composition of a tooth extraction detection circuit.

FIG. 24 is a timing chart for explaining an operation when a clock signal in a normal state is input to the clock surplus / tooth extraction detection circuit according to the eighth embodiment shown in FIG. 23;

FIG. 25 is a timing chart for describing an operation when a 1-bit missing clock signal is input to the clock surplus / extraction detection circuit according to the eighth embodiment shown in FIG. 23;

[Explanation of symbols]

 101 frequency dividing circuit 102 holding circuit 103 reset generation circuit CLK clock signal FP frame pulse signal ERR clock surplus / extraction detection data (error signal)

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H03K 23/00 H03K 23/00 B (72) Inventor Toru Matsumoto 4 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Chome 1-1 Fujitsu Limited

Claims (8)

[Claims] 1. The method according to claim 1, wherein the "H" level is between "H" levels of the clock signal.
In a clock surplus / extraction detection circuit for detecting a surplus state in which a level is inserted and a missing state in which an "H" level is omitted, a frequency dividing circuit for dividing the clock signal by 2, a frame synchronized with the clock signal A circuit for holding the frequency-divided data of the frequency-dividing circuit by a pulse input of a pulse signal, wherein the frequency-divided data obtained when a surplus / extraction state of an odd-numbered bit occurs in a previous frame is a pulse of a current frame. A holding circuit that outputs held data when held by an input as the surplus / extraction state detection data; and a reset generation circuit that resets the divide-by-2 circuit when the detection data is input. And a clock surplus / extraction detection circuit. 2. An "H" level between "H" levels of a clock signal.
In a clock surplus / extraction detection circuit for detecting a surplus state in which a level is inserted and a missing state in which an "H" level is omitted, a divide-by-2 circuit for dividing the clock signal by 2, and an output of the divide-by-2 circuit A selector circuit for selecting one of data and inverted output data in accordance with a selector signal; and a circuit for holding selected data in the selector circuit by a pulse input of a frame pulse signal synchronized with the clock signal, wherein And a holding circuit for outputting, as the surplus / extraction state detection data, the retained data when the selected data is retained by the pulse input of the current frame when the surplus / extraction state of an odd number of bits occurs. And a selector signal generation circuit for outputting the selector signal for the selector circuit to select another output data of the divide-by-2 circuit when is input. A clock surplus / extraction detection circuit, comprising: 3. An "H" level between "H" levels of a clock signal.
In a clock surplus / extraction detection circuit for detecting a surplus state in which a level is inserted and a missing state in which an "H" level is omitted, a first divide-by-2 circuit for dividing a frame pulse signal synchronized with the clock signal by 2 A second divide-by-2 circuit that divides the clock signal by 2 and outputs inverted divide-by-2 data obtained by inverting the divide-by-2 data; And a circuit for holding the inverted divide-by-two data in response to a pulse input of the frame pulse signal, which is used when a surplus / extraction state of an odd number of bits occurs in the previous frame. A first holding circuit that outputs held data when the inverted 2 frequency-divided data is held by a pulse input of the current frame as the surplus / extraction state detection data; Circumference data A circuit for holding, the detection of the surplus / extracted state of the retained data when the frequency-divided-by-2 data at the time of occurrence of surplus / extracted state of an odd-numbered bit in the previous frame is retained by the pulse input of the current frame. A second holding circuit for outputting data as data, wherein one of the second and third divide-by-2 circuits is activated by the output divide-by-2 data of the first divide-by-2 circuit And a clock surplus / extraction detection circuit. 4. An "H" level between "H" levels of a clock signal.
In a clock surplus / extraction detection circuit for detecting a surplus state in which a level is inserted and a missing state in which an "H" level is omitted, a first divide-by-2 circuit for dividing a frame pulse signal synchronized with the clock signal by 2 A second divide-by-2 circuit that divides the clock signal by 2 and outputs inverted divide-by-2 data obtained by inverting the divide-by-2 data; A second divide-by-two circuit that outputs, a selector circuit that selects output data of any one of the second and third divide-by-two circuits performing the divide-by-two operation, And a holding circuit for holding as a frame pulse signal and outputting it as surplus / extraction state detection data of an odd number of bits, wherein the second and third data are output according to the output divide-by-2 data of the first divide-by-2 circuit. One of the two frequency divider circuits operates Together are state, clock surplus / tooth 抜検 detection circuit, characterized in that either the output data of the second and third divide-by-two circuit in the operating state so as to select the selector circuit. 5. An "H" level between "H" levels of a clock signal.
In a clock surplus / extraction detection circuit for detecting a surplus state in which a level is inserted and a missing state in which an "H" level is omitted, a clock signal is loaded with a frame pulse signal synchronized with the clock signal, and a 2 ^n- ary count is performed using the clock signal. Perform the operation 2
and ^n-ary counter, the 2 and ^n-ary counter carry-out data, detects a match between the phase of the pulse of the frame pulse signal FP, in the case of disagreement, the 2 ⁿ -1 bits in the previous frame surplus /
A clock surplus comprising: a coincidence detection circuit for detecting occurrence of a tooth extraction state; and a holding circuit for holding non-coincidence data of the coincidence detection circuit and outputting it as surplus / extraction state detection data. / Tooth extraction detection circuit. 6. A decoder for decoding a count value of the 2 ^n-ary counter, said the 2 ^n-ary counter connected between said coincidence detection circuit, said decoder matching the phase of the pulse of the frame pulse signal FP 6. The decoding circuit according to claim 5, wherein the holding circuit holds the decoded value and outputs the detected data as the detection data, whereby it is possible to detect how many bits of the clock signal are in a surplus / extracted state. Clock surplus / extraction detection circuit. 7. Loading with the frame pulse signal,
A second 2 ^n-ary counter for performing 2 ^n-ary counting in the clock signal different from the other-system clock signal, the coincidence of the level of carry-out data and the second 2 ^n-ary counter the 2 ^n-ary counter A second match detection circuit for detecting that a ^2n- bit surplus / extracted state has occurred in the clock signal when a mismatch is detected, and holding the mismatch data of the second match detection circuit. 6. The clock surplus / extraction detection circuit according to claim 5, further comprising a second holding circuit that outputs surplus / extraction state detection data. 8. An "H" level between "H" levels of a clock signal.
In a clock surplus / extraction detection circuit for detecting a surplus state in which a level is inserted and a missing state in which an "H" level is omitted, a first divide-by-2 circuit for dividing the clock signal by two, A delay circuit that delays one cycle, a second divide-by-2 circuit that divides the clock signal delayed by the delay circuit by 2, and a divide-by-2 data of the first and second divide-by-2 circuits a coincidence detection circuit for detecting occurrence of a surplus / extraction state of n bits; a retention circuit for retaining detection data of the coincidence detection circuit and being reset by a pulse input of a frame pulse signal synchronized with the clock signal; A clock surplus / extraction detection circuit characterized by comprising: