JP4206780B2 - Rotation position detector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a rotational position detection device that detects a reference position based on an angle signal including an unequal period generated in synchronization with the rotation of an object.
[0002]
[Prior art]
As this type of rotational position detection device, there are those described in Patent Documents 1 to 3. Among them, the rotational position detection device for an internal combustion engine described in Patent Documents 1 and 2 detects a reference position based on a comparison between a ratio of adjacent pulse periods in a pulse train of angle signals and a predetermined determination value K. And an up / down counter and an f / K frequency divider circuit (see FIG. 13). Here, the f / K frequency dividing circuit generates a down clock by combining a 1/3 frequency-divided clock and a 1/2 frequency-divided clock.
[0003]
This rotational position detection device measures the period of a pulse train by up-counting a predetermined clock, and detects the reference position by generating a borrow by down-counting the down clock from the number of clocks. According to this configuration, even when a relatively low frequency clock is used, the determination value K including a decimal point can be set.
[0004]
On the other hand, the toothpick sensor circuit described in Patent Document 3 is configured by using only an up counter without using an up / down counter in order to simplify the circuit.
[0005]
[Patent Document 1]
JP-A-5-66105
[0006]
[Patent Document 2]
JP-A-5-71909
[0007]
[Patent Document 3]
JP-A-5-93603
[0008]
[Problems to be solved by the invention]
FIG. 13 shows an example of the configuration of a rotational position detection device similar to that of Patent Document 2, and FIG. 14 shows the operation waveform thereof. In this rotational position detection device 1, the angle signal NE output from the rotation sensor 2 via the waveform shaping circuit 3 is divided by half by the frequency divider circuit 4, and the two up / down counters 5 and 6 Up-counting and down-counting are repeated alternately for each period of the signal. The up / down counters 5 and 6 count in the opposite directions (up / down), up-count by the clock CLK from the clock generation circuit 7, and down-count by the frequency-divided clock from the 1 / K frequency divider circuit 8. . Clock supply to the up / down counters 5 and 6 is controlled by the selectors 9 and 10. When the edge detection circuits 11 and 12 detect the up edge of the angle signal NE, the up / down counters 5 and 6 are reset. According to the above configuration, when the rotation sensor 2 detects the missing tooth portion that is the reference position, the borrow signal BO is output from one of the up / down counters 5 and 6.
[0009]
However, since this rotational position detection apparatus 1 includes two up / down counters 5 and 6 and a 1 / K frequency dividing circuit 8, the circuit scale becomes large, and when an IC is formed, the chip area increases and the cost increases. There is a problem of becoming higher.
[0010]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a rotational position detection device capable of reducing the circuit scale as compared with the conventional configuration.
[0011]
[Means for Solving the Problems]
According to the means described in claim 1, the clock pulse generating means generates the first and second clock pulses that are two-phased so that there is no overlapping period. A multiplexed operation can be performed by selecting the first counting means and the second counting means corresponding to the first clock pulse and the second clock pulse, respectively. That is, the first counting unit measures each period of the angle signal output from the angle signal generating unit by up-counting the first clock pulse, and the second counting unit performs the first counting in parallel with this. Two clock pulses are counted to obtain an n-ary counter value.
[0012]
The decoding means decodes the n-ary count value and generates a permission pulse corresponding to the m count values among the n count values. The third counting means is in phase with the operation of the second counting means, and counts down the count value measured by the first counting means corresponding to the permission pulse, so that the presence / absence of a borrow, etc. Based on this, it is possible to detect an unequal period (reference position) in the angle signal.
[0013]
Such multiplexing is performed when the operation of the first counting means for counting up and the operation of the third counting means for counting down need to proceed simultaneously with respect to the periodic angle signal, that is, in down-counting. The second counting means for generating the necessary permission pulse is also an effective means for removing redundant components when it is necessary to operate in parallel with the first counting means.
[0014]
In the present invention, since the operations of the first counting means and the second counting means are multiplexed by time division, the count value of the holding means possessed by the components that are not used at the same time, that is, each counting means, is incremented and a new value is obtained. Incrementing means for input values can be shared. As a result, it is possible to omit a part of the increment means conventionally required for each count means, and to reduce the circuit scale as compared with the conventional configuration.
[0015]
According to the means described in claim 2, the increment means includes a common incrementer, a common data bus for returning the count value of each holding means to the input side of each holding means via the incrementer, and the data It is composed of common selection means that is provided in the bus and gives a predetermined reset value to each holding means instead of the count value. According to this configuration, the first and second counting means can share the incrementer, the data bus, and the selection means.
[0016]
According to the means described in claim 3, by using the common selection means, the holding means of the first count means is reset corresponding to the predetermined edge of the angle signal, and the second The holding means of the counting means can be reset every radix n.
[0018]
Claim 4 According to the means described above, the crank angle of the internal combustion engine can be detected with high accuracy.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
A first embodiment of a rotational position detection device that detects a crank angle of an internal combustion engine will be described below with reference to FIGS.
FIG. 1 shows the overall electrical configuration of the rotational position detection device. The rotational position detector 21 includes an angle signal generator 22 that outputs an angle signal NE, an edge detection circuit 23 that detects an up edge of the angle signal NE, a clock generator circuit 24 that outputs a synchronization clock CLK of the entire system, a clock A two-phase circuit 25 that generates clocks CK0 and CK1 with two-phase CLK, a counter 26 that counts up the clock CK0 and measures each cycle of the angle signal NE, and an n-ary that counts up the clock CK1 (this embodiment) In quinary), the counter 27, the decode circuit 28 that decodes the count value of the counter 27 and outputs the enable signal EN and the reset signal RST, the count value of the counter 26 is decreased in synchronization with the clock CLK using the enable signal EN as a permission pulse. Counter 29 for counting and preset signal generation times And a AND gate 30 is.
[0020]
Hereinafter, a specific configuration of each component will be described. In addition, the specific waveform and generation timing of each signal are shown in the timing chart shown in FIG. The angle signal generator 22 (corresponding to angle signal generating means) outputs a signal corresponding to the rotational position of the crankshaft or camshaft 31 (corresponding to the object) of the internal combustion engine. On the outer periphery of the rotor 32 attached to the crankshaft or camshaft 31, for example, two teeth out of 36 teeth 32a provided at equal intervals of 10 ° CA are missing at the reference position. A portion 32b is formed. A rotation sensor 33 including an electromagnetic pickup, a hall sensor, an optical sensor, and the like is provided at a position facing the teeth 32a on the outer peripheral portion of the rotor 32. An output signal of the rotation sensor 33 is a waveform shaping circuit 34. , The waveform is shaped into a rectangular wave and becomes an angle signal NE.
[0021]
As shown in FIG. 4, the edge detection circuit 23 includes three D flip-flops 35, 36, and 37 connected in cascade, and a clock CK 0 is input to each clock input terminal CK via an inverter 38. It has come to be. The AND gate 39 generates an edge detection signal NEEG0 from the non-inverted output signal of the first-stage flip-flop 35 and the inverted output signal of the second-stage flip-flop 35, and the AND gate 40 is the second-stage flip-flop. The edge detection signal NEEG1 is generated from the 36 non-inverted output signals and the inverted output signal of the third flip-flop 37.
[0022]
The edge detection circuit 23 detects the up edge of the angle signal NE at the timing of the down edge of the clock CK0, and the second edge from the down edge of the first clock CK0 after the angle signal NE changes from the L level to the H level. During the period until the down edge, the edge detection signal NEEG0 operates so as to be at the H level. This edge detection signal NEEG0 is used to generate a preset signal PR described later. The edge detection circuit 23 operates so that the edge detection signal NEEG1 is set to the H level during the period from the second down edge to the third down edge of the clock CK0. The edge detection signal NEEG1 is used to reset the counters 26 and 27.
[0023]
As shown in FIG. 5, the two-phase circuit 25 (corresponding to the clock pulse generation means) includes a D flip-flop 41 for dividing the clock CLK input via the inverter 42 by two, and a non-flip of the flip-flop 41. The AND gate 43 generates the clock CK0 from the inverted output signal and the clock CLK, and the AND gate 44 generates the clock CK1 from the inverted output signal of the flip-flop 41 and the clock CLK. The non-inverted output signal of the flip-flop 41 is the select signal SEL.
[0024]
The generated clock CK0 is supplied to the counter 26, and the clock CK1 is supplied to the counter 27. Since these clocks CK0 and CK1 have a frequency half that of the clock CLK and are two-phased so that there is no overlap period, the operations of the counters 26 and 27 are multiplexed by time division as will be described later. It becomes possible.
[0025]
The counter 26 (corresponding to the first counting means) and the counter 27 (corresponding to the second counting means) have individual holding circuits 45 and 46 (corresponding to the holding means), respectively, and other circuit portions. The increment circuit 47 is a common configuration. The increment circuit 47 (corresponding to the increment means) includes a common data bus 48, an incrementer 49, a selector 50, and an OR gate 51 interposed in the common data bus 48.
[0026]
The select signal SEL and the inverted select signal INVSEL are input to the chip select terminals CS of the holding circuits 45 and 46, respectively, so that the holding circuits 45 and 46 do not output data to the common data bus 48 at the same time. It has become. In the present embodiment, since the number N of constituent bits of the holding circuit 45 is larger than the number of constituent bits M (= 3) of the holding circuit 46, the bus width of the common data bus 48 is N bits.
[0027]
As shown in FIGS. 8 and 9, the holding circuits 45 and 46 have the same configuration except that the number of bits is N and M, respectively. Referring to FIG. 8 as an example, D flip-flops 52 (0) to 52 (N-1) are provided corresponding to the respective bits D0 to DN-1 of the input data, and their clock input terminals CK are provided at their clock input terminals CK. Is supplied with a clock CK0 via a buffer 54.
[0028]
The inverted output signals of the flip-flops 52 (0) to 52 (N-1) are passed through clocked inverters 53 (0) to 53 (N-1), and then output data Q0 to Q (N-1). The clocked inverters 53 (0) to 53 (N-1) are supplied with a select signal SEL via inverters 55 and 56. Similarly, the holding circuit 46 shown in FIG. 9 includes D flip-flops 57 (0) to 57 (M-1), clocked inverters 58 (0) to 58 (M-1), a buffer 59, and inverters 60 and 61. It is configured.
[0029]
When the selection signal supplied from the OR gate 51 is L level (0), the selector 50 (corresponding to the selection means) selects the output data of the incrementer 49 and applies it to the holding circuits 45 and 46, and the selection control signal is H. In the case of level (1), data of all 0 bits is selected and given to the holding circuits 45 and 46. The edge detection signal NEEG1 and the reset signal RST are input to the OR gate 51. The data of the holding circuits 45 and 46 is reset by the edge detection signal NEEG1, and the data of the holding circuit 46 is reset by the reset signal RST. .
[0030]
As shown in FIG. 6B, the incrementer 49 outputs data obtained by adding 1 to the input data. As shown in FIG. 6 (a), the incrementer 49 has a circuit configuration in which addition circuits 62 (0) to 62 (N-1) are provided corresponding to the bits D0 to DN-1 of the input data. It has become.
[0031]
The decode circuit 28 (corresponding to the decode means) is enabled from the decoder 63 that decodes the output data of the holding circuit 46 (count value of the counter 27), the output signal X of the decoder 63, and the select signal INVSEL output from the inverter 66. An AND gate 64 that generates the signal EN, and an AND gate 65 that generates the reset signal RST from the output signal Y of the decoder 63 and the select signal INVSEL. The gate controlled using the select signal INVSEL is the bus connected to the input terminal of the decoder 63 is the common data bus 48 of the counters 26 and 27 that perform time-division operation, and not only the output data of the holding circuit 46. This is because the output data of the holding circuit 45 is also input.
[0032]
The decoder 63 includes inverters 67 to 69, a NAND gate 70, and an AND gate 71 as shown in FIG. As shown in FIG. 7B, the decoder 63 corresponds to a signal X that becomes H level corresponding to 1 and 3 among the count values 0 to 4 of the quinary counter 27, and the count value 4. The signal Y which becomes H level is output. When this decoder 63 is used, the enable signal EN (corresponding to the enable pulse) is generated at a rate of 2 (m) in 5 cycles (n) of the clock CK0 for counting up the counter 26. The tooth determination value K is n / = 5/2 = 2.5.
[0033]
The counter 29 (corresponding to the third counting means) presets the count value that the counter 26 has up-counted over one period of the angle signal NE by the preset signal PR, and when the enable signal EN is given, the counter 29 is synchronized with the clock CLK. It is an N-bit down counter for counting. When the rotation sensor 33 detects the missing tooth portion 32b (reference position) of the rotor 32, the counter 29 outputs a borrow signal BO.
[0034]
As shown in FIG. 10, the counter 29 includes a holding circuit 72, a decrementer 73, selectors 74 and 75, and a data bus 76. The holding circuit 72 is provided with D flip-flops 77 (B) and 77 (0) to 77 (N-1) corresponding to the bits of the data DB and D0 to DN-1, and these clock input terminals A clock CLK is supplied to CK via a buffer 78. Output data QB and Q0 to QN-1 of the flip-flops 77 (B) and 77 (0) to 77 (N-1) are input to the selector 74 and the decrementer 73 via the data bus 76, and the flip-flop 77 ( The output data of B) is input to the selector 74.
[0035]
When the enable signal EN is at L level (0), the selector 74 selects and outputs the output data QB, Q0 to QN-1 of the flip-flops 77 (B) and 77 (0) to 77 (N-1). When the enable signal EN is at the H level (1), the output data DB, D0 to DN-1 of the decrementer 73 is selected and output. The selector 75 selects the output data of the selector 74 when the preset signal PR is at the L level, and selects the data DB that is 0 and the count value of the counter 26 when the preset signal PR is at the H level. The data DBs D0 to DN-1 are given to the flip-flops 77 (B) and 77 (0) to 77 (N-1).
[0036]
As shown in FIG. 11B, the decrementer 73 outputs data obtained by subtracting 1 from the input data. As shown in FIG. 11A, the decrementer 73 includes subtraction circuits 79 (0) to 79 (N-1) corresponding to the bits Q0 to QN-1 of the input data, and further includes a borrow data DB. Is provided with a subtracting circuit 79 (B).
[0037]
Next, the operation of the rotational position detection device 21 will be described with reference to the timing charts shown in FIGS.
FIG. 2 shows changes in the count values of the counters 26 and 29 with respect to the angle signal NE. FIG. 3 shows the change timing of the clock, signal, and count value. In FIG. 3, the angle signal NE, the clock CLK, the select signal SEL, the clock CK0, the clock CK1, the edge detection signal NEEG0, the edge detection signal NEEG1, the count value of the counter 26, the reset signal RST, and the count value of the counter 27 are sequentially shown from the top. The preset signal PR, the enable signal EN, and the count value of the counter 29 are shown.
[0038]
The main clocks used in this rotational position detection device 21 are the two-phase clocks CK0 and CK1 generated by the two-phase circuit 25. The clock CK0 is used for up-counting the counter 26, and the clock CK1 is the counter 27. Used for up-counting. In accordance with this, the holding circuit 45 of the counter 26 is chip-selected by the select signal SEL corresponding to the clock CK0, and the holding circuit 46 of the counter 27 is chip-selected by the select signal INVSEL corresponding to the clock CK1.
[0039]
When the rotor 32 rotates with the rotation of the crankshaft or the camshaft 31 of the internal combustion engine, the rotation sensor 33 attached in the vicinity of the rotor 32 changes according to the teeth 32a provided on the outer periphery of the rotor 32. A signal is generated. This signal is converted into a rectangular wave-shaped angle signal NE by the waveform shaping circuit 34. When an up edge appears in the angle signal NE, the edge detection signal NEEG0 first becomes H level, and the edge detection signal NEEG0 and the select signal SEL are supplied to the counter 29 as a preset signal PR by the AND gate 30. The counter 29 inputs and presets the count value (a or 3a shown in FIG. 2) from the holding circuit 45 that is chip-selected by the select signal SEL via the data bus 80.
[0040]
When the edge detection signal NEEG0 returns to the L level, the edge detection signal NEEG1 is now at the H level. Since the edge detection signal NEEG1 is kept at the H level during the period when the up edges are generated in the clocks CK0 and CK1, the selector 50 continues to select the data of all bits 0 and the holding circuits 45 and 46 are reset. When the edge detection signal NEEG1 returns to the L level, the counter 26 starts to count up the clock CK0 again during the period until the edge detection signal NEEG1 next becomes the H level.
[0041]
On the other hand, the quinary counter 27 is also reset by a reset signal RST in addition to the edge detection signal NEEG1. Since the reset signal RST is gated by the select signal INVSEL in the AND gate 65, the counter 26 that is chip-selected by the select signal SEL is not reset.
[0042]
Since the counters 26 and 27 operate complementarily by the select signals SEL and INVSEL, even if the common data bus 48, the incrementer 49, the selector 50, etc. are shared, they do not affect each other.
[0043]
The counter 29 preset with the count value of the counter 26 counts down in synchronization with the up edge of the clock CLK while the enable signal EN is at the H level. Since the enable signal EN becomes H level corresponding to 1 and 3 among the count values 0 to 4 of the counter 27 (see FIG. 7B), the down count ratio (count value change rate) by the counter 29 Is 1 / K = 1 / 2.5 of the ratio of up-counting by the counter 26 (count value change rate). This missing tooth determination value K is obtained by n / m from the radix n (= 5) of the counter 27 and the number m (= 2) of the enable signal EN.
[0044]
Therefore, the count value of the counter 26 and the count value of the counter 29 change as shown in FIG. That is, even if there is some rotational fluctuation, if the pitch T (j-1) of the teeth 32a other than the reference position appears continuously, the count value of the counter 29 does not decrease to zero. On the other hand, when the tooth pitch Tj (≈3 · T (j-1)) at the reference position (missing tooth portion 32b) appears, the preset signal PR is generated in the middle of the pitch T (j-1). Since it does not occur, the count value of the counter 29 decreases to 0, and an H level borrow signal BO is output. Accordingly, the reference position in the angle signal NE can be detected by outputting the H level borrow signal BO.
[0045]
As described above, according to the present embodiment, each cycle of the angle signal NE output from the angle signal generator 22 is measured by up-counting the clock CK0 using the counter 26, and the count value is counted by the counter. 29, the reference position (missing tooth portion 32b) can be detected as the borrow signal BO. The rotational position detection device 21 has a feature that the erroneous detection of the reference position is extremely small with respect to the variation in the signal period due to the shape accuracy of the rotor 32 and the rotational speed.
[0046]
The counter 29 uses the enable signal EN output from the decoding circuit 28 as a down-count permission pulse, and the decoding circuit 28 is given a quinary count value from the counter 27. In this embodiment, the clock CK0 supplied to the counter 26 and the clock CK1 supplied to the counter 27 are two-phased so that there is no overlap period. Then, the holding circuit 45 of the counter 26 is chip-selected by the select signal SEL corresponding to the clock CK0, and the holding circuit 46 of the counter 27 is chip-selected by the select signal INVSEL corresponding to the clock CK1. By multiplexing by this time division operation, the counters 26 and 27 can share the increment circuit 47 (common data bus 48, incrementer 49, selector 50) which is a circuit part other than the holding circuits 45 and 46.
[0047]
As a result, some of the data buses, incrementers, and selectors that have been required so far can be omitted, and the circuit scale can be reduced compared to the conventional configuration. In particular, when an IC is used, the chip area can be reduced. Cost can be reduced. Further, by appropriately setting the radix n of the counter 46 and the configuration of the decoder 63, the missing tooth determination value K (2.5 in this embodiment) including not only the integer part but also the decimal part can be set. The reference position can be detected by using the missing tooth determination value K that is optimal in accordance with the characteristics of the internal combustion engine.
[0048]
(Second Embodiment)
FIG. 12 shows a configuration and function table of a decoder used in the rotational position detection apparatus according to the second embodiment of the present invention. When this decoder 81 is used, it is necessary to use a decimal counter instead of the quinary counter 27. Other components are the same as those in the first embodiment.
[0049]
The decoder 81 includes inverters 82 and 83, a NAND gate 84, and an AND gate 85. The decoder 81 includes 1 out of 12 states (n = 12) from a count value 0 to 11 input from a decimal counter (not shown). A signal X which becomes H level corresponding to five states 3, 5, 7, 9 (m = 5) and a signal Y which becomes H level corresponding to the count value 11 are output. Accordingly, the missing tooth determination value K of the present embodiment is n / m = 12.5 / 5 = 2.4.
[0050]
(Other embodiments)
The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified or expanded as follows, for example.
Although the operations of the counters 26 and 27 are multiplexed by time division, the operations of the counters 26, 27 and 29 can be multiplexed by time division using a three-phase clock. As a result, the circuit scale can be further reduced.
The rotational position detecting device 21 can be widely applied not only to an internal combustion engine but also to a rotating object.
The number of missing teeth of the missing tooth portion 32b in the rotor 32 is not limited to 2, and may be 3, 4,.
The decoder 63 outputs the signal X which becomes the H level corresponding to 1 and 3 among the count values 0 to 4 of the quinary counter 27. However, the decoder 63 outputs corresponding to other combinations such as 2 and 3, for example. It may be.
[Brief description of the drawings]
FIG. 1 is an overall electrical configuration diagram of a rotational position detection device showing a first embodiment of the present invention;
FIG. 2 is a timing chart showing changes in the count value of the counter with respect to the angle signal NE
FIG. 3 is a timing chart showing changes in clock, signal, and count value.
FIG. 4 is an electrical configuration diagram of an edge detection circuit.
FIG. 5 is an electrical configuration diagram of a two-phase circuit.
FIG. 6 is an electrical configuration diagram (a) and a functional diagram (b) of an incrementer.
7 is an electrical configuration diagram (a) and a functional diagram (b) of a decoder. FIG.
FIG. 8 is an electrical configuration diagram of the holding circuit 45;
9 is an electrical configuration diagram of the holding circuit 46. FIG.
FIG. 10 is an electrical configuration diagram of the counter 29.
FIG. 11 is an electrical configuration diagram (a) and a functional diagram (b) of a decrementer.
FIG. 12 is a view corresponding to FIG. 7 showing a second embodiment of the present invention.
FIG. 13 is a view corresponding to FIG.
FIG. 14 is a diagram corresponding to FIG.
[Explanation of symbols]
Reference numeral 21 denotes a rotational position detector, 22 an angle signal generator (angle signal generator), 25 a two-phase circuit (clock pulse generator), 26 a counter (first count means), and 27 a counter (second counter). Counting means), 28 is a decoding circuit (decoding means), 45 and 46 are holding circuits (holding means), 47 is an incrementing circuit (incrementing means), 48 is a common data bus (data bus), and 50 is a selector (selecting means). ).

Claims (4)

Generation of an angle signal that generates an angle signal that is generated in synchronization with the rotation of the object and has a constant period under constant speed rotation, and the part corresponding to the reference position of the object has an unequal period Means,
Clock pulse generating means for generating first and second clock pulses that are two-phased so that there is no overlapping period;
First counting means that is selected corresponding to the first clock pulse and measures each period of the angle signal by up-counting the first clock pulse;
Second counting means selected corresponding to the second clock pulse and constituting an n-ary counter by counting the second clock pulse;
Decoding means for decoding an n-ary count value output from the second counting means and generating a permission pulse corresponding to m count values of the n count values;
A third counting means for detecting an unequal period in the angle signal by down-counting the count value measured by the first counting means in correspondence with the permission pulse;
Each of the first counting means and the second counting means includes holding means for holding a count value, and also includes common increment means for incrementing the count value to be a new input value to the holding means. A rotational position detecting device. The increment means includes
With a common incrementer,
A common data bus for inputting count values of the holding means of the first and second counting means to the holding means via the incrementer;
Interposed the data bus, to the respective holding means, that instead of the count value to the increment value through the incrementer is composed of a common selection means for providing a predetermined reset value The rotational position detection device according to claim 1, wherein:   For the holding means of the first counting means, the selection means selects a reset value by a reset signal corresponding to a predetermined edge of the angle signal, and for the holding means of the second counting means 3. The rotational position detection device according to claim 2, wherein a reset value is selected by a reset signal generated every radix n in the decoding means. 4. The rotational position detection device according to claim 1 , wherein the angle signal generating means generates an angle signal synchronized with the rotation of the internal combustion engine .

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