JP2004257814A - Rotational position sensing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a rotational position sensing device having a reduced circuit scale. <P>SOLUTION: Each period of an angle signal NE is measured by up-counting a clock CK0 by using a counter 26, and the count value is down-counted at the rate of 1/K of up-counting by using a counter 29, to thereby detect a standard position (chipped tooth part 32b) as a borrow signal BO. In the counter 29, an enable signal EN from a decode circuit 28 is used as a permission pulse of down-counting, and a quinary count value is imparted from a counter 27 to the decode circuit 28. The clock CK0 imparted to the counter 26 and a clock CK1 imparted to the counter 27 are adjusted respectively to have two-phase property without generating an overlapped period by a two-phase imparting circuit 25, and an increment circuit 47 is used in common by multiplexing the counters 26, 27 by time-sharing operation. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a rotation position detection device that detects a reference position based on an angle signal including an irregular period generated in synchronization with the rotation of an object.
[0002]
[Prior art]
Patent Documents 1 to 3 disclose such a rotational position detecting device. Among these, the rotational position detecting devices for internal combustion engines described in Patent Documents 1 and 2 detect a reference position based on a comparison between a ratio of a cycle of adjacent pulses in a pulse train of an angle signal and a predetermined determination value K. And an up / down counter and an f / K frequency dividing circuit (see FIG. 13). Here, the f / K frequency divider circuit is configured to generate a down clock by combining a １ ／ frequency-divided clock and a 分 frequency-divided clock.
[0003]
This rotation position detection device measures the period of the pulse train by counting up a predetermined clock, and counts down the down clock from the number of clocks to detect the reference position when a borrow occurs. According to this configuration, the determination value K including a decimal point can be set even when a clock having a relatively low frequency is used.
[0004]
On the other hand, the circuit for a toothed tooth sensor described in Patent Document 3 is configured using only an up-counter without using an up-down counter in order to simplify the circuit.
[0005]
[Patent Document 1]
JP-A-5-66105
[0006]
[Patent Document 2]
JP-A-5-71909
[0007]
[Patent Document 3]
JP-A-5-93603
[0008]
[Problems to be solved by the invention]
FIG. 13 shows a configuration example of a rotational position detecting device similar to that of Patent Document 2, and FIG. 14 shows operation waveforms thereof. In the rotational position detecting device 1, the angle signal NE output from the rotational sensor 2 via the waveform shaping circuit 3 is frequency-divided by a frequency dividing circuit 4 into two, and the two up / down counters 5, 6 Up-counting and down-counting are alternately repeated for each cycle of the signal. The up / down counters 5 and 6 have the counting directions (up / down) opposite to each other, count up with the clock CLK from the clock generation circuit 7, and count down with the frequency-divided clock from the 1 / K frequency dividing circuit 8. . The supply of the clock to the up / down counters 5 and 6 is controlled by the selectors 9 and 10. When the edge detection circuits 11 and 12 detect the up edge of the angle signal NE, the up / down counters 5 and 6 are reset. According to the above configuration, when the rotation sensor 2 detects a missing tooth portion as a reference position, one of the up / down counters 5 and 6 outputs a borrow signal BO.
[0009]
However, since the rotational position detecting device 1 includes the two up / down counters 5 and 6 and the 1 / K frequency dividing circuit 8, the circuit scale becomes large and the chip area increases when the IC is used, resulting in cost reduction. There is a problem of becoming high.
[0010]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a rotational position detecting device capable of reducing a circuit scale as compared with a conventional configuration.
[0011]
[Means for Solving the Problems]
According to the first aspect of the present invention, the clock pulse generating means generates the first and second clock pulses that are two-phased so that there is no overlap period. Then, by selecting the first counting means and the second counting means in accordance with the first clock pulse and the second clock pulse, respectively, a multiplexed operation becomes possible. That is, the first counting means measures each cycle of the angle signal output from the angle signal generating means by counting up the first clock pulse, and the second counting means performs the counting in parallel with this. By counting the two clock pulses, an n-ary counter value is obtained.
[0012]
The decoding means decodes the n-ary count value, and generates a permission pulse corresponding to the m count values of the n count values. The third counting means counts down the count value measured by the first counting means in response to the permission pulse in the same phase as the operation of the second counting means, thereby determining whether or not a borrow has occurred. Unequal period (reference position) in the angle signal can be detected based on
[0013]
Such multiplexing is performed when the operation of the first counting means for up-counting and the operation of the third counting means for down-counting need to proceed simultaneously with the periodic angle signal, that is, the down-counting is performed. When it is necessary to operate the second counting means for generating the necessary permission pulse in parallel with the first counting means, the second counting means is an effective means for eliminating redundant components.
[0014]
In the present invention, since the operations of the first counting means and the second counting means are multiplexed by time division, the components which are not used at the same time, that is, the count value of the holding means of each counting means is incremented and a new one is obtained. Increment means for input values can be shared. As a result, a part of the increment means conventionally required for each counting means can be omitted, and the circuit scale can be reduced as compared with the conventional configuration.
[0015]
According to the means described in claim 2, the increment means includes a common incrementer, a common data bus for returning the count value of each holding means to the input side of each holding means via the incrementer, and a common data bus. And a common selecting means interposed on the bus for giving a predetermined reset value to each holding means in place of the count value. According to this configuration, the first and second counting units can share the incrementer, the data bus, and the selecting unit.
[0016]
According to the means described in claim 3, by using the common selection means, the holding means of the first counting means is reset in response to a predetermined edge of the angle signal, and the second counting means is reset. The holding means of the counting means can be reset every radix n.
[0017]
According to the means described in claim 4, the ratio n / m of the radix n of the count value of the second counting means to the number m of the permission pulses is appropriately set, so that not only the integer part but also the decimal part is included. Based on the determination value K, it is possible to compare the equal period and the irregular period of the angle signal.
[0018]
According to the means described in claim 5, it is possible to accurately detect the crank angle of the internal combustion engine and the like.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
Hereinafter, a first embodiment of a rotational position detecting device for detecting a crank angle of an internal combustion engine will be described with reference to FIGS.
FIG. 1 shows the overall electrical configuration of the rotational position detecting device. The rotational position detecting device 21 includes an angle signal generating unit 22 that outputs an angle signal NE, an edge detecting circuit 23 that detects an up edge of the angle signal NE, a clock generating circuit 24 that outputs a synchronized clock CLK of the entire system, and a clock. A two-phase circuit 25 that generates clocks CK0 and CK1 obtained by two-phase CLK, a counter 26 that counts up the clock CK0 and measures each cycle of the angle signal NE, and an n-ary that counts up the clock CK1 (this embodiment Quinary) The counter 27, a decode circuit 28 that decodes the count value of the counter 27 and outputs an enable signal EN and a reset signal RST, and uses the enable signal EN as an enable pulse to lower the count value of the counter 26 in synchronization with the clock CLK. Counter 29 for counting and preset signal generation times And a AND gate 30 is.
[0020]
Hereinafter, a specific configuration of each component will be described. The specific waveform and generation timing of each signal are shown in the timing chart shown in FIG.
The angle signal generator 22 (corresponding to an angle signal generator) outputs a signal corresponding to the rotational position of the crankshaft or camshaft 31 (corresponding to an object) of the internal combustion engine. In the outer peripheral portion of the rotor 32 attached to the crankshaft or the camshaft 31, for example, of the 36 teeth 32a provided at equal intervals at 10 ° CA, two teeth are missing at a reference position. A portion 32b is formed. A rotation sensor 33 composed of an electromagnetic pickup, a Hall sensor, an optical sensor, and the like is provided at a position facing the teeth 32 a on the outer peripheral portion of the rotor 32, and an output signal of the rotation sensor 33 is a waveform shaping circuit 34. , Is shaped into a rectangular wave and becomes an angle signal NE.
[0021]
As shown in FIG. 4, the edge detection circuit 23 includes three cascade-connected D flip-flops 35, 36, and 37. The clock input terminal CK receives a clock CK0 via an inverter 38. It is supposed to be. The AND gate 39 generates an edge detection signal NEEG0 from the non-inverted output signal of the first-stage flip-flop 35 and the inverted output signal of the second-stage flip-flop 35, and the AND gate 40 generates the edge-detected signal NEEG0. The edge detection signal NEEG1 is generated from the non-inverted output signal 36 and the inverted output signal of the flip-flop 37 at the third stage.
[0022]
The edge detection circuit 23 detects the rising edge of the angle signal NE at the timing of the falling edge of the clock CK0, and detects the second rising edge of the first clock CK0 after the angle signal NE changes from the L level to the H level. During the period until the down edge, the operation is performed so that the edge detection signal NEEG0 is set to the H level. The edge detection signal NEEG0 is used to generate a preset signal PR described later. Further, the edge detection circuit 23 operates so that the edge detection signal NEEG1 is set to the H level during a period from the second down edge to the third down edge of the clock CK0. The edge detection signal NEEG1 is used to reset the counters 26 and 27.
[0023]
As shown in FIG. 5, the two-phase circuit 25 (corresponding to a clock pulse generating means) includes a D flip-flop 41 for dividing the frequency of the clock CLK input through the inverter 42 by two, and a non-operation of the flip-flop 41. It comprises an AND gate 43 for generating a clock CK0 from the inverted output signal and the clock CLK, and an AND gate 44 for generating a clock CK1 from the inverted output signal of the flip-flop 41 and the clock CLK. The non-inverted output signal of the flip-flop 41 is the select signal SEL.
[0024]
The generated clock CK0 is provided to the counter 26, and the clock CK1 is provided to the counter 27. Since these clocks CK0 and CK1 have a frequency of 1/2 of the clock CLK and are two-phased so that there is no overlapping period, the operations of the counters 26 and 27 are multiplexed by time division as described later. It becomes possible.
[0025]
The counter 26 (corresponding to the first counting means) and the counter 27 (corresponding to the second counting means) have separate holding circuits 45 and 46 (corresponding to the holding means), respectively. Are common to the increment circuit 47. The increment circuit 47 (corresponding to an increment means) includes a common data bus 48, an incrementer 49 and a selector 50 interposed on the common data bus 48, and an OR gate 51.
[0026]
The select signal SEL and its inverted select signal INVSEL are input to the chip select terminals CS of the holding circuits 45 and 46, respectively, so that the holding circuits 45 and 46 do not simultaneously output data to the common data bus 48. It has become. In the present embodiment, since the number N of configuration bits of the holding circuit 45 is larger than the number M of configuration bits of the holding circuit 46 (= 3), the bus width of the common data bus 48 is N bits.
[0027]
The holding circuits 45 and 46 have the same configuration as shown in FIGS. 8 and 9 except that the number of bits is N and M, respectively. Referring to FIG. 8 as an example, D flip-flops 52 (0) to 52 (N-1) are provided corresponding to each bit of D0 to DN-1 of the input data, and their clock input terminals CK are provided. Are supplied with a clock CK0 via a buffer 54.
[0028]
The inverted output signals of the flip-flops 52 (0) to 52 (N-1) are output as data Q0 to Q (N-1) after passing through clocked inverters 53 (0) to 53 (N-1). The select signals SEL are supplied to the clocked inverters 53 (0) to 53 (N-1) via inverters 55 and 56. Similarly, the holding circuit 46 shown in FIG. 9 includes D flip-flops 57 (0) to 57 (M-1), clocked inverters 58 (0) to 58 (M-1), a buffer 59 and inverters 60 and 61. It is configured.
[0029]
When the selection signal supplied from the OR gate 51 is at L level (0), the selector 50 selects the output data of the incrementer 49 and supplies it to the holding circuits 45 and 46, and the selection control signal is H. In the case of level (1), data of all bits 0 is selected and supplied to the holding circuits 45 and 46. The edge detection signal NEEG1 and the reset signal RST are input to the OR gate 51, the data of the holding circuits 45 and 46 are reset by the edge detection signal NEEG1, and the data of the holding circuit 46 are reset by the reset signal RST. .
[0030]
The incrementer 49 outputs data obtained by adding 1 to the input data as shown in FIG. 6B. As shown in FIG. 6A, the incrementer 49 has a circuit configuration in which adders 62 (0) to 62 (N-1) are provided corresponding to the respective bits D0 to DN-1 of the input data. Has become.
[0031]
A decoding circuit 28 (corresponding to a decoding means) is enabled by a decoder 63 for decoding output data (count value of the counter 27) of the holding circuit 46, an output signal X of the decoder 63 and a select signal INVSEL output from the inverter 66. It comprises an AND gate 64 for generating a signal EN, and an AND gate 65 for generating a reset signal RST from the output signal Y of the decoder 63 and the select signal INVSEL. The gate controlled by using the select signal INVSEL is that the bus connected to the input terminal of the decoder 63 is the common data bus 48 of the counters 26 and 27 that operate in a time-division manner. This is because the output data of the holding circuit 45 is also input.
[0032]
The decoder 63 includes inverters 67 to 69, a NAND gate 70 and an AND gate 71, as shown in FIG. As shown in FIG. 7 (b), the decoder 63 outputs a signal X which goes to an H level corresponding to 1 and 3 of the count values 0 to 4 of the quinary counter 27, and a signal X corresponding to the count value 4. And outputs a signal Y which is at H level. When this decoder 63 is used, the enable signal EN (corresponding to an enable pulse) is generated twice (m) twice in every five cycles (n) of the clock CK0 for counting up the counter 26. The tooth determination value K is n / = 5/2 = 2.5.
[0033]
The counter 29 (corresponding to a third counting means) presets a count value, which is counted up by the counter 26 over one cycle of the angle signal NE, by a preset signal PR, and when an enable signal EN is supplied, the counter 29 decreases in synchronization with the clock CLK. This is an N-bit down counter for counting. When the rotation sensor 33 detects the missing tooth portion 32b (reference position) of the rotor 32, the counter 29 outputs a borrow signal BO.
[0034]
The counter 29 includes a holding circuit 72, a decrementer 73, selectors 74 and 75, and a data bus 76, as shown in FIG. The holding circuit 72 is provided with D flip-flops 77 (B), 77 (0) to 77 (N-1) corresponding to each bit of the data DB and D0 to DN-1, and these clock input terminals. CK is supplied with a clock CLK via a buffer 78. The output data QB, Q0 to QN-1 of the flip-flops 77 (B), 77 (0) to 77 (N-1) are input to the selector 74 and the decrementer 73 via the data bus 76, and The output data of B) is input to the selector 74.
[0035]
When the enable signal EN is at L level (0), the selector 74 selects and outputs the output data QB, Q0 to QN-1 of the flip-flops 77 (B), 77 (0) to 77 (N-1). When the enable signal EN is at H level (1), the output data DB, D0 to DN-1 of the decrementer 73 are selected and output. The selector 75 selects the output data of the selector 74 when the preset signal PR is at the L level, and selects the data DB of 0 and the count value of the counter 26 when the preset signal PR is at the H level. Data DB, D0 to DN-1 are supplied to flip-flops 77 (B), 77 (0) to 77 (N-1).
[0036]
The decrementer 73 outputs data obtained by subtracting 1 from the input data as shown in FIG. As shown in FIG. 11A, the decrementer 73 includes subtraction circuits 79 (0) to 79 (N-1) corresponding to the respective bits Q0 to QN-1 of the input data. Is provided with a subtraction circuit 79 (B) for obtaining.
[0037]
Next, the operation of the rotational position detecting device 21 will be described with reference to timing charts shown in FIGS.
FIG. 2 shows a change in the count value of the counters 26 and 29 with respect to the angle signal NE. FIG. 3 shows a change timing of a clock, a signal, and a count value. FIG. 3 shows an angle signal NE, a clock CLK, a select signal SEL, a clock CK0, a clock CK1, an edge detection signal NEEG0, an edge detection signal NEEG1, a count value of the counter 26, a reset signal RST, and a count value of the counter 27 in order from the top. , The preset signal PR, the enable signal EN, and the count value of the counter 29.
[0038]
The main clocks used in the rotational position detecting device 21 are the two-phase clocks CK0 and CK1 generated by the two-phase circuit 25. The clock CK0 is used for counting up the counter 26, and the clock CK1 is used for the counter 27. Is used for counting up. At the same time, the holding circuit 45 of the counter 26 is chip-selected by the select signal SEL corresponding to the clock CK0, and the holding circuit 46 of the counter 27 is chip-selected by the select signal INVSEL corresponding to the clock CK1.
[0039]
When the rotor 32 rotates with the rotation of the crankshaft or the camshaft 31 of the internal combustion engine, the rotation sensor 33 attached near the rotor 32 changes according to the teeth 32 a provided on the outer peripheral portion of the rotor 32. A signal is generated. This signal is converted into a rectangular wave angle signal NE by the waveform shaping circuit 34. When an up edge appears in the angle signal NE, the edge detection signal NEEG0 goes high first, and the edge detection signal NEEG0 and the select signal SEL are provided to the counter 29 as the preset signal PR by the AND gate 30. The counter 29 inputs the count value (a or 3a shown in FIG. 2) via the data bus 80 from the holding circuit 45 which has been chip-selected by the select signal SEL, and presets it.
[0040]
When the edge detection signal NEEG0 returns to the L level, the edge detection signal NEEG1 goes to the H level this time. Since the edge detection signal NEEG1 keeps the H level while the clocks CK0 and CK1 each have an up-edge, the selector 50 continues to select data of all the bits 0 and the holding circuits 45 and 46 are reset during that time. When the edge detection signal NEEG1 returns to the L level, the counter 26 starts counting up the clock CK0 again until the edge detection signal NEEG1 next goes to the H level.
[0041]
On the other hand, the quinary counter 27 is reset by a reset signal RST in addition to the edge detection signal NEEG1. Since the reset signal RST is gated by the select signal INVSEL in the AND gate 65, the counter 26 that is chip-selected by the select signal SEL is not reset.
[0042]
Since the counters 26 and 27 operate complementarily by the select signals SEL and INVSEL, they do not affect each other even if the common data bus 48, the incrementer 49, the selector 50, and the like are shared.
[0043]
Now, the counter 29 in which the count value of the counter 26 is preset counts down in synchronization with the rising edge of the clock CLK while the enable signal EN is at the H level. Since the enable signal EN is at the H level corresponding to 1 and 3 of the count values 0 to 4 of the counter 27 (see FIG. 7B), the rate of down-counting by the counter 29 (the rate of change of the count value) Is 1 / K = 1 / 2.5 of the rate of up-counting by the counter 26 (the rate of change of the count value). The missing tooth determination value K is obtained as n / m from the radix n (= 5) of the counter 27 and the number m (= 2) of the enable signal EN.
[0044]
Therefore, the count value of the counter 26 and the count value of the counter 29 change as shown in FIG. That is, even if there is some rotation fluctuation, if the pitch T (j-1) of the teeth 32a other than the reference position appears continuously, the count value of the counter 29 does not decrease to zero. On the other hand, when the pitch Tj (≒ 3 · T (j−1)) of the tooth at the reference position (the missing tooth portion 32b) appears, the preset signal PR is generated in the middle of the pitch T (j−1). Since this does not occur, the count value of the counter 29 decreases to 0, and the H-level borrow signal BO is output. Therefore, the reference position in the angle signal NE can be detected by outputting the H-level borrow signal BO.
[0045]
As described above, according to the present embodiment, each cycle of the angle signal NE output from the angle signal generator 22 is measured by counting up the clock CK0 using the counter 26, and the count value is counted by the counter 26. The reference position (the missing tooth portion 32b) can be detected as the borrow signal BO by counting down at a rate of 1 / K of the above-described up-counting using the number 29. This rotation position detection device 21 has a feature that erroneous detection of the reference position is extremely small with respect to variations in the signal period due to the shape accuracy of the rotor 32 and the number of rotations.
[0046]
The counter 29 uses the enable signal EN output from the decoding circuit 28 as a down-counting permission pulse, and the decoding circuit 28 is supplied with a quinary count value from the counter 27. In the present embodiment, the clock CK0 applied to the counter 26 and the clock CK1 applied to the counter 27 are two-phased so that there is no overlap period. The holding circuit 45 of the counter 26 is chip-selected by the select signal SEL corresponding to the clock CK0, and the holding circuit 46 of the counter 27 is chip-selected by the select signal INVSEL corresponding to the clock CK1. The multiplexing by the time division operation enables the counters 26 and 27 to share the increment circuit 47 (common data bus 48, incrementer 49, and selector 50) which is a circuit part other than the holding circuits 45 and 46.
[0047]
As a result, a part of the data bus, the incrementer, and the selector which have been required so far can be omitted, and the circuit scale can be reduced as compared with the conventional configuration. In particular, when the IC is used, the chip area can be reduced. Costs can be reduced. Further, by appropriately setting the radix n of the counter 46 and the configuration of the decoder 63, the missing tooth determination value K (2.5 in the present embodiment) including not only the integer part but also the decimal part can be set. The reference position can be detected by using the optimum missing tooth determination value K in accordance with the characteristics of the internal combustion engine.
[0048]
(Second embodiment)
FIG. 12 shows a configuration and a function table of a decoder used in the rotational position detection device according to the second embodiment of the present invention. When this decoder 81 is used, it is necessary to use a decimal counter instead of the quinary counter 27. Other components are the same as in the first embodiment.
[0049]
The decoder 81 includes inverters 82 and 83, a NAND gate 84, and an AND gate 85. One of 12 states (n = 12) of count values 0 to 11 input from a decimal counter (not shown), A signal X that goes high in response to the five states 3, 5, 7, and 9 (m = 5) and a signal Y that goes high in response to the count value 11 are output. Therefore, the missing tooth determination value K in the present embodiment is n / m = 12/5 = 2.4.
[0050]
(Other embodiments)
The present invention is not limited to the embodiments described above and shown in the drawings. For example, the present invention can be modified or expanded as follows.
Although the operations of the counters 26 and 27 are multiplexed by time division, it is also possible to multiplex the operations of the counters 26, 27 and 29 by time division using a three-phase clock. As a result, the circuit scale can be further reduced.
The rotation position detection device 21 can be widely applied to not only internal combustion engines but also rotating objects.
The number of missing teeth of the missing tooth portion 32b in the rotor 32 is not limited to two and may be three, four,.
The decoder 63 outputs the signal X which becomes H level corresponding to 1 and 3 of the count values 0 to 4 of the quinary counter 27, but outputs the signal X corresponding to another combination such as 2 and 3. It may be.
[Brief description of the drawings]
FIG. 1 is an overall electrical configuration diagram of a rotation position detection device according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing a change in a count value of a counter with respect to an angle signal NE;
FIG. 3 is a timing chart showing changes in a clock, a signal, and a count value.
FIG. 4 is an electrical configuration diagram of an edge detection circuit.
FIG. 5 is an electrical configuration diagram of a two-phase circuit.
FIG. 6 is an electrical configuration diagram (a) and a functional diagram (b) of an incrementer.
FIG. 7A is an electrical configuration diagram of a decoder, and FIG.
FIG. 8 is an electrical configuration diagram of a holding circuit 45;
FIG. 9 is an electrical configuration diagram of a holding circuit 46;
FIG. 10 is an electrical configuration diagram of a counter 29;
FIG. 11 is an electrical configuration diagram (a) and a functional diagram (b) of a decrementer.
FIG. 12 is a view corresponding to FIG. 7, showing a second embodiment of the present invention;
FIG. 13 is a diagram corresponding to FIG. 1 showing a conventional technique.
FIG. 14 is a diagram corresponding to FIG. 2;
[Explanation of symbols]
21 is a rotation position detecting device, 22 is an angle signal generating section (angle signal generating means), 25 is a two-phase circuit (clock pulse generating means), 26 is a counter (first counting means), and 27 is a counter (second counting means). Counting means), 28 is a decoding circuit (decoding means), 45 and 46 are holding circuits (holding means), 47 is an increment circuit (incrementing means), 48 is a common data bus (data bus), and 50 is a selector (selecting means). ).

Claims (5)

An angle signal generation that generates an angle signal that is a pulse train generated in synchronization with the rotation of the object and has an equal period under a constant speed rotation, and a portion corresponding to a reference position of the object has an irregular period. Means,
Clock pulse generating means for generating first and second clock pulses that are two-phased so that there is no overlap period;
A first counting unit that is selected in response to the first clock pulse and measures each cycle of the angle signal by up-counting the first clock pulse;
Second counting means selected in response to the second clock pulse and configured to form an n-ary counter by counting the second clock pulse;
Decoding means for decoding an n-ary count value output from the second count means and generating a permission pulse corresponding to the m count values of the n count values;
A third counting means for detecting an unequal period in the angle signal by down-counting the count value measured by the first counting means in accordance with the permission pulse;
The first counting means and the second counting means each include a holding means for holding a count value, and a common increment means for incrementing the count value to be a new input value to the holding means. A rotational position detecting device. The increment means,
A common incrementer,
A common data bus for inputting the count value of each holding means of the first and second counting means to each holding means via the incrementer;
2. The rotational position detecting device according to claim 1, further comprising common selecting means interposed on said data bus and providing a predetermined reset value to said holding means in place of said count value. . The selecting means selects a reset value for the holding means of the first counting means by a reset signal corresponding to a predetermined edge of the angle signal, and selects a reset value for the holding means of the second counting means. 3. The rotational position detecting device according to claim 2, wherein said decoding means is configured to select a reset value by a reset signal generated for each radix n in said decoding means. The ratio n / m of the radix n of the count value of the second counting means to the number m of the permission pulses is used for detecting the unequal period based on a comparison between the equal period and the unequal period of the angle signal. The rotational position detecting device according to any one of claims 1 to 3, wherein the determination value K is set to a predetermined determination value K (K> 1). 5. The rotational position detecting device according to claim 1, wherein said angle signal generating means generates an angle signal synchronized with the rotation of the internal combustion engine.

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