JPH10321873A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure areas which are to become electrode parts by forming oxide films out the areas of gate electrode layers, growing a single crystal epitaxial Growth layer in an area except for the oxide films and a polycrystalline epitaxial layer on the oxide film and setting the poly-crystalline epitaxial growth layers to be conduction types similar to the gate electrode layers. SOLUTION: A prescribed dimension is left on a slit on the area which is to become the electrode parts of the P<+> gate electrode layers 4' of the SiO2 film. N-type polycrystalline epitaxial layers 6' are grown only on the P<+> gate electrode layers 4' with the existence of the SiO2 films 5" and an N-type single crystal epitaxial growth layer 6 is grown in an active area. P<+> -type diffiusion is executed on SiO2 film 7 as the mask of diffusion and the N-type polycrystalline epitaxial growth layers 6' are set to be P<+> gate electrode extraction layers 6". Thus, the parts which are to become the electrode parts of the P<+> gate electrode layers 4' are secured by the existence of the P<+> gate electrode extraction layers 6", and the disappearance of the P<+> gate electrode extration layers 4' and P<+> gate electrode extraction layers 6" themselves can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a static induction transistor having a buried gate structure.
The present invention relates to a method for manufacturing a semiconductor device in which a gate layer is buried inside a single crystal epitaxial growth layer, as represented by an nsistor (hereinafter referred to as SIT).

[0002]

2. Description of the Related Art Conventionally, in a method of manufacturing a semiconductor device of this type, a thermal oxide film SiO ₂ is formed on a first main surface of a semiconductor substrate of a first conductivity type, and then a stripe or mesh is formed by photolithography. The gate electrode layer is formed by making a selective opening of a second conductivity type and by diffusing impurities of a second conductivity type opposite to that of the semiconductor substrate. Further, a semiconductor single crystal layer of the same first conductivity type as that of the semiconductor substrate is formed on the semiconductor substrate by epitaxial growth to form a structure in which a gate electrode layer is embedded. Thereafter, a portion of the gate electrode layer is opened by a thermal oxidation process and a photolithography method, and only the opening is selectively etched at a depth substantially equal to the thickness of the semiconductor single crystal layer to form a gate electrode. The layer is taken out (exposing a predetermined region of the gate electrode layer).

FIGS. 3A to 3D and FIGS. 4A and 4B show a method of manufacturing an SIT having a buried gate structure as an example of a conventional method of manufacturing this type of semiconductor device. It is a schematic process drawing. Hereinafter, FIGS. 3 and 4
, A conventional method of manufacturing an SIT having a buried gate structure will be described.

In FIG. 3A, phosphorus or antimony is diffused at a high concentration from a second main surface (lower surface in the figure) of a silicon wafer to a surface impurity concentration of 10 ¹⁹ cm ⁻³ or more.
An N ⁺ diffusion layer (drain ohmic layer) 1 having a diffusion layer depth of 150 μm and an N ⁻ drain layer 2 are formed. In FIG. 3 (b), the silicon wafer of FIG. 3 (a) H ₂
Thermal oxidation is performed at 1100 ° C. for 15 minutes in an atmosphere containing O vapor to form a SiO ₂ film of about 3000 Å. Thereafter, a negative type photoresist having a viscosity of 40 cp is spin-coated at 4000 rpm for 20 seconds. Thereafter, exposure is performed using a mask-shaped dry plate in a stripe shape, and development is performed. Further, selective etching is performed with buffered hydrofluoric acid (BHF) to form a stripe-shaped SiO ₂ film 3 on the first main surface and an SiO ₂ film 3 ′ on the entire second main surface. In FIG. 3C, a normal open-tube liquid diffusion source is diffused using the SiO ₂ film 3 of FIG. 3B as a diffusion mask and BBr ₃ as an impurity source, and the P ⁺ gate layer 4 and P ⁺
A gate electrode layer 4 'is formed. Thereafter, the substrate is immersed in BHF to remove the SiO ₂ films 3 and 3 ′ of FIG. 3B. FIG.
In (d), epitaxial growth is performed at 1150 ° C. for 20 minutes using SiCl ₄ as a growth source and H ₂ as a carrier gas to grow an N-type single crystal epitaxial growth layer (source layer) 6. Through the above steps, the P ⁺ gate layer 4,
The P ⁺ gate electrode layer 4 ′ has a buried structure.

In FIG. 4A, a thermal oxidation treatment is performed on the silicon wafer of FIG. 3D in the same manner as in FIG. 3B to form an SiO ₂ film on the entire surface. Thereafter, the first main surface so as to selectively leave the photolithography technique to form the SiO ₂ film 7, the SiO ₂ film 7 to the second major surface over the entire surface '
To form In FIG. 4B, the silicon wafer of FIG. 4A is used as a mask for selective etching of the SiO ₂ film 7, and is a hydrofluoric acid, nitric acid, acetic acid-based silicon etching solution (HF: HNO ₃ : CH ₃ COOH). = 1: 5: 1 (vo
1 ratio)) to expose the buried P ⁺ gate electrode layer 4 ′ so as to excavate it. Thereafter, the substrate is immersed in BHF to remove the SiO ₂ films 7, 7 ′, thereby completing the basic structure of SIT.

[0006]

In the conventional method of manufacturing a semiconductor device, including the examples shown in FIGS. 3 and 4, the single crystal epitaxial growth layer has various thicknesses and the gate electrode layer is exposed. Due to the difficulty in controlling the amount of etching to perform the etching, an exposure defect often occurs in which the region of the gate electrode layer that is to be exposed and becomes an electrode portion cannot be accurately and reliably exposed.

FIGS. 5 (a) and 5 (b) are diagrams each showing an example of a defect relating to a gate electrode layer take-out structure in an SIT manufactured by a conventional manufacturing method. In FIG. 5A, in this SIT, the region of the P ⁺ gate electrode layer 4 ′ on the left side in the figure to be exposed and to become an electrode portion is still buried under the N-type single crystal epitaxial growth layer 6. . This is due to insufficient etching. Further, in FIG. 5A, most of the P ⁺ gate electrode layer 4 ′ on the left side in the figure has disappeared in this SIT. This is due to excessive etching.

In the conventional method of manufacturing a semiconductor device,
Since the concave portion is partially formed by the etching, the main surface has an uneven shape with a depth of more than ten microns. in this case,
Thick coating is required to complete the photoresist coverage in the photolithography process after etching. That is, it is necessary to repeat the same photolithography process a plurality of times, which is not rational. Further, since the photoresist is thick, it is difficult to form a fine pattern.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of rationally manufacturing a semiconductor device in which a region to be an electrode portion of a gate electrode layer is secured and the gate electrode layer itself is not lost. It is to be.

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a gate layer and a first region in which a gate electrode layer is to be embedded are embedded inside a single crystal epitaxial growth layer. Forming the gate layer and the gate electrode layer on top of a layer, and forming an oxide film having slit holes of a predetermined size and shape on a second region to be an electrode part of the gate electrode layer Growing the single crystal epitaxial growth layer on the region excluding the oxide film, and growing a polycrystalline epitaxial growth layer on the oxide film; and diffusing the polycrystalline epitaxial growth layer to form the gate electrode layer. And a step of forming the same conductivity type.

[0011]

1 (a) to 1 (c) and FIG.
(A)-(d) are SITs having a buried gate structure as a method of manufacturing a semiconductor device according to an embodiment of the present invention.
It is a schematic process drawing which shows the manufacturing method of. In these drawings, the same or similar parts as in the conventional example are denoted by the same reference numerals as in FIGS.

Hereinafter, the manufacturing method will be described with reference to FIGS.

In FIG. 1A, phosphorus or antimony is diffused at a high concentration from a second main surface (lower surface in the drawing) of a silicon wafer to a surface impurity concentration of 10 ¹⁹ cm ⁻³ or more.
An N ⁺ diffusion layer (drain ohmic layer) 1 having a diffusion layer depth of 150 μm and an N ⁻ drain layer 2 are formed. In FIG. 1 (b), the silicon wafer of FIG. 1 (a) H ₂
Thermal oxidation is performed at 1100 ° C. for 15 minutes in an atmosphere containing O vapor to form a SiO ₂ film of about 3000 Å. Thereafter, a negative type photoresist having a viscosity of 40 cp is spin-coated at 4000 rpm for 20 seconds. Thereafter, exposure is performed using a mask-shaped dry plate in a stripe shape, and development is performed. Further, selective etching is performed with buffered hydrofluoric acid (BHF) to form a stripe-shaped SiO ₂ film 3 on the first main surface and an SiO ₂ film 3 ′ on the entire second main surface. In FIG. 1 (c), a normal open-tube liquid diffusion source diffusion is performed using the SiO ₂ film 3 of FIG. 1 (b) as a diffusion mask and BBr ₃ as an impurity source to form a P ⁺ gate layer 4, P ⁺
A gate electrode layer 4 'is formed. Thereafter, the substrate is immersed in BHF to remove the SiO ₂ films 3 and 3 ′ of FIG. 1B. Also,
At the time of drive-in (push-in process) in an oxidizing atmosphere of P ⁺ selective diffusion, the first and second main surfaces respectively have S
The iO ₂ films 5 and 5 ′ are formed.

In FIG. 2A, the SiO 2 shown in FIG.
_{The two} films 5 are left in a slit shape having a predetermined size on a region of the P ⁺ gate electrode layer 4 ′ to be an electrode portion by the same photolithography method as that of FIG. 1B. The SiO ₂ film having the slit hole g having a predetermined width is referred to as an SiO ₂ film 5 ″.

In FIG. 2B, SiCl _{4 is} used as a growth source.
Is epitaxially grown at 1150 ° C. for 20 minutes using H ₂ as a carrier gas to grow an N-type polycrystalline epitaxial growth layer 6 ′ only on the P ⁺ gate electrode layer 4 ′ due to the presence of the SiO ₂ film 5 ″. In the other active region, an N-type single crystal epitaxial growth layer (source layer) 6
Grow. Through the above steps, the region where the P ⁺ gate layer 4 and the P ⁺ gate electrode layer 4 ′ are to be buried has a buried structure.

In FIG. 2C, the silicon wafer of FIG. 2B is subjected to a thermal oxidation treatment in the same manner as in FIG. 1B, and an SiO ₂ film is formed on the entire surface. Thereafter, the first main surface so as to selectively leave the photolithography technique to form the SiO ₂ film 7, the SiO ₂ film 7 to the second major surface over the entire surface '
To form

In FIG. 2D, the SiO ₂ film 7 is used as a diffusion mask, and BBr ₃ is used as an impurity source in the silicon wafer of FIG.
^{By performing +} type diffusion, an N type polycrystalline epitaxial growth layer 6 ′
The P ⁺ to be the P ⁺ gate electrode lead layer 6 ". This P ⁺
Since the type diffusion is diffusion to the polycrystalline epitaxial growth layer, the diffusion to the single crystal epitaxial growth layer is approximately 1%.
It is completed with a pressing time of / 3. Thereafter, the substrate is immersed in BHF to remove the SiO ₂ films 7 and 7 ′, thereby completing the basic structure of SIT.

[0018] In this completed SIT, with which is ensured by the presence of P ⁺ gate electrode lead layer 6 'which the electrode portion and the region that becomes the P ⁺ gate electrode layer 4' are continuous here, P ⁺ gate electrode layer The 4 'and P ⁺ gate electrode lead-out layers 6 "themselves have not disappeared.

The present invention is applicable not only to the SIT but also to the manufacture of all semiconductor devices in which a gate layer is embedded inside a single crystal epitaxial growth layer.

[0020]

According to the method of manufacturing a semiconductor device according to the present invention,
Forming a gate layer and a gate electrode layer on the semiconductor layer, and forming an oxide film having slit holes of a predetermined size and shape on a second region to be an electrode portion of the gate electrode layer; Growing a single-crystal epitaxial growth layer on the region excluding the oxide film and growing a polycrystalline epitaxial growth layer on the oxide film; and diffusing the polycrystalline epitaxial growth layer to have the same conductivity type as the gate electrode layer. Therefore, a region to be an electrode portion of the gate electrode layer is secured, and a semiconductor device in which the gate electrode layer itself has not disappeared can be rationally manufactured.

[Brief description of the drawings]

FIGS. 1A to 1C are schematic process diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 2A to 2D are schematic process diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 3A to 3D are schematic process diagrams illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIGS. 4A and 4B are schematic process diagrams showing a method for manufacturing a semiconductor device according to a conventional example.

FIGS. 5A and 5B are diagrams for explaining a problem caused by a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 N ⁺ diffusion layer 2 N ⁻ drain layer 3 SiO ₂ film 4 P ⁺ gate layer 4 ′ P ⁺ gate electrode layer 5, 5 ′, 5 ″ SiO ₂ film 6 N-type single crystal epitaxial growth layer 6 ′ N-type polycrystal epitaxial growth Layer 6 ″ P ⁺ gate electrode extraction layer 7, 7 ′ SiO ₂ film g Slit hole

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device in which a gate layer and a first region in which a gate electrode layer is to be buried are buried inside a single crystal epitaxial growth layer, wherein the gate layer and the gate are formed above a semiconductor layer. A step of forming an electrode layer, a step of forming an oxide film having slit holes of a predetermined size and shape on a second region to be an electrode part of the gate electrode layer, and a step of forming an oxide film on a region excluding the oxide film. A step of growing the single crystal epitaxial growth layer and growing a polycrystalline epitaxial growth layer on the oxide film; and a step of diffusing the polycrystal epitaxial growth layer to have the same conductivity type as the gate electrode layer. A method for manufacturing a semiconductor device, comprising: