JPH10321872A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To completely expose areas to be exposed in a gate electrode layer by forming oxide films whose etching ability is lower than a monocrystal epitaxial growth layer on a second area to be exposed in the gate electrode layer and growing a polycrystalline epitaxial growth layer whose etching ability is higher on the oxide film. SOLUTION: SiO2 films 5 and 5' are formed on the first and second main faces at the time of drive-in at the oxidized atmosphere of P<+> selection diffusion. The SiO2 film 5 is left only on P<+> gate electrode layers 4' and they are set to be the SiO2 films 5". SiCl4 is epitaxial-grown in a growth source, N-type polycrystalline epitaxial growth layers are grown on the P<+> gate electrode layers 4' and N-type mono-crystal epitaxial growth layers are grown in active areas. Thus, the areas to be exposed in the gate electrode layer are completely exposed and a semiconductor device where the gate electrode layer itself does not disappear can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a static induction transistor having a buried gate structure.
The present invention relates to a method for manufacturing a semiconductor device in which a gate layer is buried inside a single crystal epitaxial growth layer, as represented by an nsistor (hereinafter referred to as SIT).

[0002]

2. Description of the Related Art Conventionally, in a method of manufacturing a semiconductor device of this type, a thermal oxide film SiO ₂ is formed on a first main surface of a semiconductor substrate of a first conductivity type, and then a stripe or mesh is formed by photolithography. The gate electrode layer is formed by making a selective opening of a second conductivity type and by diffusing impurities of a second conductivity type opposite to that of the semiconductor substrate. Further, a semiconductor single crystal layer of the same first conductivity type as that of the semiconductor substrate is formed on the semiconductor substrate by epitaxial growth to form a structure in which a gate electrode layer is embedded. Thereafter, a portion of the gate electrode layer is opened by a thermal oxidation process and a photolithography method, and only the opening is selectively etched at a depth substantially equal to the thickness of the semiconductor single crystal layer to form a gate electrode. The layer is taken out (exposing a predetermined region of the gate electrode layer).

FIGS. 3A to 3D and FIGS. 4A and 4B show a method of manufacturing an SIT having a buried gate structure as an example of a conventional method of manufacturing this type of semiconductor device. It is a schematic process drawing. Hereinafter, FIGS. 3 and 4
, A conventional method of manufacturing an SIT having a buried gate structure will be described.

In FIG. 3A, phosphorus or antimony is diffused at a high concentration from a second main surface (lower surface in the figure) of a silicon wafer to a surface impurity concentration of 10 ¹⁹ cm ⁻³ or more.
An N ⁺ diffusion layer (drain ohmic layer) 1 having a diffusion layer depth of 150 μm and an N ⁻ drain layer 2 are formed. In FIG. 3 (b), the silicon wafer of FIG. 3 (a) H ₂
Thermal oxidation is performed at 1100 ° C. for 15 minutes in an atmosphere containing O vapor to form a SiO ₂ film of about 3000 Å. Thereafter, a negative type photoresist having a viscosity of 40 cp is spin-coated at 4000 rpm for 20 seconds. Thereafter, exposure is performed using a mask-shaped dry plate in a stripe shape, and development is performed. Further, selective etching is performed with buffered hydrofluoric acid (BHF) to form a stripe-shaped SiO ₂ film 3 on the first main surface and an SiO ₂ film 3 ′ on the entire second main surface. In FIG. 3C, a normal open-tube liquid diffusion source is diffused using the SiO ₂ film 3 of FIG. 3B as a diffusion mask and BBr ₃ as an impurity source, and the P ⁺ gate layer 4 and P ⁺
A gate electrode layer 4 'is formed. Thereafter, the substrate is immersed in BHF to remove the SiO ₂ films 3 and 3 ′ of FIG. 3B. FIG.
In (d), epitaxial growth is performed at 1150 ° C. for 20 minutes using SiCl ₄ as a growth source and H ₂ as a carrier gas to grow an N-type single crystal epitaxial growth layer (source layer) 6. Through the above steps, the P ⁺ gate layer 4,
The P ⁺ gate electrode layer 4 ′ has a buried structure.

In FIG. 4A, a thermal oxidation treatment is performed on the silicon wafer of FIG. 3D in the same manner as in FIG. 3B to form an SiO ₂ film on the entire surface. Thereafter, the first main surface so as to selectively leave the photolithography technique to form the SiO ₂ film 7, the SiO ₂ film 7 to the second major surface over the entire surface '
To form In FIG. 4 (b), the silicon wafer of FIG. 4 (a) is used as a mask for selective etching of the SiO ₂ film 7, and a hydrofluoric acid, nitric acid and acetic acid based silicon etchant (HF: HNO ₃ : CH ₃₎ COOH = 1: 5: 1
(Vol ratio)) to expose the embedded P ⁺ gate electrode layer 4 ′ so as to excavate it. After this, B
The SiO ₂ films 7, 7 'are removed by immersion in HF to complete the basic structure of SIT.

[0006]

In the conventional method of manufacturing a semiconductor device, including the examples shown in FIGS. 3 and 4, the single crystal epitaxial growth layer has various thicknesses and the gate electrode layer is exposed. Due to the difficulty in controlling the amount of etching to perform the exposure, poor exposure often occurs in which the region to be exposed of the gate electrode layer cannot be accurately and reliably exposed.

FIGS. 5 (a) and 5 (b) are diagrams each showing an example of a defect relating to a gate electrode layer take-out structure in an SIT manufactured by a conventional manufacturing method. In FIG. 5A, in this SIT, the region to be exposed of the P ⁺ gate electrode layer 4 ′ on the left side in the figure is still buried under the N-type single crystal epitaxial growth layer 6. This is due to insufficient etching. FIG. 5 (a)
In this SIT, most of the P ⁺ gate electrode layer 4 ′ itself on the left side in the figure has disappeared. This is due to excessive etching.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device in which a region to be exposed of a gate electrode layer is completely exposed and the gate electrode layer itself is not lost. It is.

[0009]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a gate layer and a first region in which a gate electrode layer is to be embedded are embedded inside a single crystal epitaxial growth layer. Forming the gate layer and the gate electrode layer on top of a layer, and etching a predetermined etchant on the second region to be exposed of the gate electrode layer with respect to a predetermined etchant more than the single crystal epitaxial growth layer. Forming a low oxide film, growing the single crystal epitaxial growth layer on a region excluding the oxide film, and having a higher etching property on the oxide film with respect to the etching solution than the single crystal epitaxial growth layer. Growing a crystalline epitaxial growth layer, and removing the polycrystalline epitaxial growth layer using the etching solution. And method of manufacturing a semiconductor device, characterized by a step of removing the oxide film can be obtained.

According to the present invention, an etching rate ratio (etching rate of the polycrystalline epitaxial growth layer / etching rate of the single crystal epitaxial growth layer) of the polycrystalline epitaxial growth layer and the single crystal epitaxial growth layer with the etching solution is as follows: A manufacturing method of the semiconductor device having three or more is obtained.

According to the present invention, there is further provided the method of manufacturing the semiconductor device, wherein the etchant is for hydrofluoric acid, nitric acid, and acetic acid-based silicon.

According to the present invention, the etching solution has a vol ratio of hydrofluoric acid, nitric acid and acetic acid of HF: H
The method for manufacturing the semiconductor device in which NO ₃ : CH ₃ COOH = 1: 5: 1 is obtained.

[0013]

1 (a) to 1 (d) and FIG.
(A)-(d) are SITs having a buried gate structure as a method of manufacturing a semiconductor device according to an embodiment of the present invention.
It is a schematic process drawing which shows the manufacturing method of. In these drawings, the same or similar parts as in the conventional example are denoted by the same reference numerals as in FIGS.

Hereinafter, the present manufacturing method will be described with reference to FIGS.

In FIG. 1A, phosphorus or antimony is diffused at a high concentration from a second main surface (lower surface in the figure) of a silicon wafer to a surface impurity concentration of 10 ¹⁹ cm ⁻³ or more.
An N ⁺ diffusion layer (drain ohmic layer) 1 having a diffusion layer depth of 150 μm and an N ⁻ drain layer 2 are formed. In FIG. 1 (b), the silicon wafer of FIG. 1 (a) H ₂
Thermal oxidation is performed at 1100 ° C. for 15 minutes in an atmosphere containing O vapor to form a SiO ₂ film of about 3000 Å. Thereafter, a negative type photoresist having a viscosity of 40 cp is spin-coated at 4000 rpm for 20 seconds. Thereafter, exposure is performed using a mask-shaped dry plate in a stripe shape, and development is performed. Further, selective etching is performed with buffered hydrofluoric acid (BHF) to form a stripe-shaped SiO ₂ film 3 on the first main surface and an SiO ₂ film 3 ′ on the entire second main surface. In FIG. 1 (c), FIG. 1 as a mask for the diffusion of the SiO ₂ film 3 (b), the BBr ₃ subjected to normal open tube liquid diffusion source diffusion as an impurity source, P ⁺ gate layer 4, P ⁺
A gate electrode layer 4 'is formed. Thereafter, the substrate is immersed in BHF to remove the SiO ₂ films 3 and 3 ′ of FIG. 1B. Also,
At the time of drive-in (push-in process) in an oxidizing atmosphere of P ⁺ selective diffusion, the first and second main surfaces respectively have S
The iO ₂ films 5 and 5 ′ are formed. In FIG. 1D, the SiO ₂ film 5 of FIG. 1C is left only on the P ⁺ gate electrode layer 4 ′ by the same photolithography technique as in FIG. 1B. This is referred to as an SiO ₂ film 5 ″.
3A, epitaxial growth is performed at 1150 ° C. for 20 minutes using SiCl ₄ as a growth source and H ₂ as a carrier gas to grow an N-type polycrystalline epitaxial growth layer 6 ′ only on the P ⁺ gate electrode layer 4 ′. The N-type single crystal epitaxial growth layer (source layer)
Grow 6. Through the above steps, the P ⁺ gate layer 4 and the P ⁺
The gate electrode layer 4 'has a buried structure. The thickness of the N-type single crystal epitaxial growth layer 6 and the N-type polycrystal epitaxial growth layer 6 ′ is 10 to 15 μm.

2 (b), the silicon wafer of FIG. 2 (a) is subjected to a thermal oxidation treatment in the same manner as in FIG. 1 (b), and an SiO ₂ film is formed on the entire surface. Thereafter, the first main surface so as to selectively leave the photolithography technique to form the SiO ₂ film 7, the SiO ₂ film 7 to the second major surface over the entire surface '
To form In FIG. 2 (c), the silicon wafer of FIG. 2 (b) is used as a mask for selective etching of the SiO ₂ film 7 to use a hydrofluoric acid, nitric acid and acetic acid-based silicon etchant (HF: HNO ₃ : CH ₃₎ COOH = 1: 5: 1
(Vol ratio)) to perform etching. The thickness of the N-type single crystal epitaxial growth layer 6 and the N-type polycrystal epitaxial growth layer 6 'is 10 to 15 [mu] m, and etching was performed for about 40 to 50 seconds with the present etching solution for silicon. The etching rate of this etching solution is 0.2 μm / sec for single crystal silicon and 0.6 μm for polycrystalline silicon.
/ S, and 0.005 μm / s for SiO ₂ . Therefore, the etching of the etching conditions, N-type polycrystalline epitaxial layer 6 'with is completely removed, the etching is prevented in the SiO ₂ film 5' portion. Therefore, P ⁺ gate electrode layer 4 ' The region to be exposed is completely exposed, and the P ⁺ gate electrode layer 4 ′ itself does not disappear by etching, and the silicon wafer of FIG. ,
The basic structure of the SIT is completed by removing the SiO ₂ films 5 ″, 7 and 7 ′. In the completed SIT, the region where the P ⁺ gate electrode layer 4 ′ is to be exposed is completely exposed. At the same time, the P ⁺ gate electrode layer 4 ′ itself has not disappeared.

The present invention is applicable not only to the SIT but also to the manufacture of all semiconductor devices in which a gate layer is embedded in an epitaxial growth layer.

[0018]

According to the method of manufacturing a semiconductor device according to the present invention,
Forming a gate layer and a gate electrode layer on the semiconductor layer, and forming an oxide film on the second region of the gate electrode layer to be exposed, which has a lower etching property than a single crystal epitaxial growth layer with respect to a predetermined etching solution on a predetermined etching solution; Forming a single crystal epitaxial growth layer on the region excluding the oxide film, and growing a polycrystalline epitaxial growth layer having a higher etching property on the oxide film than the single crystal epitaxial growth layer on the oxide film. Has a step of removing the polycrystalline epitaxial growth layer using an etchant, and a step of removing the oxide film.
A semiconductor device in which a region to be exposed of the gate electrode layer is completely exposed and the gate electrode layer itself is not lost can be manufactured.

[Brief description of the drawings]

FIGS. 1A to 1D are schematic process diagrams showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 2A to 2D are schematic process diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 3A to 3D are schematic process diagrams illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIGS. 4A and 4B are schematic process diagrams showing a method for manufacturing a semiconductor device according to a conventional example.

FIGS. 5A and 5B are diagrams for explaining a problem caused by a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 N ⁺ diffusion layer 2 N ⁻ drain layer 3 SiO ₂ film 4 P ⁺ gate layer 4 ′ P ⁺ gate electrode layer 5, 5 ′, 5 ″ SiO ₂ film 6 N-type single crystal epitaxial growth layer 6 ′ N-type polycrystal epitaxial growth Layer 7, 7 'SiO ₂ film

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device in which a gate layer and a first region in which a gate electrode layer is to be buried are buried inside a single crystal epitaxial growth layer, wherein the gate layer and the gate are formed above a semiconductor layer. Forming an electrode layer; and forming an oxide film having a lower etching property on the second region to be exposed of the gate electrode layer with respect to a predetermined etchant than the single crystal epitaxial growth layer, Growing the single-crystal epitaxial growth layer on the region excluding the oxide film, and growing a polycrystalline epitaxial growth layer having a higher etching property on the oxide film than the single-crystal epitaxial growth layer with respect to the etchant; Removing the polycrystalline epitaxial growth layer using an etchant; and removing the oxide film. And a method of manufacturing a semiconductor device. 2. An etching rate ratio of said polycrystalline epitaxial growth layer and said single crystal epitaxial growth layer to said etchant (etching rate of said polycrystalline epitaxial growth layer / etching rate of said single crystal epitaxial growth layer) is 3 or more. Item 2. A method for manufacturing a semiconductor device according to item 1. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching solution is for use with hydrofluoric acid, nitric acid, and acetic acid-based silicon. 4. The etching solution according to claim 1, wherein a vol ratio of hydrofluoric acid, nitric acid, and acetic acid is HF: HNO ₃ : CH ₃ COO.
4. The method according to claim 3, wherein H = 1: 5: 1.