JPH04324922A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To sharply improve the alignment accuracy of photomask in an epitaxial process and succeeding processes. CONSTITUTION:A stepping 12, which becomes an alignment mark, is formed on the surface of a substrate 11, and an epitaxial layer 14 is selectively grown on the surface of the substrate 11 excluding the region where the stepping 12 is formed. The mask alignment of the surface of the epitaxial layer 14 is conducted on the stepping 12 of the surface of the exposed substrate 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to alignment marks for photomasks of bipolar ICs.

0002

[Background Art] In the process of manufacturing bipolar ICs, a technique is used in which a Si layer is grown by epitaxial technology on a Si semiconductor substrate, and impurities for semiconductor elements such as transistors are selectively diffused onto the surface of this Si layer. is well known. In order to perform alignment in the lithography process for selective diffusion, etc., a small step is provided in advance on a part of the substrate surface in order to define the positional relationship with the high concentration buried layer formed on the substrate surface. , as a mask positioning index (alignment mark) after epitaxial growth.

[0003] The form of a second step appearing on the surface of an epitaxial layer formed thereon due to a step on the substrate surface is described in, for example, Japanese Patent Publication No. 58-43903.

0004

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, as shown in FIG. As a result, the alignment marks become asymmetrical. Therefore, there was a drawback that alignment accuracy during exposure was reduced. In particular, it is known that when the epitaxial growth conditions are set to a low temperature, the deformation and asymmetry of the step increases.

[0005] Regarding this problem, Japanese Patent Laid-Open No. 01-1406
As shown in No. 24, a technique for growing amorphous or polysilicon on alignment marks has been proposed. However, there is a drawback that it is difficult to grow amorphous or polysilicon simultaneously with the single crystal epitaxial layer (2) with good controllability.

[0006]

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned drawbacks of the conventional art, and includes covering steps (12) serving as alignment marks with an amorphous film, and not covering the steps (12) with an amorphous film. An epitaxial layer (14) is formed only on the surface of the substrate (11).
) is selectively grown and alignment can be performed at the step on the substrate (11), thereby providing a semiconductor device and its manufacturing method that can significantly improve alignment accuracy.

[0007]

According to the present invention, the primary step (12) on the surface of the substrate (11) can be used as an alignment mark as is, instead of the secondary step that appears on the surface of the epitaxial layer (14). Therefore, a pattern without pattern shift or sag can be used, and alignment accuracy can be greatly improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing an alignment mark portion of the present invention, and FIG. 2 is a plan view showing the alignment mark. The P-type silicon semiconductor substrate (11) is sliced from a silicon single crystal ingot in the (100) plane direction, and in some cases, sliced at an angle of several degrees from the (100) plane. The depth of 0.1 to 0.1 to form an alignment mark on the surface of the area that should become the scribe line or the corner area of the pellet pattern.
A step (12) of about 0.3μ is formed. The step (12) portion has an N+ type buried layer (13) formed by forming a buried layer of an NPN transistor in order to form the step (12). The alignment mark due to the step (12) is formed in a pattern as shown in FIG. 2 in an area of approximately 100μ×100μ or less.

The surface of the substrate (11) except for the region where the alignment mark is formed is coated with a substrate (11) by vapor phase epitaxy.
It has an N-type epitaxial layer (14) with a thickness of 2 to 4 μm grown according to the plane orientation of 11). Epitaxial layer (
A number of semiconductor circuit elements are built into the surface of 14) using well-known planar technology. An example of the manufacturing method of the present invention will be described below.

(1) Silicon substrate with plane orientation (100) (
The surface of 11) is thermally oxidized to form an oxide film (15), and the N
An oxide film (1
5) Pattern. At the same time, an opening (16) is formed in the area where the alignment mark is to be formed, and the opening (16) is formed in the area where the alignment mark is to be formed.
6) to dope antimony (As) for forming a buried layer (FIG. 3). In this step, a buried layer (13) is also formed in the alignment mark formation region.

(2) Pre-doped antimony (As)
The buried layer (13) is driven in by thermal diffusion. This step is performed in an oxidizing atmosphere, and an oxide film is formed at the same time as the drive-in. The silicon on the surface of the buried layer (13) is etched by the oxide film formation, forming steps (12) forming a mask pattern (FIG. 4). still,
The process for creating the step (12) is not limited to the one using the above-mentioned buried layer formation, for example, CDE.
It can also be formed by selective isotropic etching of silicon using a chemical dry etcher (chemical dry etcher).

(3) The formed oxide film (15) is patterned to form an insulating film (16) as an amorphous film that covers only the alignment mark region (FIG. 5). In addition to the silicon oxide film, the amorphous film may be made of any material such as a silicon nitride film, as long as it can prevent single crystal epitaxial growth. (4) The substrate (
11) A single-crystal N-type epitaxial layer (14) grown in accordance with the plane orientation of the substrate (11) is grown by 2 to 4 μm on top (FIG. 6). At this time, by covering the step (12) with an amorphous insulating film (16), the single crystal epitaxial layer (14) is not grown on the insulating film (16). Although there is a possibility that amorphous or polycrystalline silicon may be deposited, the growth of silicon on the insulating film (16)
6) Since it has a property that depends on the area, these conditions are used to control it so that it does not grow. The conditions vary depending on the epitaxial growth conditions, but the SiH2
Under the conditions of low-temperature epitaxial growth using Cl2, the growth of silicon on the insulating film (16) can be prevented by setting the area of the insulating film (16) to approximately 100 μ x 100 μ or less.

(5) The insulating film (16) is removed using hydrofluoric acid (FIG. 7). After this, in a normal bipolar process, the surface of the epitaxial layer (14) is oxidized, photoresist is applied, and photoetching is performed to diffuse the isolation region.
The surface step (12) serves as a reference for mask alignment.

As is clear from the above examples, since the present invention performs epitaxial growth selectively except for the alignment mark region, the step (12) on the surface of the substrate (11)
can be used as is as a reference for alignment. Therefore, there is no misalignment or asymmetry of the reference pattern due to epitaxial growth, and alignment accuracy can be greatly improved.

[0015]

[Effects of the Invention] As explained above, according to the present invention,
Since the step (12) on the surface of the substrate (11) is exposed, the accuracy of mask alignment after epitaxial growth can be greatly improved. Therefore, it is possible to further promote miniaturization and high integration of elements.

[Brief explanation of the drawing]

FIG. 1 is a sectional view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a first cross-sectional view illustrating the manufacturing method of the present invention.

FIG. 4 is a second sectional view illustrating the manufacturing method of the present invention.

FIG. 5 is a third sectional view illustrating the manufacturing method of the present invention.

FIG. 6 is a fourth sectional view illustrating the manufacturing method of the present invention.

FIG. 7 is a fifth sectional view illustrating the manufacturing method of the present invention.

FIG. 8 is a sectional view for explaining a conventional example.

Claims (5)

[Claims] 1. A semiconductor substrate of one conductivity type, an alignment mark formed on a part of the surface of the substrate and consisting of a surface step of the substrate, and a semiconductor substrate of the substrate other than the area where the alignment mark is formed. 1. A semiconductor device comprising: an epitaxial layer of opposite conductivity type grown according to a plane orientation; and a plurality of circuit elements formed on a surface of the epitaxial layer. 2. The semiconductor device according to claim 1, further comprising a diffusion region formed simultaneously with a buried layer of an opposite conductivity type in a stepped portion of the substrate surface. 3. A step of forming a step serving as an alignment mark on the surface of a semiconductor substrate of one conductivity type, a step of covering the region where the alignment mark is formed with an amorphous film, and a step of covering the region with the insulating film. A step of growing an epitaxial layer of the opposite conductivity type according to the surface orientation of the substrate on the surface of the substrate that has not been etched, a step of removing an insulating film covering the alignment mark, and a photomask for the next step using the alignment mark. 1. A method for manufacturing a semiconductor device, comprising the step of aligning. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of the alignment mark is formed by forming a buried layer of an opposite conductivity type. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the amorphous film is a silicon oxide film.