JP2773905B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device using vertical diffusion separation as a method for separating an element formation region from others.

(Prior Art) A typical method of manufacturing a conventional bipolar semiconductor device using vertical diffusion separation will be described with reference to the process sectional views of FIGS. 5 (a) to 5 (j).

First, as shown in FIG. 5A, an oxide film 2 is formed on a P-type silicon substrate 1, and a window 3 for performing selective diffusion is formed by photolithography.

Next, as shown in FIG. 5B, a high concentration N-type impurity is diffused from the window 3 to the P-type silicon substrate 1 to form a buried layer 4. In this buried diffusion step, an oxidizing gas is flowed to form an oxide film 5 on the buried layer 4 in order to form a mask oxide film for the next P-type impurity diffusion. At this time, by oxidizing the substrate silicon, a shallow flat bottom step 6 having a depth of about 1000 ° is formed in the buried layer 4.

Next, as shown in FIG. 5 (c), the P-type silicon substrate 1
A window 7 for performing selective diffusion is formed in the oxide film 2 by photolithography so as to surround the buried layer 4.

Next, as shown in FIG. 5D, a P-type impurity is implanted into the P-type silicon substrate 1 through the window 7 by ion implantation to form a buried P-type layer 8 shallow.

Next, as shown in FIG. 5 (e), the buried P-type layer 8 is driven to a predetermined depth in an oxygen atmosphere. At this time, the silicon substrate is oxidized, and an oxide film 9 is formed in the buried P-type layer 8, so that the buried P-type layer 8 has a shallow flat bottom step 10 with a depth of about 1000 °.
Is formed.

Thereafter, as shown in FIG. 5 (f), the oxide films 2, 5, and 9 are removed, and then the N-type impurity doped layer is formed on the P-type silicon substrate 1 having the N-type buried layer 4 and the buried P-type layer 8. Is grown. When growing this epitaxial layer,
The N-type buried layer 4 and the buried P-type layer 8 are each diffused upward by heat at the time of growth (normally 1050 ° C. to 1200 ° C.) as shown in the figure. When the epitaxial layer 11 is grown on the silicon substrate 1 having the steps 6, 10 as described above, the steps 6, 10 are also transferred to the surface of the epitaxial layer 11 as steps 6 ', 10'. However, this transfer is shifted. That is, the steps 6, 10 have a slope 12 with the original surface at the end, and a difference in growth rate occurs in the epitaxial growth between the slope 12 and the step bottom 13, so that a phenomenon called pattern shift occurs. As shown in FIG. 5F, the steps 6 ', 10' after the epitaxial layer growth are formed at positions different from the positions of the steps 6, 10 formed by the N-type buried layer 4 and the buried P-type layer 8. Is done. Such a pattern shift phenomenon is described in the document "Solid state technology / Japanese version / January 1982, P61.
-P68 "and are well known.

Next, as shown in FIG.
An oxide film 14 is formed thereon.

Thereafter, as shown in FIG. 5H, a window 15 for selective diffusion is formed in the oxide film 14 by using a photolithography technique.
At this time, the photolithography is adjusted by the step of the buried P-type layer 8.
10 is performed by using a step 10 'formed on the surface of the epitaxial layer 11 by transfer, so that the window 15 and the next isolation layer are located at appropriate positions outside the buried layer 4. Perform alignment.

Next, as shown in FIG. 5 (i), a high-concentration P-type impurity is diffused from the window 15 so as to penetrate the epitaxial layer 11 and reach the upper diffusion portion of the buried P-type layer 8, thereby performing isolation. The layer 16 is formed. This isolation layer 16
The buried P-type layer 8 separates the inner epitaxial layer region from the others, thereby forming an element forming region 17. During the diffusion of the P-type impurity, an oxide film 18 is formed on the window 15 (the surface of the isolation layer 16).

Thereafter, as shown in FIG.
When an NPN transistor is formed, a base region 19 is formed by diffusing a P-type impurity, and an emitter region 20 and a collector extraction region 21 are formed by diffusing an N-type impurity. Finally, as shown in the figure, the epitaxial layer
A window for making contact with each diffusion layer is opened in the oxide film 22 on the surface 11 to form a wiring layer 23.

(Problems to be Solved by the Invention) However, the conventional manufacturing method as described above has the following problems.

When the epitaxial layer 11 is grown as shown in FIG. 5 (f), the steps 6, 10 of the buried layer 4 and the buried P-type layer 8 are shifted from the surface of the epitaxial layer 11 as steps 6 ', 10'. Transcribed.

FIG. 6 shows details of this pattern shift. In FIG. 6, 1 is a P-type silicon substrate, 8 is a buried P-type layer, 11 is an epitaxial layer, 10 is a step in the buried P-type layer 8, and 10 'is a step transferred to the surface of the epitaxial layer 11. , Θ are the center of the step 10 formed in the buried P-type layer 8 and the step 1 transferred to the surface of the epitaxial layer 11.
This is an angle with the center of 0 ', and is called a pattern shift angle.

The pattern shift angle θ is determined by the growth conditions of epitaxial growth, for example, the growth temperature, thickness,
The angle θ varies depending on the growth rate, the gas used, and the like. Generally, θ changes between 5 ° and 55 ° due to the above-mentioned difference in the conditions.

In the conventional method, the step 10 of the buried P-type layer 8
The step 10 'on the surface of the epitaxial layer 11 deviated from that of FIG. 5 is used for mask alignment in the photolithography technique (the window formation shown in FIG. 5 (h), and further the isolation shown in FIG. 5 (i)). The layer 16 is formed, so that when the step 10 'is shifted, that is, when the pattern shift angle θ is small, the isolation layer 16 is buried although there is a shift due to the pattern shift as shown in FIG. There is no problem in that the element formation regions 17 on the P-type layer 8 are electrically separated from each other, and there is no problem. However, when the pattern shift angle θ is large, the shift due to the pattern shift as shown in FIG. Therefore, the isolation layer 16 did not overlap with the buried P-type layer 8 and the element formation region 17 could not be electrically separated.

In order to avoid this problem, the width La of the isolation layer 16 may be set to be as large as the width La ′ as shown in FIG. 8, but this method can electrically isolate the element formation region 17, Since the width Lb of the element formation region 17 is reduced to the width Lb ', the molecule formation region 17 must be increased, and as a result, there is a problem that the integration degree of the integrated circuit is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and provides a semiconductor device which can form an isolation layer accurately on a lower isolation layer (buried P-type layer) without increasing the width of the isolation layer. It is intended to provide a manufacturing method.

(Means for Solving the Problems) In the first aspect of the present invention, a first buried layer of the same conductivity type as a lower isolation layer is provided in a semiconductor substrate of one conductivity type;
Forming simultaneously a second buried layer of the same conductivity type as an alignment mark, forming an epitaxial layer of the opposite conductivity type on the substrate, forming a groove in a part of the epitaxial layer, The second diffused upward into the second
The upper surface of the buried layer is exposed at the bottom of the groove, and the upper surface of the second buried layer is colored with a coloring liquid utilizing the difference in conductivity type, and the upper surface of the colored second buried layer is positioned. An alignment mark is formed on the mask layer on the surface of the epitaxial layer by a photolithographic technique of a window for forming an upper isolation layer, and impurities are introduced through the window so as to reach the first buried layer (lower isolation layer). An upper isolation layer is formed in the epitaxial layer.

In the second aspect of the present invention, a first buried layer of the same conductivity type as a lower isolation layer is formed in a semiconductor substrate of one conductivity type;
After simultaneously forming a second buried layer of the same conductivity type as an alignment mark and forming an epitaxial layer of the opposite conductivity type on the substrate, the epitaxial layer is etched using an etching solution having a different etching rate depending on the impurity concentration. Forming a groove in a part thereof, projecting an upper portion of the second buried layer diffused upward from a bottom portion thereof, and using the upper portion of the protruded second buried layer as an alignment mark above the mask layer on the surface of the epitaxial layer. A window for forming an isolation layer is formed by a photolithography technique, and an upper isolation layer is formed in the epitaxial layer so as to reach the first buried layer (lower isolation layer) by introducing impurities through the window. .

(Operation) Now, assume that the second buried layer as the alignment mark is P-type and the epitaxial layer is N-type. When a groove is formed in the epitaxial layer as in the first embodiment of the present invention and the upper surface of the second buried layer is exposed at the bottom thereof, only the upper surface of the second buried layer becomes P-type in this groove. Others are N-type due to the epitaxial layer. In such a groove, for example, about 1%
When the liquid mixed with concentrated HNO ₃ is dropped, only the P-type portion, that is, the upper surface of the second buried layer is dyed black, and the upper surface of the second buried layer can be visually checked thereafter, and can be used as an alignment mark. . Here, the second buried layer is formed at the same time as the first buried layer as the lower isolation layer, that is, at a precise interval from the first buried layer using one photomask. ing. Therefore, a window for forming an upper isolation layer is opened by photolithography using the upper surface of the second buried layer as an alignment mark, and an upper isolation layer is formed through the window. The upper isolation layer can be accurately positioned on the lower isolation layer (first buried layer) without increasing the width of the layer.

In the first aspect of the present invention, the upper surface of the second buried layer is colored black so that it can be used as an alignment mark. In the second aspect of the present invention, the upper part of the second buried layer is formed. Are projected to the bottom of the groove so that the second buried layer can be recognized from the step between the top of the second buried layer and the bottom of the groove, and this can be used as an alignment mark.

For example, an etching solution such as an aqueous solution of ethylenediamine procatechol has a different etching rate depending on the impurity concentration, and the higher the impurity concentration, the lower the etching rate. Usually, the epitaxial layer has a low impurity concentration of 1 × 10 ¹⁵ cm ^−3, and the buried layer has a high impurity concentration of 1 × 10 ¹⁹ cm ⁻³ .
Therefore, if the epitaxial layer is etched slightly below the upper surface of the second buried layer diffused upward using an etchant such as the aqueous solution of ethylenediamine procatechol to form a groove, the second buried layer having a high impurity concentration can be formed. The embedded layer remains without being etched and protrudes to the groove bottom. If the upper portion of the second buried layer protrudes to the groove bottom as described above, the upper portion of the second buried layer is recognized from the step between the upper portion of the second buried layer and the groove bottom as described above. This can be used as a positioning mark. By using the second buried layer as an alignment mark, the upper isolation layer can be replaced with the lower isolation layer without increasing the width of the upper isolation layer as in the first aspect of the present invention. It can be accurately positioned on the (first buried layer).

Embodiment An embodiment of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. 1 (a) to 1 (l).

First, as shown in FIG. 1A, an oxide film 32 is formed on a P-type silicon substrate 31, and a window 33 for performing selective diffusion is formed by photolithography.

Next, as shown in FIG. 1B, a high concentration N-type impurity is diffused from the window 33 to the P-type silicon substrate 31 to form a buried layer. In this buried diffusion step, an oxidizing gas is flowed to form an oxide film 35 on the upper surface of the buried layer 34 in order to form a mask oxide film for the next P-type impurity diffusion. At this time, by oxidizing the substrate silicon, a shallow flat-bottom step 36 having a depth of about 1000 ° is formed in the buried layer 34.

Next, as shown in FIG. 1C, a P-type silicon substrate 31 is formed.
First, windows 37 and 38 for performing selective diffusion are formed in the oxide film 32 by photolithography. Here, the window 37 is formed so as to surround the buried layer 34, and the window 38 is formed outside the window 37.

Next, as shown in FIG. 1 (d), P-type impurities are implanted into the P-type silicon substrate 31 from the windows 37 and 38 by ion implantation to form buried P-type layers 39 and 40 shallowly. Where the embedded P
The mold layer 39 is a buried P-type layer as a lower isolation layer, and is formed corresponding to the window 37. In addition, a buried P-type layer as an alignment mark with respect to the buried P-type layer 40 is provided.
Is formed in correspondence with.

Next, as shown in FIG. 1 (e), the buried P-type layers 39, 40 are driven in the substrate in an oxygen atmosphere.
Is a predetermined depth. At this time, since the substrate silicon is oxidized and the oxide films 41 and 42 are formed on the buried P-type layers 39 and 40, the buried P-type layers 39 and 40 have a shallow flat bottom step 43, of about 1000 °. 44 is formed.

Thereafter, as shown in FIG. 1 (f), the oxide films 32, 35, 41, 4
2 is removed, the N-type buried layer 34 and the buried P-type layers 39, 40
An N-type impurity doped epitaxial layer 45 is grown on a P-type silicon substrate 31 having During the growth of the epitaxial layer, the N-type buried layer 34 and the buried P-type layers 39 and 40 are respectively diffused upward into the epitaxial layer 45 as shown in the figure by the heat of the growth (usually 1050 ° C. to 1200 ° C.). Also, steps
36, 43, and 44 also have steps 36 ', 43'4 on the surface of the epitaxial layer 45.
Transcribed as 4 '. At this time, a pattern shift occurs as in the related art.

Next, as shown in FIG.
An oxide film 46 is formed thereon.

Next, a resist 47 is applied on the oxide film 46 as shown in FIG. 1H, and a window 48 is formed in the oxide film 46 by a photolithography technique using the resist 47. At that time,
Mask alignment (mask alignment at the time of exposing the resist 47) is performed using a step 44 'generated on the surface of the epitaxial layer 45 by transferring the step 44 of the buried P-type layer 40. The window 48 is formed in the portion of the step 44 ', which is larger than the step 44', using the step 44 'as a reference. FIG. 2 (a) is a plan view of this portion after the window 48 is formed.
Of course, since the buried P-type layer 40 is buried in the epitaxial layer 45, its position is not known here.

Thereafter, while the resist 47 is left, the epitaxial layer 45 is dry-etched through the window 48 using the oxide film 46 as a mask as shown in FIG. The upper surface of the buried P-type layer 40 is exposed. At this time, it is necessary to control the etching so as to be deeper than the upper end of the buried P-type layer 40 diffused upward into the epitaxial layer 45 but not to reach the P-type silicon substrate 31. It is necessary to measure the thickness of 45 using a well-known measuring method using an FTG (infrared interference device), and to calculate the required etching time from the etching rate and control it accurately from that etching time. it can.

After that, the most commonly used coloring liquid,
A mixture of HF and about 1% concentrated HON ₃ is dropped in the groove 49. Then, in the groove 49, the exposed upper surface of the buried P-type layer 40 is P-type, and the other is N-type by the epitaxial layer 45. According to the coloring liquid, the P-type is dyed black and the N-type is changed. Buried P-type layer
Only the upper surface of the buried P-type layer 40 is dyed black, and the upper surface of the buried P-type layer 40 becomes visible thereafter. FIG. 2 (b) is a plan view of the groove after coloring. The coloring method using this coloring liquid is disclosed in detail in "Basics of Silicon Integration Technology", published on May 30, 1980, P123.

Thereafter, the coloring liquid is removed, and the resist 47 is further removed. Then, as shown in FIG. 1 (j), a resist 50 is applied again on the oxide film 46 and the entire surface of the groove. Next, the resist 50 is mask-aligned, exposed, and developed to form a resist 50 as shown in FIG.
The window 51 is opened. At this time, mask alignment is performed using the upper surface of the buried P-type layer 40, which has been dyed black and visible through the resist 50 (transparent), as an alignment mark. The window 51 is formed in the resist 50 by accurately aligning the window 51 with the buried P-type layer 39 as a mask. At this time, as shown in FIG. 3 (a), two alignment marks 40 'formed by the buried diffusion layer 40 are provided on the substrate 31 side, and the alignment marks 40' are likewise shown in FIG. 3 (b). 2 as shown
By superimposing the alignment marks 53 on the mask 52 provided at several places, mask alignment can be performed with extremely high accuracy. When opening this window, the 49
50 have also been removed.

Thereafter, the oxide film 46 is etched through the window 51 using the resist 50 as a mask, so that the window 51 is a window penetrating to the oxide film 46 as shown in FIG.

Thereafter, after the resist 50 is removed, a high concentration P-type impurity is diffused into the epitaxial layer 45 through the window 51 using the oxide film 46 as a mask, thereby obtaining the structure shown in FIG.
As shown in FIG. 7, an upper isolation layer 54 which is overlapped on the buried P-type layer 39 and reaches the buried P-type layer 39 (lower isolation layer) is formed in the epitaxial layer 45. At this time, the P-type impurity is also diffused into the epitaxial layer 45 in the groove 49, and the width of the upper portion of the buried P-type layer 40 is increased to the full width of the groove. However, the coloring area does not change. At the same time, an oxide film is formed on the window 51 (the surface of the upper isolation layer 54) and the groove 49.
55 are formed.

By forming the upper isolation layer 54 in this manner, the inner epitaxial layer region is separated from the others by the upper isolation layer 54 and the buried P-type layer (lower isolation layer) 39. An element formation region 56 is formed.

Thereafter, as shown in FIG.
When an NPN transistor is formed, a base region 57 is formed by diffusing a P-type impurity, and an emitter region 58 and a collector extraction region 59 are formed by diffusing an N-type impurity. Finally, as shown in the figure, the epitaxial layer
In the oxide film 60 on the surface 45, a window for making contact with each diffusion layer is opened to form a wiring layer 61.

In the above-described first embodiment, the upper surface of the buried P-type layer 40 exposed at the bottom of the groove 49 is colored black so that it can be used as an alignment mark. In the embodiment, the upper part of the buried P-type layer 40 is made to project from the bottom of the groove 49 so that the upper part of the buried P-type layer 40 can be recognized from the step between the upper part of the buried P-type layer 40 and the bottom of the groove 49. Make it available as an alignment mark. The second embodiment differs from the first embodiment shown in FIG. 1 only in this point. Therefore, in the following description, a step of forming a groove 49 and projecting the upper part of the buried P-type layer 40 at the bottom thereof is described. Only about
Others are omitted.

In the second embodiment of FIG. 4, the same steps as in the first embodiment of FIG. 1 are performed until the step of forming the window 48 as shown in FIGS. 4 (a) to 4 (h).

Next, while the resist 47 is left, the epitaxial layer 45 is etched through the window 48 using the oxide film 46 as a mask as shown in FIG. At this time, the etching is wet etching, and an aqueous solution of ethylenediamineprocatechol is used as an etching solution. The etching depth is set to be slightly lower than the upper surface of the buried P-type layer 40 which is diffused upward into the epitaxial layer 45. As in the case of the first embodiment, such etching depth control is performed by measuring the thickness of the epitaxial layer 45 in advance using an apparatus such as FTG and determining the etching rate in etching using an aqueous solution of ethylenediamineprocatechol. The required etching time can be obtained by calculation and can be accurately controlled from the etching time.

Incidentally, the etching rate of the aqueous solution of ethylenediamine procatechol varies depending on the impurity concentration, and the higher the impurity concentration, the lower the etching rate. Where
The epitaxial layer 45 has a low impurity concentration of 1 × 10 ¹⁵ cm ^−3, and the buried P-type layer 40 (boron doped) has a concentration of 1 × 10 ¹⁹
High impurity concentration of cm ^-3 . Therefore, when the trench 49 is formed by etching the epitaxial layer 45 with the above-described depth using an aqueous solution of ethylenediamineprocatechol, the embedded P
Since the etching rate of the mold layer 40 is about 1/10 of that of the epitaxial layer 45, it remains almost without being etched. Therefore, as shown in FIG.
The upper portion of the mold layer 40 projects to the bottom of the groove 49. If the upper portion of the buried P-type layer 40 projects to the bottom of the groove 49, the upper portion of the buried P-type layer 40 can be recognized from the step between the upper portion of the buried P-type layer 40 and the bottom of the groove 49. Can be used as an alignment mark.

Thereafter, as shown in FIGS. 4 (j) to (l), the same steps as in the first embodiment of FIG. 1 are performed again to complete the semiconductor device. However, in the second embodiment, needless to say, when the window 51 is opened in the resist 50 in FIG.
Mask alignment is performed by using the protruding upper portion of the buried P-type layer 40 as an alignment mark, thereby accurately positioning the buried P-type layer 39 on the buried P-type layer 39 as the lower isolation layer, as in the first embodiment. As a result, the window 51 can be formed in the resist 50, so that the upper isolation layer 54 of FIG. 1 (k) can be accurately formed on the buried P-type layer 39.

(Effects of the Invention) As described above in detail, according to the method of the present invention, the second buried layer is formed simultaneously with the first buried layer as the lower isolation layer, and the upper surface thereof is epitaxially formed. The upper isolation layer is widened because it is exposed at the bottom in the groove of the layer and colored, or the upper part of the second buried layer is protruded into the groove to mark them as alignment marks. Even without this, the upper isolation layer can be accurately positioned on the lower isolation layer, and a highly accurate isolation region can be formed without narrowing the element formation region. Therefore, it is not necessary to widen the element formation region, and the degree of integration of the integrated circuit is not reduced.

[Brief description of the drawings]

1 is a process sectional view showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a plan view of a main part in the course of manufacturing, and FIG. FIG. 4 is a process sectional view showing a second embodiment of the present invention, FIG. 5 is a process sectional view showing a conventional manufacturing method, and FIG. 6 is a sectional view showing a pattern shift in detail. FIG. 7 is a cross-sectional view showing a result produced by the magnitude of the pattern shift angle, and FIG. 8 is a cross-sectional view showing a measure for preventing separation. 31 ... P-type silicon substrate, 39 ... Buried P-type layer, 40 ...
Buried P-type layer, 45 ... Epitaxial layer, 49 ... Groove, 51
... windows, 54 ... upper isolation layer.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/73 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/76-21/765 H01L 21/027 H01L 21/30 H01L 21/46 H01L 21/205

Claims (2)

(57) [Claims] (A) A first buried layer of the same conductivity type as a lower isolation layer and a second buried layer of the same conductivity type as an alignment mark are simultaneously formed on a semiconductor substrate of one conductivity type. (B) growing an epitaxial layer of the opposite conductivity type on the semiconductor substrate and simultaneously diffusing the buried layer upward,
Forming a groove in a part of the epitaxial layer and exposing the upper surface of the upwardly diffused second buried layer at the bottom thereof; and (c) forming the upper surface of the second buried layer with a different conductivity type. And (d) using the colored upper surface of the second buried layer as an alignment mark to isolate the upper surface at a predetermined position of a mask layer formed on the surface of the epitaxial layer. Forming a layer forming window by photolithography; and (e) introducing one conductivity type impurity into the epitaxial layer through the window to form the first burying as a lower isolation layer diffused upward. Forming an upper isolation layer in the epitaxial layer so as to reach the layer. (A) A first buried layer of the same conductivity type as a lower isolation layer and a second buried layer of the same conductivity type as an alignment mark are simultaneously formed on a semiconductor substrate of one conductivity type. (B) growing an epitaxial layer of the opposite conductivity type on the semiconductor substrate and simultaneously diffusing the buried layer upward; and (c) using an etchant having an etching rate different depending on the impurity concentration. Forming a groove in a part of the epitaxial layer and projecting an upper part of the upwardly diffused second buried layer at the bottom thereof; and (d) aligning the upper part of the protruded second buried layer. Forming a window for forming an upper isolation layer by photolithography at a predetermined position of a mask layer formed on the surface of the epitaxial layer as a mark; and (e) forming a window on the epitaxial layer through the window. Forming an upper isolation layer in the epitaxial layer so as to reach a first buried layer as a lower isolation layer which is diffused upward by introducing impurities of a conductivity type. Manufacturing method.