JPH10320277A5 - - Google Patents

Info

Publication number
JPH10320277A5
JPH10320277A5 JP1997301182A JP30118297A JPH10320277A5 JP H10320277 A5 JPH10320277 A5 JP H10320277A5 JP 1997301182 A JP1997301182 A JP 1997301182A JP 30118297 A JP30118297 A JP 30118297A JP H10320277 A5 JPH10320277 A5 JP H10320277A5
Authority
JP
Japan
Prior art keywords
data
cacheable
response
storage circuit
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997301182A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10320277A (ja
Filing date
Publication date
Application filed filed Critical
Publication of JPH10320277A publication Critical patent/JPH10320277A/ja
Publication of JPH10320277A5 publication Critical patent/JPH10320277A5/ja
Pending legal-status Critical Current

Links

JP9301182A 1996-10-31 1997-10-31 マイクロプロセッサ回路およびシステム Pending JPH10320277A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2923296P 1996-10-31 1996-10-31
US029232 1996-10-31

Publications (2)

Publication Number Publication Date
JPH10320277A JPH10320277A (ja) 1998-12-04
JPH10320277A5 true JPH10320277A5 (enExample) 2005-07-07

Family

ID=21847956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9301182A Pending JPH10320277A (ja) 1996-10-31 1997-10-31 マイクロプロセッサ回路およびシステム

Country Status (3)

Country Link
EP (1) EP0840232B1 (enExample)
JP (1) JPH10320277A (enExample)
DE (1) DE69727031T2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0886216A1 (en) 1997-06-06 1998-12-23 Texas Instruments Incorporated Microprocessor comprising means for storing non-cacheable data
JP2011248515A (ja) * 2010-05-25 2011-12-08 Panasonic Corp キャッシュコントローラ及びその制御方法
CN115878507B (zh) * 2023-01-19 2023-07-21 北京象帝先计算技术有限公司 系统级芯片的内存访问方法、装置及电子设备
CN115794675B (zh) * 2023-01-19 2023-05-16 北京象帝先计算技术有限公司 写数据方法、装置、图形处理系统、电子组件及电子设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382396A3 (en) * 1989-02-08 1991-11-27 Hitachi, Ltd. Program memory buffer for processor
US5561780A (en) * 1993-12-30 1996-10-01 Intel Corporation Method and apparatus for combining uncacheable write data into cache-line-sized write buffers

Similar Documents

Publication Publication Date Title
JP3934710B2 (ja) マイクロプロセッサ
US8972671B2 (en) Method and apparatus for cache transactions in a data processing system
JP2007504552A5 (enExample)
US6343344B1 (en) System bus directory snooping mechanism for read/castout (RCO) address transaction
US6874056B2 (en) Method and apparatus for reducing cache thrashing
GB2260432A (en) Processor for multiple cache coherent protocols
JPH1083346A5 (enExample)
JP2005158040A5 (enExample)
EP0840455A3 (en) A microcontroller accessible macrocell
GB2260628A (en) Line buffer for cache memory
JPH11175454A5 (enExample)
JPH08272688A5 (enExample)
EP1284457A3 (en) Internal cache block eviction with external request
JPH10320277A5 (enExample)
JP2001222468A5 (enExample)
JP2007502480A5 (enExample)
JP5635311B2 (ja) リンクされているデータストアにおいて、アイテムの保存およびアイテムの上書きを決定するデータ保存プロトコル
CN101116063A (zh) 具有高速缓存内存之系统及访问方法
GB2246002A (en) Self configuring cache for microprocessor
JPH04357539A (ja) ２重ポートのキャッシュタグメモリデバイス
JP3971807B2 (ja) キャッシュ記憶装置および方法
EP0840232A3 (en) Microprocessor comprising means for storing non-cacheable data
US6643736B1 (en) Scratch pad memories
US6324617B1 (en) Method and system for communicating tags of data access target and castout victim in a single data transfer
JPH08179988A (ja) キャッシュメモリ制御回路