JPH11175454A5 - - Google Patents

Info

Publication number
JPH11175454A5
JPH11175454A5 JP1998278559A JP27855998A JPH11175454A5 JP H11175454 A5 JPH11175454 A5 JP H11175454A5 JP 1998278559 A JP1998278559 A JP 1998278559A JP 27855998 A JP27855998 A JP 27855998A JP H11175454 A5 JPH11175454 A5 JP H11175454A5
Authority
JP
Japan
Prior art keywords
queue
packets
completion
posted
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998278559A
Other languages
English (en)
Japanese (ja)
Other versions
JP4104746B2 (ja
JPH11175454A (ja
Filing date
Publication date
Priority claimed from US08/940,367 external-priority patent/US6128669A/en
Application filed filed Critical
Publication of JPH11175454A publication Critical patent/JPH11175454A/ja
Publication of JPH11175454A5 publication Critical patent/JPH11175454A5/ja
Application granted granted Critical
Publication of JP4104746B2 publication Critical patent/JP4104746B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP27855998A 1997-09-30 1998-09-30 自動直接メモリ・アクセス機能を備えたコンピュータ・システム Expired - Fee Related JP4104746B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US940367 1997-09-30
US08/940,367 US6128669A (en) 1997-09-30 1997-09-30 System having a bridge with distributed burst engine to decouple input/output task from a processor

Publications (3)

Publication Number Publication Date
JPH11175454A JPH11175454A (ja) 1999-07-02
JPH11175454A5 true JPH11175454A5 (enExample) 2005-11-04
JP4104746B2 JP4104746B2 (ja) 2008-06-18

Family

ID=25474702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27855998A Expired - Fee Related JP4104746B2 (ja) 1997-09-30 1998-09-30 自動直接メモリ・アクセス機能を備えたコンピュータ・システム

Country Status (3)

Country Link
US (1) US6128669A (enExample)
EP (1) EP0905629A1 (enExample)
JP (1) JP4104746B2 (enExample)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW386215B (en) * 1997-03-24 2000-04-01 Seiko Epson Corp Emulation system and information processor
US6330631B1 (en) 1999-02-03 2001-12-11 Sun Microsystems, Inc. Data alignment between buses
US6732067B1 (en) * 1999-05-12 2004-05-04 Unisys Corporation System and adapter card for remote console emulation
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US6661794B1 (en) 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6952824B1 (en) * 1999-12-30 2005-10-04 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US6584522B1 (en) 1999-12-30 2003-06-24 Intel Corporation Communication between processors
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US6725315B2 (en) 2000-12-22 2004-04-20 Nortel Networks Limited System and method to efficiently move data from one data bus to another data bus in a network switch
US20030046499A1 (en) * 2001-08-30 2003-03-06 Wen Lin Integrated drive controller for systems with integrated mass storage
US20030097503A1 (en) * 2001-11-19 2003-05-22 Huckins Jeffrey L. PCI compatible bus model for non-PCI compatible bus architectures
US7471688B2 (en) 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7433307B2 (en) 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
US6993598B2 (en) * 2003-10-09 2006-01-31 International Business Machines Corporation Method and apparatus for efficient sharing of DMA resource
US7136943B2 (en) * 2004-03-18 2006-11-14 International Business Machines Corporation Method and apparatus for managing context switches using a context switch history table
JP2006127300A (ja) * 2004-10-29 2006-05-18 Hitachi Global Storage Technologies Netherlands Bv ホストと記憶デバイスとの間における通信方法、記憶デバイス、ホスト、記憶デバイスとホストを備えるシステム
US7917659B2 (en) * 2005-03-02 2011-03-29 Lsi Corporation Variable length command pull with contiguous sequential layout
US7644198B2 (en) 2005-10-07 2010-01-05 International Business Machines Corporation DMAC translation mechanism
US7721023B2 (en) * 2005-11-15 2010-05-18 International Business Machines Corporation I/O address translation method for specifying a relaxed ordering for I/O accesses
US7664213B2 (en) * 2005-11-22 2010-02-16 Sun Microsystems, Inc. Clock alignment detection from single reference
GB2433333B (en) 2005-12-13 2011-07-13 Advanced Risc Mach Ltd Distributed direct memory access provision within a data processing system
CN101237445B (zh) * 2007-01-30 2013-01-02 世意法（北京）半导体研发有限责任公司 缓冲器管理方法和用于缓冲器管理及封装wusb分组的设备
CN102693206B (zh) * 2007-01-30 2015-06-24 世意法（北京）半导体研发有限责任公司 在终点中无线usb同步的缓冲器管理
WO2008149459A1 (ja) * 2007-06-08 2008-12-11 Fujitsu Limited ストレージ装置および制御方法
US7733130B2 (en) * 2008-03-06 2010-06-08 Oracle America, Inc. Skew tolerant communication between ratioed synchronous clocks
US7861024B2 (en) * 2008-09-30 2010-12-28 Intel Corporation Providing a set aside mechanism for posted interrupt transactions
US9026698B2 (en) * 2013-03-15 2015-05-05 Intel Corporation Apparatus, system and method for providing access to a device function
US9778859B2 (en) 2013-09-18 2017-10-03 Western Digital Technologies, Inc. Doorless protocol having multiple queue read requests in flight
US9547472B2 (en) 2013-09-18 2017-01-17 HGST Netherlands B.V. ACK-less protocol for noticing completion of read requests
US10048878B2 (en) 2015-06-08 2018-08-14 Samsung Electronics Co., Ltd. Nonvolatile memory module and storage system having the same
US10977198B2 (en) * 2018-09-12 2021-04-13 Micron Technology, Inc. Hybrid memory system interface
US12131184B2 (en) * 2021-10-29 2024-10-29 Blackberry Limited Thread scheduling including preemption of a thread in a kernel persona
CN114546906B (zh) * 2022-01-28 2023-06-23 郑州信大捷安信息技术股份有限公司 一种基于ring通信机制的数据交互方法和系统
US20240045618A1 (en) * 2022-08-04 2024-02-08 Mediatek Inc. Completion Queue Handling By Host Controller For Storage Device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5050066A (en) * 1988-10-14 1991-09-17 Intel Corporation Apparatus with a single memory and a plurality of queue counters for queuing requests and replies on a pipelined packet bus
DE69032614T2 (de) * 1989-11-03 1999-04-15 Compaq Computer Corp., Houston, Tex. 77070 Verfahren zur Datenverteilung in einer Speicherplattenanordnung
US5386524A (en) 1992-04-16 1995-01-31 Digital Equipment Corporation System for accessing information in a data processing system
US5657471A (en) * 1992-04-16 1997-08-12 Digital Equipment Corporation Dual addressing arrangement for a communications interface architecture
US5487146A (en) * 1994-03-08 1996-01-23 Texas Instruments Incorporated Plural memory access address generation employing guide table entries forming linked list
US5448558A (en) * 1994-04-05 1995-09-05 International Business Machines Corporation Method and apparatus for managing packet FIFOS
US5664223A (en) * 1994-04-05 1997-09-02 International Business Machines Corporation System for independently transferring data using two independently controlled DMA engines coupled between a FIFO buffer and two separate buses respectively
US5687316A (en) * 1994-07-29 1997-11-11 International Business Machines Corporation Communication apparatus and methods having P-MAC, I-MAC engines and buffer bypass for simultaneously transmitting multimedia and packet data
AU703388B2 (en) * 1994-10-31 1999-03-25 Intel Corporation Method and apparatus for exchanging data, status and commands over an hierarchical serial bus assembly using communication packets
US5613162A (en) * 1995-01-04 1997-03-18 Ast Research, Inc. Method and apparatus for performing efficient direct memory access data transfers
US5734847A (en) * 1995-06-15 1998-03-31 Intel Corporation Method and apparatus for enabling intelligent I/O subsystems using PCI I/O devices
SG82563A1 (en) * 1995-07-07 2001-08-21 Sun Microsystems Inc An apparatus and method for packetizing and segmenting mpeg packets
US6519268B1 (en) * 1996-03-07 2003-02-11 Sony Corporation Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure

Similar Documents

Publication Publication Date Title
JPH11175454A5 (enExample)
US5634099A (en) Direct memory access unit for transferring data between processor memories in multiprocessing systems
US5870627A (en) System for managing direct memory access transfer in a multi-channel system using circular descriptor queue, descriptor FIFO, and receive status queue
US20130318285A1 (en) Flash memory controller
US6836829B2 (en) Peripheral device interface chip cache and data synchronization method
US20040107265A1 (en) Shared memory data transfer apparatus
KR20010031430A (ko) 상이한 주파수로 동작하는 버스사이에 전송되는 데이터를버퍼링하는 디바이스 및 방법
US20020184453A1 (en) Data bus system including posted reads and writes
CN102597971A (zh) 具有多个虚拟队列的地址转换单元
CN112948293A (zh) 一种多用户接口的ddr仲裁器及ddr控制器芯片
JPS60142439A (ja) ストアバツフア装置
US5829042A (en) Prefetch operation for network peripheral device having shared memory
US7603496B2 (en) Buffering data during data transfer through a plurality of channels
TWI223153B (en) Memory control for multiple read requests
US5944788A (en) Message transfer system and control method for multiple sending and receiving modules in a network supporting hardware and software emulated modules
TW491970B (en) Page collector for improving performance of a memory
US5745707A (en) Bus control device for computer system having computer and DMA device
JPS62120574A (ja) ベクトル処理装置
JP3824122B2 (ja) Ｄｍａ装置
US20040117565A1 (en) Memory bus interface for use in a peripheral device
EP1607869B1 (en) Data cache system
TW544575B (en) Page organizer within memory controller
US7159084B1 (en) Memory controller
JP3994724B2 (ja) 印刷システム
US20040213054A1 (en) Memory Access System Providing Increased Throughput Rates When Accessing Large Volumes of Data