JPH10320277A - マイクロプロセッサ回路およびシステム - Google Patents

マイクロプロセッサ回路およびシステム

Info

Publication number
JPH10320277A
JPH10320277A JP9301182A JP30118297A JPH10320277A JP H10320277 A JPH10320277 A JP H10320277A JP 9301182 A JP9301182 A JP 9301182A JP 30118297 A JP30118297 A JP 30118297A JP H10320277 A JPH10320277 A JP H10320277A
Authority
JP
Japan
Prior art keywords
data
memory
address
cache
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9301182A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10320277A5 (enExample
Inventor
Steven D Krueger
ディー．クルーガー スチーブン
Jonathan H Shiell
エィチ．シェル ジョナサン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of JPH10320277A publication Critical patent/JPH10320277A/ja
Publication of JPH10320277A5 publication Critical patent/JPH10320277A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP9301182A 1996-10-31 1997-10-31 マイクロプロセッサ回路およびシステム Pending JPH10320277A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2923296P 1996-10-31 1996-10-31
US029232 1996-10-31

Publications (2)

Publication Number Publication Date
JPH10320277A true JPH10320277A (ja) 1998-12-04
JPH10320277A5 JPH10320277A5 (enExample) 2005-07-07

Family

ID=21847956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9301182A Pending JPH10320277A (ja) 1996-10-31 1997-10-31 マイクロプロセッサ回路およびシステム

Country Status (3)

Country Link
EP (1) EP0840232B1 (enExample)
JP (1) JPH10320277A (enExample)
DE (1) DE69727031T2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011148552A1 (ja) * 2010-05-25 2011-12-01 パナソニック株式会社 キャッシュコントローラ及びその制御方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0886216A1 (en) 1997-06-06 1998-12-23 Texas Instruments Incorporated Microprocessor comprising means for storing non-cacheable data
CN115878507B (zh) * 2023-01-19 2023-07-21 北京象帝先计算技术有限公司 系统级芯片的内存访问方法、装置及电子设备
CN115794675B (zh) * 2023-01-19 2023-05-16 北京象帝先计算技术有限公司 写数据方法、装置、图形处理系统、电子组件及电子设备

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382396A3 (en) * 1989-02-08 1991-11-27 Hitachi, Ltd. Program memory buffer for processor
US5561780A (en) * 1993-12-30 1996-10-01 Intel Corporation Method and apparatus for combining uncacheable write data into cache-line-sized write buffers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011148552A1 (ja) * 2010-05-25 2011-12-01 パナソニック株式会社 キャッシュコントローラ及びその制御方法

Also Published As

Publication number Publication date
DE69727031D1 (de) 2004-02-05
EP0840232A3 (en) 1998-11-11
DE69727031T2 (de) 2004-11-25
EP0840232A2 (en) 1998-05-06
EP0840232B1 (en) 2004-01-02

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