JPH10308787A - Communication protocol processing method and processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processing method and a processor which fast execute similar processing without reading a parameter from other memory inside and outside a device at the time of performing processing that accompanies state transition when a communication protocol is processed. SOLUTION: This device retrieves associative memory 12 that holds a current state number 61 of a protocol, a state transition condition 62, the next state 63 of the protocol, a start instruction 64 of processing that accompanies a state transition and a parameter 65 which is needed for processing from the number 61 of the protocol and the condition 62. When the memory 12 is hit, the number 63, the instruction 64 and at the same time, the parameter 65 are read from the memory 12, and an executing circuit performs necessary operations based on it and repeats the operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for processing a communication protocol in a data communication system.

[0002] A conventional communication protocol processing device is composed of a memory storing the contents of communication protocol processing and a microprocessor. In the state transition control of the protocol in such a configuration, when there are a plurality of branch destinations, they are enumerated, and those that match the current state number of the protocol and the state transition condition are sequentially collated to obtain the next state. It has become. Also, depending on the state, it is not always necessary to collate all state transition conditions, so that only necessary information is extracted and collated to obtain the next state. In such a conventional processing device, it is difficult to greatly improve the protocol processing capability because of the process of extracting only necessary information from the state transition and the process of sequentially comparing the current state number with the state transition condition. is there.

A method and an apparatus capable of solving this problem, speeding up the state transition control in the communication protocol processing, and improving the processing capacity are disclosed in Japanese Patent Application No. Hei 7-36920, filed by the inventor of the present invention. No. "Communication protocol processing method and processing apparatus" (Japanese Patent Laid-Open No. 8-237327)
No.).

In the device proposed in this application, an associative memory holding a current state number of a protocol, a plurality of state transition conditions, a next state number of the protocol, and an instruction to start a process associated with a state transition is stored in an associative memory. Searching from the state number and multiple state transition conditions, if the associative memory hits, reads out the next state number of the protocol and the instruction to start processing associated with the state transition from the associative memory, and an execution circuit is required based on this. And these operations are repeated as many times as necessary.

In the invention of Japanese Patent Application No. 7-36920,
Therefore, the next state number of the protocol and the start instruction of the process accompanying the state transition are read from the associative memory. As a result, the process accompanying the state transition is executed in the execution circuit by the start instruction.

[0006]

In the above-mentioned method, it is necessary to read out necessary parameters from another memory inside or outside the apparatus when performing a process accompanying a state transition. There is a problem that the time for reading from the memory is long.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a processing method and a processing apparatus for performing the same processing at a high speed without reading parameters from another memory inside or outside the apparatus when performing processing accompanying a state transition. It is in.

[0008]

According to the communication protocol processing method of the present invention, in order to achieve this object, a current state number of a protocol, a state transition condition, a next state of the protocol, a start instruction of a process accompanying a state transition, and The associative memory holding the parameters required for processing is searched from the current state number of the protocol and the state transition condition, and if the associative memory is hit, the next state number of the protocol and the processing associated with the state transition are retrieved from the associative memory. At the same time as the start instruction, parameters necessary for processing are read out, and the execution circuit performs necessary calculations based on the readout parameters, and repeats these operations.

According to the present invention, it is not necessary to read parameters necessary for processing from another memory inside or outside the apparatus when performing processing accompanying a state transition, so that the time required for reading memory can be reduced. And speed up the processing.

Further, the communication protocol processing device of the present invention is an associative memory holding a current state number of a protocol, a state transition condition, a next state of the protocol, an instruction to start processing associated with the state transition, and parameters required for the processing. A state transition control circuit that retrieves the associative memory from the current state number of the protocol and the state transition condition, and instructs the next state number of the protocol, an instruction to start processing accompanying the state transition, and parameters necessary for the processing, An execution circuit configured by a logic gate and performing an operation or a memory read / write operation in accordance with a start instruction read in accordance with a state transition.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a communication protocol processing device for implementing the present invention. The communication protocol processing device 1 stores the current state number, the state transition condition, the next state number, the start instruction of the processing accompanying the state transition, and the associative memory 12 storing the parameters necessary for the processing, and searches and associates the associative memory 12 from the associative memory 12. The system includes a state transition control circuit 13 for performing reading, and an execution circuit 14 that is activated by a process activation instruction.

The associative memory 12 and the state transition control circuit 13 control a signal line 15 for transmitting and receiving a state number, a signal line 16 for giving a state transition condition to the associative memory 12, and a search / read / write / search range. To the state transition control circuit, and a hit signal line 18 indicating that the content of the relevant memory is stored in the associative memory 12 as a result of the search, and an instruction to start processing as a search result of the associative memory 12. They are connected by a signal line 23 and a signal line 24 for transmitting and receiving parameters required for processing in the execution circuit 14.

The state transition control circuit 13 and the execution circuit 14 are connected to a signal line 19 for giving a start instruction of a process, which is a search result of the associative memory 12, to the execution circuit 14, and the state transition condition generated by the execution circuit 14 Signal line to be provided to the transition control circuit 13
20 and a signal line 25 for transmitting and receiving parameters required for processing in the execution circuit 14.

The state transition control circuit 13 includes a register 31 for storing a current state number, a register 32 for storing a state transition condition,
And search / read / write /
A logic circuit 41 for controlling a search range is provided. Execution circuit 14
Includes a plurality of logic circuits 42 for performing various operations or processing such as reading / writing of a memory.

The state transition control circuit 13 and the external circuit 2 are connected to a signal line for receiving a state transition control condition from the external circuit.
Linked by 21. The execution circuit 14 and the external circuit 2 are connected by a signal line 22 for giving the execution result of the execution circuit 14 to the external circuit 2.

FIG. 2 is a diagram for explaining the contents of the associative memory 12. The associative memory 12 has a current state number 61, a state transition condition 62, a next state number 63,
A plurality of rows of a combination of a start instruction 64 for a process accompanying a state transition and a parameter 65 required for the process are stored. In FIG. 2, S1, S2, S3 are set as the current state number 61 and the next state number 63, a set of Ca, Cb, Cc is set as the state transition condition 62, and * 1, * 2, * are set as the start instruction 64 of the process accompanying the state transition. 3 to * n
Up to P1, P2, P3
To Pn are stored in necessary combinations.

The description on the first line of the associative memory 12 indicates that when the current state number is S1 and the state transition condition is Ca,
This means that the processes * 1, * 2, * 3 are activated and the state transits to the state S2.

FIG. 3 is a flow chart for explaining an example of the communication protocol processing in the case of the device configuration shown in FIGS. Step 101 and Step 10
Step 2 is a step for initializing the associative memory and the state transition control circuit. The current state number and the state transition condition are set in the search range (step 103). Next, the state transition condition is fetched and written into the register 32 (step 104).

If the result of the search of the associative memory based on the contents of the registers 31 and 32 (step 105) results in a hit (the corresponding item is in the associative memory), the start instruction and the processing of the state transition from the associative memory are performed. Are read out and the execution circuit 14 is started (step 10).
6). Processing is performed using parameters necessary for processing in the logic circuit that has received the instruction in the execution circuit (step 107).
). For example, * 1 as an instruction to start a process accompanying a state transition
Is read out, the execution circuit is activated, and the processing is performed by the logic circuit * 1 in the execution circuit. When the completion of the processing is notified (step 108), the processing from step 103 is repeated.

If the result of the search of the associative memory (step 105) is a mishit (the relevant item is not in the associative memory), a mishit process is performed (step 109).
), The processing from step 103 is repeated.

Here, in the process of step 106 in FIG. 3, parameters necessary for the process can be read from the associative memory in addition to the next state number and the instruction to start the process accompanying the state transition.

[0022]

As described above in detail, according to the present invention, it is possible to read out the parameters necessary for performing the processing accompanying the state transition from the associative memory simultaneously with the next state number and the instruction to start the processing. Therefore, it is possible to reduce the time required for reading parameters from another memory, which has been required when performing processing associated with the state transition.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a communication protocol processing device for implementing the present invention.

FIG. 2 is a diagram illustrating the contents of an associative memory.

FIG. 3 is a flowchart for explaining an example of a communication protocol process in the case of the device configuration shown in FIGS. 1 and 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Communication protocol processing apparatus 2 External circuit 12 CAM 13 State transition control circuit 14 Execution circuit 15, 16, 17, 18, 19, 20, 21, 22, 2
3, 24, 25 Signal lines 31, 32, 33 Registers 41, 42 Logic circuit 61 Current state number 62 State transition condition 63 Next state number 64 Start instruction 65 Parameters required for processing

Claims (2)

[Claims] 1. An associative memory holding a current state number of a protocol, a state transition condition, a next state of the protocol, a process start instruction accompanying a state transition, and parameters necessary for the processing are stored in a current state number and a state of the protocol. When the associative memory is hit from the transition condition, the next state number of the protocol and the instruction to start the process associated with the state transition are read from the associative memory, and at the same time, the parameters necessary for the process are read out. A communication protocol processing method which performs necessary operations and repeats these operations. 2. An associative memory holding a current state number of the protocol, a state transition condition, a next state of the protocol, an instruction to start processing associated with the state transition, and parameters required for the processing, and a current state number and state of the protocol. It consists of a state transition control circuit that retrieves the associative memory from the transition conditions and reads the next state number of the protocol, the instruction to start the processing accompanying the state transition, and the parameters required for the processing, and a logic gate. A communication protocol processing device comprising: an execution circuit for performing a calculation or a memory read / write operation in accordance with a start instruction read in conjunction therewith.