JP2783865B2 - Data processing device - Google Patents

Description

The present invention relates to a data driven type data processing device, and more particularly, to a high speed queuing memory which is indispensable as a component of a data driven type data processing device. It relates to the conversion process.

(B) Conventional technology In a data-driven data processing device, operands are handled in a data format called a packet including operand data, a packet destination number (node number), an execution environment identifier (color), and the like.

In such an apparatus, usually, the node number and the color are collectively referred to as a tag, and by searching for two operand packets in which the ducks coincide, an operand pair that can be operated can be detected.

FIG. 3 shows an example of a conventional operand pair detecting device. Hereinafter, a method of detecting a match will be described with reference to FIG.

The coincidence detection mechanism includes a memory 1 usually called a queuing memory, an address generator 2 for generating a queuing memory address from a tag of an operand packet, a comparator 3 for comparing tags, and an operation packet (two operand data An operation packet generator 4 for generating an operation target packet having the operation packet) and a control unit 5 for controlling the entire apparatus.

When the operand packet 6 is input, the address generator 2 generates a queuing address 7 for the memory 1 from the tag of the operand packet 6. If an operand packet is stored at the address of the queuing memory 1 indicated by the queuing address 7, that packet is read. Then, the tag of the read operand packet 8 and the input operand packet 6
Are compared by the comparator 3, and a comparison result signal 9 is sent to the control unit 5. The control unit 5 sends an operation packet generation signal 10 to the operation packet generator 4 if a match is obtained according to the comparison result signal 9, and the operation packet generator 4 generates an operation packet 12. Further, the address of the corresponding memory 1 is deleted.

On the other hand, if the tags do not match because no packet is stored, the control unit 5 sends a packet write signal 11 to the memory 1 and writes the input operand packet 6 in the memory 1.

There are various methods for the operation in the case where a packet whose tag does not match the corresponding address is already stored in the corresponding address.

The above is the outline of the operation of the operand packet queuing mechanism.

(C) Problems to be Solved by the Invention As described above, in the conventional data processing device, since the normal memory mechanism is employed for the waiting memory 1, the processing timing chart of FIG. As shown in the figure, every time a packet arrives, a read memory access for [read / match detection] in a unit period (for example, the Tth cycle) is followed by a [write / erase] for a unit period (for example, the (T + 1) th cycle). ], Two memory accesses of write memory access are required. Therefore,
In such a conventional device, a total of four memory accesses are required to generate an operation packet from two operand packets, respectively, which has been a cause of impeding the speeding up of the packet queuing process. .

(D) Means for Solving the Problems A data processing device according to the present invention provides a queuing memory for a data-driven processor, which is different from a normal memory, in that a memory capable of simultaneously executing reading and writing to different addresses. A mechanism such as a two-port memory.

(E) Function In the data processing device of the present invention, the queuing memory of the data driven processor is constituted by a memory mechanism capable of simultaneously executing reading and writing to different addresses, for example, a two-port memory. Of the two continuous waiting operations, the writing operation of the preceding waiting operation and the next reading operation can be executed simultaneously, and the waiting operation can be performed in a pipeline-like parallel manner.

(F) Embodiment FIG. 1 shows an embodiment of the queuing mechanism of the data driven processor according to the present invention.

The apparatus of this embodiment includes a two-port memory 21, an address generator 22 for generating an address of a waiting memory from a tag of an operand packet, and a comparator 2 for comparing tags.
3, an operation packet generator 24 that generates an operation packet from a pair of operand packets,
Address latch 26 for latching read addresses, packet latch for latching input operand packets
27, a memory latch 28 for latching packets read from the two-port memory 21, and a control device 25 for controlling the whole of them
Consists of

The operation of the two-port memory 21 is shown in FIG. 2, and the operation of the device of the present invention having such a configuration will be described below with reference to FIG.

First, when the operand packet 31 is input, the address generator 22 generates a waiting address 32 for the two-port memory 21 from the tag of the operand packet 31. If the operand packet is stored at the address of the two-port memory 21 indicated by the queuing address 32, the packet is read, for example, in the Tth cycle.

Subsequently, in the T-th cycle, the tag of the operand packet 33 read as described above and the tag of the input operand packet 31 are compared by the comparator 23, and the comparison result signal 34 is sent to the control unit 25. . The read address 32, the input operand packet 31, and the read operand packet 33 are stored in the next write cycle (T + 1
(Cycle), the data is stored in the address latch 26, the packet latch 27 and the memory latch 28, respectively.

As described above, the [read / match detection] process is performed in one cycle, and the [write / erase] is performed in the same cycle.

That is, in the above-described T-th cycle, for example, the control unit 25 outputs the comparison result signal 34 one cycle before (T-1 cycle).
, An operation packet generation signal 36 is sent to the operation packet generator 24 if they match. In the previous cycle, the operation packet generator 24 generates an operation packet 40 from the input operand packet 38 and the read operand packet 37 stored in the packet latch 27 and the memory latch 28, respectively. In addition, a write signal 35 is sent to the two-port memory 21.
To erase the corresponding address of the two-port memory 21 in accordance with the address 39 of the previous cycle stored in the address latch 26.

On the other hand, according to the comparison result signal 34 of the previous cycle, if they match, the control unit 25 sends a write signal 35 to the two-port memory 21 and according to the address 39 of the previous cycle stored in the address latch 26. 2-port memory 21
Then, the input operand packet 38 stored in the packet latch 27 is written at the corresponding address.

As described above, the writing operation of the preceding waiting operation and the next reading operation can be performed simultaneously.

(G) Effects of the Invention According to the present invention, the detection of an operand packet pair and the writing of a packet to a queuing memory in a packet queuing mechanism of a data driven processor can be executed at the same time, so that the packet queuing process is speeded up. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a packet queuing mechanism of a data processing device according to the present invention, FIG. 2 is an operation diagram of the device of the present invention shown in FIG. 1, FIG. 3 is a block diagram of a conventional device, and FIG. FIG. 21: 2-port memory, 22: Address generator,
23 ... Comparator, 24 ... Operation packet generator, 25 ... Control unit.

Claims (2)

(57) [Claims] An operation for executing an operation using two data as operands is performed by detecting that the two operands have been generated and are in a state where the operation is possible, and driving the operation. In a data processing device that waits for an operand by using a memory mechanism, by configuring the memory device with a two-port memory capable of simultaneously reading and writing different addresses, it is possible to detect an operand to be an operation partner. A data-driven data processing device wherein the storage of an operand when a counterpart operand is not present in the memory device is performed simultaneously in a pipeline manner. 2. The memory mechanism is constituted by a two-port memory capable of simultaneously reading and writing different addresses, thereby detecting an operand to be operated and an operation when an operand to be detected is detected. 2. The data driven type data processing device according to claim 1, wherein the contents of the address area of the memory device in which the operand is present are simultaneously erased in a pipeline manner.