JPH03127289A - Data processor - Google Patents

Data processor

Info

Publication number
JPH03127289A
JPH03127289A JP26662389A JP26662389A JPH03127289A JP H03127289 A JPH03127289 A JP H03127289A JP 26662389 A JP26662389 A JP 26662389A JP 26662389 A JP26662389 A JP 26662389A JP H03127289 A JPH03127289 A JP H03127289A
Authority
JP
Japan
Prior art keywords
waiting
packet
memory
write
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP26662389A
Other languages
Japanese (ja)
Other versions
JP2783865B2 (en
Inventor
Masahisa Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP26662389A priority Critical patent/JP2783865B2/en
Publication of JPH03127289A publication Critical patent/JPH03127289A/en
Application granted granted Critical
Publication of JP2783865B2 publication Critical patent/JP2783865B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To increase the packet waiting processing speed by simultaneously executing detection of a pair of operand packets and packet write to a waiting memory in the packet waiting mechanism of a data driven processor.
CONSTITUTION: The waiting mechanism of the data driven processor consists of a 2-port memory 21, an address generator 22, a comparator 23, an operation packet generator 24, a control part 25, an address latch 26, a packet latch 27, and a memory latch 28. Since the waiting memory consists of the two-port memory 21 where read and write of different addresses can be simultaneously executed, the write operation of a preceding waiting operation out of two continuous waiting operations and the read operation of the succeeding waiting operation are simultaneously executed, and waiting operations are executed in parallel by pipeline. Thus, the packet waiting processing speed is increased.
COPYRIGHT: (C)1991,JPO&Japio
JP26662389A 1989-10-13 1989-10-13 Data processing device Expired - Fee Related JP2783865B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26662389A JP2783865B2 (en) 1989-10-13 1989-10-13 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26662389A JP2783865B2 (en) 1989-10-13 1989-10-13 Data processing device

Publications (2)

Publication Number Publication Date
JPH03127289A true JPH03127289A (en) 1991-05-30
JP2783865B2 JP2783865B2 (en) 1998-08-06

Family

ID=17433390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26662389A Expired - Fee Related JP2783865B2 (en) 1989-10-13 1989-10-13 Data processing device

Country Status (1)

Country Link
JP (1) JP2783865B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404558A (en) * 1992-02-17 1995-04-04 Sharp Kabushiki Kaisha Data driven type information processor having a plurality of memory banks

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404558A (en) * 1992-02-17 1995-04-04 Sharp Kabushiki Kaisha Data driven type information processor having a plurality of memory banks

Also Published As

Publication number Publication date
JP2783865B2 (en) 1998-08-06

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees