JPH10308062A - Signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve the burden of a host by effectively utilizing a memory resources when the same user's data of a plurality of sectors continue in data to be recorded in an optical disk. SOLUTION: When the same user's data of plural sectors continue, only user's data of two sectors are transferred to a buffer memory, stored in Nth page and N+1th page, a system controller specifies the number of sector repeat, and issues a repeat start instruction. Receiving the instruction, a sector processor respects to produces alternately the Nth page and the N+1 page checking a CD-ROM coding page register (b), and sector processing of the number of sector repeat (generation and addition of a header) is performed. At this time, in a CD-ROM encoder, interleaving and scrambling processing are performed for pages directly after finishing of sector processing checking a value of a sector processing page register (c).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a signal processing circuit used in an information processing apparatus using an optical disk, and more particularly, to an encoding process when recording information on an optical disk. .

[0002]

2. Description of the Related Art Compact D (CD)
isk), compact disk ROM (CD-ROM) (Com
pact Disk-Read Only Memory), write-once compact disc (CD-R) (Compact Disk-Recordable), CD rewritable (CD-RW) (Compact Disk-Rewritabl)
e), Digital Video Disc (DVD) (Digital Video
When recording data on an optical disk such as Disk)
The signal processing circuit encodes the data to be recorded transferred from the host computer for each predetermined number of bytes, so that encoded data corresponding to the format of the optical disk is created one sector at a time. You. For example, every predetermined number of bytes of data to be recorded,
Q parity code (hereinafter referred to as "ECC code") or C
After generating and adding information such as an RC code, header / subheader information (hereinafter referred to as “header” and “subheader”, respectively), and a sector synchronization signal (hereinafter also referred to as “sync pattern”), a CIRC (Cross Interleave Reed-Solom) is generated.
on Code) and EFM (Eight to Fourteen)
By performing modulation by Modulation, encoded data corresponding to the format of the optical disk is created one sector at a time. Hereinafter, the encoding process when writing data will be described using a CD-R device as an example.

FIG. 1 is a functional block diagram showing a configuration of a CD-R device for writing data on an optical disc such as a CD-R. However, portions unnecessary for the description of the encoding process at the time of data writing are omitted. This CD-
The R device includes a disk recording unit 51, a buffer memory 52, a signal processing circuit 53, a system controller 54, and a host computer 55. The host computer (hereinafter referred to as “host”) 55 is a personal computer (personal computer) or the like, and data to be written to the optical disk is transferred from the host 55 to the signal processing circuit 53 (this transfer data is “CD-ROM format”). User data "). This user data is stored in the buffer memory 52 via the signal processing circuit 53. The signal processing circuit 53 performs an encoding process on the user data stored in the buffer memory 52. The coded data obtained by this is transferred to the disk recording unit 51, where it is recorded on an optical disk. The system controller 54 controls the operation of the signal processing circuit 53 in such encoding processing.

[0004]

As a target of the above-mentioned encoding processing, there is a case where user data having exactly the same content continues for a plurality of sectors. For example, in the case of gap data, data consisting of only "0" continues for a plurality of sectors. However, in the conventional signal processing circuit, user data of a plurality of sectors to be subjected to the encoding process is processed regardless of whether the user data of each sector is the same. Therefore, even when user data having the same content continues for a plurality of sectors in data to be recorded on the optical disk, the user data for each sector is stored in the buffer memory 52 via the signal processing circuit 53. I was

[0005] In recent years, with the improvement of the processing capability of personal computers, there has been a demand for the improvement of the processing capability of CD-R devices as peripheral devices thereof. Processing digital data has become commonplace. In the case of processing at several times the reproduction speed of audio data (1/75 seconds per sector), for example, 8 times, the above encoding process must be performed within 1/600 seconds per sector. There is a demand for an improvement in the processing speed of a signal processing circuit in a CD-R device. In addition, a host computer such as a personal computer is also required to improve a transfer speed when transferring user data to a signal processing circuit. Further, the capacity of the buffer memory tends to increase in order to improve the processing speed of the CD-R device. Therefore, even if user data of the same content continues for a plurality of sectors, the conventional method of storing the data in the buffer memory for each sector results in an increase in the cost of the entire CD-R device. Become.

Therefore, in the present invention, when user data of the same content continues for a plurality of sectors in data to be recorded on an optical disk, the transfer amount of the user data to the buffer memory is reduced, thereby transferring the user data. It is an object of the present invention to provide a signal processing circuit capable of reducing the time and the area occupied by user data in a buffer memory.

[0007]

According to a first aspect of the present invention, there is provided a signal processing circuit comprising: a host for transmitting data to be recorded, which is data to be recorded on an optical disk; A buffer memory for storing data to be recorded, and a signal processing circuit to which a system control unit that issues a control instruction is connected, and the data to be recorded stored in the buffer memory is stored in the buffer memory based on the control instruction. On the other hand, in a signal processing circuit having an encoding unit that performs an encoding process corresponding to the format of the optical disc in units of a sector, when the encoding unit issues a predetermined control command from the system control unit, Based on a predetermined control command, the encoding process is repeatedly performed on the same recording target data stored in the buffer memory in advance. It is characterized by a door.

In the second signal processing circuit according to the present invention, when the predetermined control command is issued in the first signal processing circuit, the recording object from the host is based on the predetermined control command. It is characterized by comprising a data generating means for generating the recording target data and storing the generated data in the buffer memory instead of transmitting the data.

In a third signal processing circuit according to the present invention, in the first or second signal processing circuit, the encoding means generates predetermined information including a sector synchronization signal and header information for each sector, First processing means for creating data obtained by adding the predetermined information to the data stored in the buffer memory for each sector;
A second process of generating encoded data by performing a predetermined encoding process on the data generated for each sector;
Processing means, and when the predetermined control command is issued, based on the predetermined control command, two sectors of first and second data having the same contents stored in the buffer memory in advance. The first processing means alternately generates and adds the predetermined information to the data, and performs the encoding processing by the second processing means on the data immediately after the addition of the predetermined information is completed. , Encoded data is created alternately from the first and second data.

[0010]

According to the first signal processing circuit of the present invention, when data having the same content continues for a plurality of sectors in data to be recorded on the optical disk, the data having the same content is replaced by at least one. By storing a predetermined number of sectors in the buffer memory and issuing a predetermined control command from the system control means, the encoding process is repeatedly performed on the data (the same recording target data) stored in the buffer memory. The encoded data for the data to be recorded for a plurality of sectors is obtained. For this reason, the area occupied by the data to be recorded in the buffer memory is reduced, and the use of memory resources is made more efficient. At this time, the amount of data transferred from the host to be stored in the buffer memory is also reduced, so that the load on the host is also reduced.

According to the second signal processing circuit of the present invention, when data having the same content continues for a plurality of sectors in data to be recorded on the optical disk, the data having the same content is transferred for at least one sector. Since the data can be generated in the signal processing circuit and stored in the buffer memory, the data transfer from the host becomes unnecessary. For this reason, the burden on the host is further reduced as compared with the first signal processing circuit.

According to the third signal processing circuit of the present invention, when data having the same content continues for a plurality of sectors in data to be recorded on the optical disk, the data having the same content is buffered by two sectors. By issuing a predetermined control command from the system control means stored in the memory, the first processing means and the second processing means in the coding means operate in parallel to perform processing for generating and adding predetermined information. A predetermined encoding process is alternately performed on the data of the two sectors. For this reason, it is possible to efficiently generate encoded data for the recording target data of the plurality of sectors while efficiently using the memory resources.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a signal processing circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings.

<Configuration and Operation of CD-R Apparatus> A CD-R apparatus using the signal processing circuit of this embodiment has basically the same configuration as that of the conventional example shown in FIG. A disk recording unit 51, a buffer memory 52, a signal processing circuit 53, a system controller 54, and a host 55 are provided. The operations of these components are basically the same. However, in this CD-R device, when user data having the same content continues for a plurality of sectors in data to be recorded on an optical disk (hereinafter, referred to as “recording target data”), the host transmits data for two sectors. The point that only the user data is transferred to the buffer memory 52 via the signal processing circuit 53 and stored, or that the signal processing circuit 53 generates 0 data for two sectors instead of the host transfer and It differs from the conventional example in that it may be filled in the area. In this CD-R device, in this case, at the start of the encoding process, the system controller 54 issues a repeat start command instead of a normal encoding process command as a control command for the signal processing circuit 53. Is also different from the conventional example.

<Configuration of Signal Processing Circuit of Embodiment> FIG. 2
Is a functional block diagram showing a configuration of the signal processing circuit 53 of the present embodiment. The signal processing circuit 53 includes a host interface unit 11, a buffer management unit 12, a sector processor 13, a CD-ROM encoder 14,
M (Random Access Memory) 15 and CD encoder 16
And a system control interface unit 17. The host interface unit 11 is an interface circuit for transferring data between the host 55 and the signal processing circuit 53. The sector processor 13 outputs a header or the like to the data to be recorded (corresponding to the user data in the CD-ROM format) transferred from the host 55 and stored in the buffer memory 52 for each sector.
Information such as a subheader, a sync pattern, an ECC code, and a CRC code is generated and added. The CD-ROM encoder 14 scrambles and interleaves the data to which the information has been added by the sector processor 13 and develops the data in the RAM 15. The CD encoder 16 applies CI to the data expanded in the RAM 15.
After adding parity and subcode information for C1 and C2 in RC, modulation by EFM is further performed, and the encoded data obtained as a result is output to the disk recording unit 51. The system control interface unit 17 is an interface circuit for the system controller 54,
The system controller 54 controls the operation of the signal processing circuit 53 via the system control interface unit 17. The buffer management unit 12 arbitrates access requests to the buffer memory 52 from each block (the sector processor 13 and the CD-ROM encoder 14) in the signal processing circuit 53, and actually accesses the buffer memory 52. .

FIG. 3A shows data allocation in the buffer memory 52. The area in the buffer memory 52 is
Each page area is divided into 3072 bytes as one page. The page area is associated with the sectors on a one-to-one basis, and access to the buffer memory 52 is managed in page units. For this purpose, the host interface unit 11, the CD-ROM encoder 14, and the sector processor 13 each have a register for storing a page value of a page area in which data to be processed by them is stored.

FIG. 3B shows a structure in one page area in the case of a CD-ROM format, that is, a data structure in one sector. For example, in the case of mode 2 (MODE2) and form 1 (FORM1), one sector has a 12-byte sync pattern, a 4-byte header, an 8-byte subheader, 2048-byte user data, and a 4-byte error detection. CRC code, a 172-byte P code parity (hereinafter referred to as “P parity”), and 1
It consists of a 04 byte Q code parity (hereinafter referred to as “Q parity”). The signal processing circuit 53 performs an encoding process in units of one sector.

<Operation of Signal Processing Circuit of Embodiment> The signal processing circuit of the present embodiment is characterized by an operation when the same user data continues for a plurality of sectors in the data to be recorded. Hereinafter, the operation in this case will be described.

When recording data on an optical disk, first, the host 55 and the system controller 54
To the buffer management unit 12
An access request is issued by designating a page position on the physical memory of the server. In response to this, the buffer management unit 12 stores data transmitted from the host 55 as recording target data in the buffer memory 52. At this time, even if user data having the same content continues for a plurality of sectors in the data to be recorded, in the conventional CD-R apparatus, all the user data for the plurality of sectors is transferred from the host 55 to the buffer memory 52, The data is stored in the corresponding page area, or the system controller fills the corresponding area with data instead of the host transfer (in the case of gap data). However, in the CD-R device using the signal processing circuit 53 of the present embodiment, in this case, the user data of the same content is transferred to the buffer memory 52 for two sectors and stored. For example,
Data consisting of only "0", such as gap data, is 1
Even when the data continues for more than 00 sectors, data consisting of only "0" is stored in the buffer memory 52 for two sectors (two pages). At this time, assuming that "N" is set in a register (hereinafter, referred to as "host page register") for storing a page value of a page area in which data to be processed is stored in the host interface unit 55, the user data Data consisting of only "0" is stored in the Nth page and the (N + 1) th page. At this time, instead of transferring such data from the host 55, in the signal processing circuit 53 (for example, the host interface unit 11), data consisting of only "0" for two sectors is generated and buffered. The information may be stored in the memory 52. In the following, description will be given on the assumption that user data of the same content for two sectors of the data to be recorded is transferred from the host 55 and stored in the Nth page and the (N + 1) th page in the buffer memory 52.

When two sectors of user data having the same contents are stored in the buffer memory 52, the system controller 54 sends information (header, header, and data) to be added to the user data (the Nth and (N + 1) th page user data). Subheader, ECC code, CRC code, sync pattern), ie, whether or not to add a header, what to address information of the header, whether or not to add a subheader, and what to set the value of the subheader , Which mode (mode 1, mode 2, form 1, form 2
) To the signal processing circuit 53 to specify whether to generate an ECC code or a CRC code. After these designations, the system controller 54 issues a repeat start command including the designation of the number of sector repeats to the signal processing circuit 53.
Issue for

Next, the sector processor 13 in the signal processing circuit 53 receives the repeat start command issued from the system controller 54. The sector processor 13 that has received the repeat start instruction operates based on the program stored in its internal memory. Hereinafter, the signal processing circuit 53 when the repeat start instruction is issued
(Hereinafter referred to as "repeat operation") will be described with reference to FIGS. 4 and 5, focusing on the operation of the sector processor. FIG. 4 is a flowchart showing the operation of the sector processor at this time, and FIG. 5 is a flowchart showing the operation of the host interface unit 11, sector processor 13 and CD-ROM encoder 14 at this time.
FIG. 5 is a diagram showing a sequence of access to No. 2 by a page value, and shows a flow of processing in each of these units.

When the sector processor 13 receives the repeat start command, it first checks the value of the host page register to determine whether the transfer of the user data for two sectors has already been completed and these are present in the buffer memory 52. It is determined whether or not it is (step S11 in FIG. 4). When the data transfer to the Nth page and the (N + 1) th page has been completed, the value of the host page register indicates the (N + 2) th or later. When the sector processor 13 determines that there are two sectors (two pages) of user data for which transfer has already been completed exists in the buffer memory 52, the system controller 5 determines whether or not the user data of the page for which transfer has been completed.
4, header, sub-header, EC
Information such as a C code, a CRC code, and a sync pattern is generated, and the generated information is added to a corresponding address of the page area (hereinafter, such generation and addition of information is referred to as “sector processing”) (see FIG. 3 (b)). And
The page value stored in the page value setting register provided in the sector processor 13 (hereinafter referred to as "sector processing page register") is incremented by one, and the processing for one sector is completed. In the case of the repeat operation, this sector processing continues for two pages (step S1).
2, S13). That is, when the user data of two sectors transmitted from the host is stored in the Nth page and the (N + 1) th page of the buffer memory 53 by the host interface unit 11, the sector processor 13 sets the Nth page and the (N + 1) th page. On the other hand, the above processing is continuously performed (FIG. 5)
(A) (b)).

During this time, the CD-ROM encoder 14
First, the page value set in the sector processing page register is checked to determine whether or not the processing of the sector processor 13 has been completed and the sector data has been completed. To facilitate this determination, a second sector processing page register for storing a page value for which sector processing has been completed, as well as a sector processing page register for storing a page value to be processed (or during sector processing). It may be provided in the sector processor 13. When the CD-ROM encoder 14 determines that the sector data is completed, the CD-ROM encoder 14
M15 is developed by performing scrambling and interleaving (FIG. 5C). That is, CD
When the ROM encoder 14 recognizes that the processing of the Nth page by the sector processor 13 has been completed and the sector data has been completed by checking the value of the sector processing page register, the ROM encoder 14 stores the sector data of the Nth page in the RAM.
15 on the N + 1th page by performing scrambling and interleaving, and recognizing that the processing of the (N + 1) th page by the sector processor 13 is completed and that the sector data is completed, the sector data of the (N + 1) th page is converted to R.
The scrambling and interleaving are performed on the AM 15 for development. The CD-ROM encoder 14
Similarly, by checking the value of the sector processing page register, the page for which sector processing has been completed is recognized,
For the data of the page for which sector processing has been completed,
The data is developed by performing scrambling and interleaving on the RAM 15 (FIG. 5C).

When the sector processor 13 completes sector processing for the Nth page and the (N + 1) th page, the CD-
The value of a page value setting register provided in the ROM encoder 14 (a register for storing a page value to be processed by the CD-ROM encoder 14 and hereinafter referred to as a “CD-ROM encoded page register”) is checked. It waits until the value changes from "N" to "N + 1" (step S14). When the sector processor 13 detects that the data of the Nth page has been expanded in the RAM 15 by the CD-ROM encoder 14 and the value of the CD-ROM encoded page register has changed from “N” to “N + 1”, the sector processing page The value of the register is returned to “N”, and the second sector processing is performed on the user data of the Nth page (step S15).

When the second sector processing for the N-th page is completed, the sector processor 13 checks the value of the CD-ROM coded page register, and changes the value of the CD-ROM coded page register from "N + 1" to "N". (Until the processing of the CD-ROM encoder for the (N + 1) th page is completed) (step S17). When detecting that the value of the CD-ROM encoded page register has changed from “N + 1” to “N”, the sector processor 13 sets the value of the sector processing page register to “N + 1”.
To perform the second sector processing on the user data of the (N + 1) th page (step S18).

Thereafter, the sector processor 13 and the CD-RO
The M encoder 14 operates in parallel while interlocking as described above, and repeatedly executes the respective processes on the Nth page and the (N + 1) th page alternately as shown in FIG. Thus, when the CD-ROM encoder 14 finishes expanding the number of sectors corresponding to the number of sector repeats specified at the time of issuing the repeat start instruction into the RAM 15, the repeat operation is completed. In the repeat operation, the sector processor 13 enters a normal operation state after completing the sector processing for the designated number of sector repeats (see steps S16 and S19) (in the example shown in FIG. 5, the N + 2th page is deleted). Process).

During the repeat operation, the CD encoder 1
6 is the same as the case of the normal operation, C is applied to the data expanded on the RAM 15 by the CD-ROM encoder 15.
After adding parity and sub-code information for C1 and C2, coded data is created by further performing EFM modulation, and this is output to the disk recording unit 51.

<Effect> As described above, in the signal processing circuit 53 of the present embodiment, after the user data of the same content is stored in the buffer memory 52 for two sectors (for two pages), the system controller 54 sends the sector repeat data. When a repeat start command specifying a number is issued, the sector processor 13 and the CD-ROM encoder 14 alternately execute the respective processes on the data of the two pages as shown in FIG. The encoding process is performed for the user data of the number of sector repeats. Therefore, if user data of the same content continues for a plurality of sectors in data to be recorded on the optical disc,
Since the encoding process for a plurality of sectors can be performed only by storing the user data for two sectors in the buffer memory 52, the area occupied by the user data in the buffer memory is reduced, and the use of memory resources is made more efficient. You. Further, at this time, the user data transferred from the host 55 to be stored in the buffer memory 52 is only two sectors, so that the load on the host 55 is reduced. At this time, when data for two sectors to be stored in the buffer memory 52 is generated by the signal processing circuit 53, the load on the host is further reduced.

<Modification> In the above embodiment, when user data having the same content continues for a plurality of sectors in the data to be recorded, two of the user data are stored in the buffer memory 52. When the processor 13 and the CD-ROM encoder 14 do not perform the parallel operation as shown in FIG. 5, the encoding process is performed on the data to be recorded only by storing the user data for one sector in the buffer memory 52. be able to.

[Brief description of the drawings]

FIG. 1 shows a C for writing data to an optical disc.
FIG. 2 is a functional block diagram illustrating a configuration of a DR device.

FIG. 2 is a functional block diagram showing a configuration of a signal processing circuit according to an embodiment of the present invention.

FIG. 3 is a CD using the signal processing circuit of the embodiment.
FIG. 3A is a diagram showing data allocation in a buffer memory in the -R device, and FIG. 3B is a diagram showing an example of a data configuration in one sector in the case of a CD-ROM format.

FIG. 4 is a flowchart showing an operation of the sector processor when the signal processing circuit of the embodiment performs a repeat operation.

FIG. 5 is a view showing a sequence of access to a buffer memory by each unit in the signal processing circuit of the embodiment.

[Explanation of symbols]

 11 Host Interface Unit 13 Sector Processor 14 CD-ROM Encoder 17 System Control Interface Unit 52 Buffer Memory 53 Signal Processing Circuit 54 System Controller 55 Host Computer

Claims (3)

[Claims] 1. A signal to which a host for transmitting recording target data, which is data to be recorded on an optical disk, a buffer memory for storing the recording target data, and a system control means for issuing a control command are connected. A signal processing circuit, comprising: an encoding unit that performs an encoding process corresponding to a format of the optical disc on a recording target data stored in the buffer memory in sector units based on the control command. In the above, when a predetermined control command is issued from the system control unit, the coding unit performs the coding on the same recording target data stored in advance in the buffer memory based on the predetermined control command. A signal processing circuit for repeatedly executing a conversion process. 2. The signal processing circuit according to claim 1, wherein when the predetermined control command is issued, the recording is performed instead of sending the recording target data from the host based on the predetermined control command. A signal processing circuit comprising: data generation means for generating target data and storing the data in the buffer memory. 3. The signal processing circuit according to claim 1, wherein the encoding unit generates predetermined information including a sector synchronization signal and header information for each sector, and stores the predetermined information in the buffer memory. First processing means for creating data obtained by adding the predetermined information to the existing data on a sector-by-sector basis; and performing predetermined encoding processing on the data created on a sector-by-sector basis by the first processing means. And a second processing unit for generating, when the predetermined control command is issued, based on the predetermined control command, from the first and second data of the same content stored in advance in the buffer memory. The first processing means alternately generates and adds the predetermined information to the data of two sectors, and immediately after the addition of the predetermined information is completed. A signal processing circuit that performs the encoding process on the data of (i) by the second processing means to generate encoded data alternately from the first and second data.