JPH10303876A - Clock phase synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable operation in low frequency, to make circuit configuration simple and compact and to reduce cost. SOLUTION: A B/U converting part 1 generates RZ unipolar signals S2a and S2b of waveforms on the plus side and minus side of the bipolar signal S1. A latch part 2 respectively receives the RZ unipolar signals S2a and S2b at its SET and RESET terminals and sends out a latch output S3 to regularly change. A frequency dividing part 3 divides the frequency of latch output S3 into 1/14 stages so that a frequency divided output S4 in the same frequency (2 kHz) can be always generated and sent to a phase comparator part 5. A frequency dividing part 6 divides the frequency of clock output signal Sc of 64 kHz from a VCO 4 into 1/32 stages, generates a frequency divided output signal S5 in the same frequency as the output of frequency dividing part 3 and sends it to the phase comparator part 5. The phase comparator part 5 compares the frequency divided output signals S4 and S5 and controls the VCO 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock phase synchronizing circuit, and more particularly to a 64K Codir specified by ITU.
The present invention relates to a clock phase locked loop circuit that generates a 64 kHz clock signal from a bipolar signal for an electrical interface.

[0002]

2. Description of the Related Art ITU-TG. 6 defined by 703
4K Directional Interface
As shown in FIG. 2A, the bipolar signal for use is a bipolar signal that alternates between a positive side and a negative side, and data “1” is represented by a clock signal of 64 kHz, and data “0” is a clock signal of 128 kHz. It is represented by a clock signal. The data is divided into 8-bit data areas, and the polarity of the first data signal in each data area is the same as the polarity of the immediately preceding data signal.

[0003] From such a bipolar signal, 64 kHz
As shown in FIG. 3, a conventional clock phase synchronization circuit that extracts a clock converts a bipolar signal S1 into two columns of RZ unipolar signals S21a and S21b on the plus side and the minus side.
BU converter 21, an oversampling circuit 22 for oversampling RZ unipolar signals S21a and S21b in two columns with an output signal S24 from a VCO (voltage controlled oscillator) 24, RZ unipolar signal S22a, S
Based on 22b, rising and falling edges of a 64 kHz clock pulse indicating data "1" and 128 indicating data "0".
64 for each rising edge of the kHz clock pulse
64 kHz signal generator 23 for generating the kHz signal S23
And a frequency of 128 kHz or more (64 kHz × S) to detect the rise and fall of the 128 kHz clock pulse.
A VCO 24 that oscillates at a frequency twice the frequency, a frequency divider 25 that divides the output signal S24 of the VCO 24 by 1 / S to output a clock output signal Sc of 64 kHz, and a 64 kHz signal S23 that the 64 kHz signal generator 23 outputs. Divider 25
And a phase comparison unit 26 that controls the VCO 24 so that the phase of the output signal coincides with that of the 64 kHz clock output signal Sc.

[0004]

In the above-mentioned conventional example,
In order to detect the rising and falling edges of the 64 kHz clock and the rising edge of the 128 kHz clock pulse included in the bipolar signal and generate a 64 kHz signal, the VCO is oscillated at a frequency higher than twice the frequency of 128 kHz to perform oversampling. For this reason, a high-frequency circuit is required, and the circuit configuration becomes complicated, which causes a problem that the circuit scale becomes large and the cost becomes high when integrated into an integrated circuit.

An object of the present invention is to provide a clock phase synchronizing circuit which can be operated at a frequency lower than that of the conventional example, which simplifies the circuit structure and realizes downsizing and cost reduction.

[0006]

The clock phase synchronization circuit of the present invention is a latch having a set and reset function after generating two columns of RZ unipolar signals having plus and minus waveforms of an input bipolar signal. Department of S
The latch output waveform that is supplied to the ET terminal and the RESET terminal respectively and that changes regularly in each bit within each data area divided by 8 bits is generated, and when this latch output waveform is divided, the same frequency is always generated. The frequency of the latch output waveform is divided by the frequency division ratio that produces the output waveform of the above, the output of the VCO that generates the clock output signal is divided, and a waveform having the same frequency as that of the divided latch output is generated to compare the phases. And V
Control CO. Specifically, a VCO (voltage-controlled oscillator) that outputs a 64 kHz clock signal, a phase comparator that controls the VCO, and means for generating two columns of RZ unipolar signals having plus and minus waveforms of the bipolar signal. A latch section that receives and latches the two columns of RZ unipolar signals at a SET end and a RESET end, respectively, and a first frequency divider that divides the output signal of the latch and divides the output signal to the phase comparator. And a second frequency divider for dividing the output signal of the VCO and sending it to the phase comparator.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation. Here, ITU-TG. 64K Directional Inter specified in 703
The figure shows a case where a clock output signal Sc of 64 kHz is output in response to the face bipolar signal S1.

In FIG. 1, a BU converter 1 converts a bipolar signal S1 into two columns of RZ unipolar signals S2a and S2b on the plus side and the minus side. The latch unit 2
The RZ unipolar signal S2a indicating the change of the positive side of the bipolar signal S1 is received at the SET end, the Q output end is latched at the “H” level when the signal S2a becomes the “H” level, and the bipolar signal S1 Has a function of receiving an RZ unipolar signal S2b indicating a change on the minus side at the RESET terminal, and latching the Q output terminal at an "L" level when the signal S2b becomes an "H" level.

The frequency divider 3 sets the Q output S3 of the latch 2 to 1
The frequency dividing unit 6 divides the output Sc of the VCO (voltage controlled oscillator) 4 oscillating at 64 kHz by 1 / M and sends it to the phase comparing unit 5. The phase comparison unit 5
1 / N frequency division output and 1 / M frequency division output are received and compared,
The VCO 4 is controlled so that the phases match each other. The output signal of the VCO 4 is synchronized with the 64 kHz clock of the bipolar signal S1, and this signal becomes the clock output signal Sc.

Next, the operation will be described.

In FIG. 2, the input bipolar signal S
1 is, for example, the signal shown in FIG.
The RZ unipolar signal S2a output from the U conversion unit 1 has a waveform showing a change on the plus side of the bipolar signal S1 as shown in FIG. 7B, and the RZ unipolar signal S2b is shown in FIG. Like the bipolar signal S1
Has a waveform indicating a change on the minus side of

The output signal S3 of the latch unit 2 is shown in FIG.
As shown in, when the RZ unipolar signal S2a becomes "H" level, it is latched at "H" level, and
When the RZ unipolar signal S2b becomes "H" level, the waveform is latched at "L" level. Output signal S
Looking at the waveform of 3, within the 8-bit data area,
The level changes to the “H” level and the “L” level alternately for each bit, but the “H” or “L” level continues at the boundary of the data area. On the other hand, the output signal Sc of the VCO 14
Is a clock output signal Sc of 64 kHz as shown in FIG.

When the Q output signal S3 of the latch section 2 is divided by 1/14, the output signal S4 of the frequency divider 3 always has the same frequency (frequency 2k) as shown in FIG.
Hz). Accordingly, V
If the output signal Sc of CO4 is divided by 1/32, the frequency divider 6
The output signal S5 of the output signal S5 of FIG. 6 coincides with the output signal S4 of the frequency divider 3, as shown in FIG.

The phase comparison unit 5 compares the phases of the 2 kHz output signal S4 output from the frequency dividing unit 3 and the 2 kHz output signal S5 output from the frequency dividing unit 6, and 64 kHz.
To control the frequency of the VCO 4 oscillating. VCO4 is
A 64 kHz clock output signal Sc synchronized in phase with the 64 kHz clock of the bipolar signal S1 is output. With this configuration, it is possible to operate the clock phase locked loop at a lower frequency than before.

[0016]

As described above, according to the present invention, after two columns of RZ unipolar signals having plus and minus waveforms of an input bipolar signal are generated, a latch unit having a set and reset function is provided. It is supplied to the SET terminal and the RESET terminal respectively, and a latch output waveform that changes regularly for each bit is generated in each data area that is divided in 8-bit units. When this latch output waveform is divided, the same frequency is always generated. The latch output waveform is divided by the division ratio that becomes the output waveform of the VCO, the output of the VCO that generates the clock output signal is divided, and a waveform having the same frequency as the divided latch output is generated to perform phase comparison. By controlling the VCO in such a manner, the VCO can be operated at a lower frequency than in the conventional example, and the circuit configuration can be simplified to achieve a reduction in size and cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the clock phase locked loop circuit shown in FIG.

FIG. 3 is a block diagram showing a conventional clock phase synchronization circuit.

[Explanation of symbols]

 Reference Signs List 1 BU conversion unit 2 Latch unit 3, 6 divider 4 VCO (voltage controlled oscillator) 5 Phase comparator S1 Bipolar signal S2a, S2b RZ unipolar signal S3 Output signal of latch unit 2 S4 Output signal of divider 3 Output signal of S5 frequency divider 6 Sc clock output signal

Claims (4)

[Claims] 1. 64K Codir specified by ITU
64 kHz that receives the bipolar signal for the electrical interface and is phase-locked to this bipolar signal
In a clock phase synchronization circuit for generating a clock signal, a VCO (Voltage Controlled Oscillator) for outputting the 64 kHz clock signal, a phase comparator for controlling the VCO, and two columns of a plus side waveform and a minus side waveform of the bipolar signal are provided. Means for generating an RZ unipolar signal, SE
A latch section that receives and latches the two columns of RZ unipolar signals at a T end and a RESET end, a first divider that divides an output signal of the latch and sends the divided signal to the phase comparator; A second frequency divider for dividing the output signal of the VCO and sending it to the phase comparator. 2. The latch unit latches an output at an “H” level when one of the two columns of RZ unipolar signals supplied to the SET end becomes an “H” level, and the latch unit outputs the output to the RESET end. 2. The clock phase synchronizing circuit according to claim 1, wherein when the other of the supplied two columns of RZ unipolar signals is at "H" level, the output is latched at "L" level. 3. The first frequency division section divides the output waveform of the latch section by a frequency division ratio that always provides an output waveform of the same frequency, and the second frequency division section , The first
V so that the waveform has the same frequency as the output of the frequency divider.
2. The clock phase locked loop circuit according to claim 1, wherein the output of the CO is divided. 4. The clock phase synchronization circuit according to claim 3, wherein said first frequency divider divides frequency by 1/14 and said second frequency divider divides frequency by 1/32.