JPH10303228A - Compressively bonded semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To absorb dispersion in height of a contact surface and reduce heat resistance and electric resistance in a contact interface by applying a metallic powder sintering layer or a metallic flake sintering layer to at least one surface of compressively bonded surfaces in opposition to each of a main electrode board and an intermediate electrode board. SOLUTION: A first main electrode 2 is formed in a first main surface of a wafer 1, a second main electrode 3 is formed in a second main surface, and intermediate electrode boards 4, 5 consisting of Mo and W are arranged in both the electrode surfaces. A pair of main Cu electrode boards 6, 7 are arranged in an outside part of the intermediate electrode boards 4, 5 and pressurized at once, thus bringing each of members into contact with each other. In the state, metallic powder sintering layers or metallic flake sintering layers 8, 9 are applied to at least one surface of compressively bonded surfaces in opposition to the main electrode boards 6, 7 and the intermediate electrode boards 4, 5. When a pressing force is applied in the state, the metallic powder sintering layers or the metallic flake sintering layers 8, 9 are compressed and deformed, and good contact between both the two surfaces is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type semiconductor device, and more particularly, to a thermal resistance between a semiconductor element and a package electrode.
The present invention relates to a pressure contact type semiconductor device capable of reducing electric resistance and ensuring uniform contact.

[0002]

2. Description of the Related Art The technology of power electronics, which controls the main circuit current by making full use of the technology of semiconductor electronics, has been applied in a wide range of fields, and its application is being expanded. Thyristors, optical thyristors, gate turn-off thyristors (GT)
O), an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) or a MOS field effect transistor (hereinafter abbreviated as MOSFET) which are MOS control devices.
In these devices, a main electrode (cathode, emitter electrode) is mainly formed on a first main surface of a semiconductor chip, and another main electrode (anode, collector electrode) is formed on a second main surface side.

In a high-power semiconductor device such as a GTO or an optical thyristor, elements are packaged for each wafer. The two main electrodes of the above-mentioned element are structured to be brought into pressure contact with a pair of external main electrodes of the package via a heat buffer electrode plate made of Mo or W. In order to improve the uniformity of the switching operation and the breaking characteristics of large currents, it is necessary to make the contact state between the above-mentioned element electrode, thermal buffer plate and external main electrode as uniform as possible, and to lower the contact thermal resistance and electric resistance. is important.

For this reason, generally, measures are taken to increase the processing accuracy (flatness, flatness) of package components to reduce warpage and undulation. Further, with respect to the contact thermal resistance between metals, it is known that the contact thermal resistance increases as the roughness of the contact surface increases. Conventionally, from this viewpoint, countermeasures have been promoted as a method of reducing the contact thermal resistance and the electric resistance in a direction of reducing the surface roughness as much as possible.

On the other hand, in IGBTs and the like, a plurality of chips have been mounted so far mainly in a package form of an electrode connection system using wires, which is called a module type structure. In the case of such a modular package, heat generated inside the element is released only from one side of the package, that is, only from the collector side directly mounted on the metal base, so that the thermal resistance is generally large and can be mounted in one package. The number of chips (calorific value or current capacity) was limited.

Recently, in order to cope with such a problem and respond to a demand for a large capacity, a plurality of IGBT elements proposed in Japanese Patent Application Laid-Open No. 8-88240 and the like are formed in a flat type similar to a GTO package. A multi-chip parallel type pressure contact structure in which the emitter electrode and collector electrode formed on the main surface of the package are brought into surface contact with a pair of external main electrode plates provided on the package side, respectively, and pulled out in parallel in the package. Semiconductor devices are receiving attention. In this multi-chip parallel type pressure contact type semiconductor device, there is an unavoidable variation in height at each chip position due to a variation in member dimensions, which results in a problem in that the pressure is different for each chip and uniform contact cannot be obtained. there were. To cope with this problem, Japanese Patent Application Laid-Open No. 8-88240 discloses a method of interposing a thickness correcting plate made of a ductile soft metal sheet such as Ag.

[0007]

In a package such as the above-mentioned GTO, the element size (wafer size) has been increased in order to increase the capacity in the future. Parts) tend to increase.

[0008] There is a limit in the processing to increase the processing accuracy (flatness, flatness) of the package parts as described above to reduce warpage and undulation, and to further reduce the surface roughness. The problem in terms of aspect is also great. Therefore, it has become increasingly difficult to ensure uniform contact between the wafer and package components (electrodes) over the entire element size (wafer size), and to reduce thermal resistance and electrical resistance.

On the other hand, the above-described method of sandwiching a soft metal sheet disclosed as a method for coping with the problem of uniform contact between chips in a multi-chip parallel type pressure contact type semiconductor device is as follows.
According to the study of the present inventors, at least in a practical pressure range where the semiconductor chip is not destroyed, the deformation amount is very small (only deformation due to elastic deformation), and the height between the chips (and the intermediate electrode member sandwiching the chip is reduced). It was found that when the variation in height included was large, the thickness variation absorption capacity was insufficient. When applying pressure in the thickness direction to the soft metal sheet surface to cause plastic deformation in the horizontal direction, the frictional force (friction resistance) generated at the interface between the soft metal sheet and the electrode member sandwiches the soft metal material. Is considered to be due to the fact that the deformation resistance in the lateral direction becomes extremely large. Even if the pressing force is increased for deformation, the plastic deformation does not easily occur because the frictional force also increases in proportion to the pressure. Especially when the thickness is very small compared to the area receiving the resistance like the sheet shape, the influence of the frictional force generated on this surface becomes dominant, so it exceeds the yield stress of commonly known materials Even if pressure is applied, practically no plastic deformation (flow) occurs, and the thickness of the soft metal sheet hardly changes. With the present invention, as described above, with the enlargement of the package due to the increase in the diameter of the wafer, and the parallelization of multiple chips of elements corresponding to the increase in capacity, the uniform pressure contact state in a large area, which becomes increasingly difficult An object of the present invention is to provide a method for securing, that is, a method capable of absorbing variations in the height of the contact surface (due to warpage, undulation, variations in member dimensions, etc.) and reducing thermal resistance and electrical resistance at the contact interface.

[0010]

SUMMARY OF THE INVENTION The object of the present invention is to provide a semiconductor device having a first main electrode on at least a first main surface and a second main electrode on a second main surface. Further, in a pressure-contact type semiconductor device in which these are incorporated between a pair of main electrode plates, at least one surface of the main electrode plate and the intermediate electrode plate facing each other, or two main surfaces of the intermediate electrode plate pressed against each other. Can be realized by applying a metal powder sintered layer or a metal flake sintered layer to at least one of the above.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an example in which the present invention is applied to the basic structure of a press contact type semiconductor device. In a pressure-contact type semiconductor device, a first main electrode 2 is formed on a first main surface of a semiconductor chip or a wafer 1, and a second main electrode 3 is formed on a second main surface.
Intermediate electrode plates 4 and 5 made of Mo or W are arranged on these two electrode surfaces. Further, a pair of C is provided on the outer portion of the intermediate electrode plate.
The main electrode plates 6 and 7 of u are arranged and pressurized at once to bring the members into contact with each other. In the present invention, among the interfaces formed in this mode, at least one of the surfaces of the main electrode plates 6 and 7 and the intermediate electrode plates 4 and 5 pressed against each other is provided with a metal powder sintered layer or a metal flake. Sintered layers 8, 9
Is performed.

In FIG. 1, at the interface between the upper main electrode 6 and the intermediate electrode 4, a metal powder sintered layer or a metal flake sintered layer 8 is applied only to the surface of the intermediate electrode 4, and the lower main electrode 7 An example in which a metal powder sintering layer or a metal flake sintering layer 9 is provided at the interface between the metal electrode and the intermediate electrode 5 is shown.

When a pressing force is applied in this state (shown below), the metal powder sintered layers or metal flake sintered layers 8, 9 of the intermediate electrode plates 4, 5 are compressed and deformed, and the main electrode plates 6, 7 are deformed. And good contact between the two surfaces is completed.

FIG. 2 is a model diagram showing the process of the sintered metal powder layer or the sintered metal flake layer. In FIG.
(A) shows a contact state before pressurization, (b) shows a state in the middle of pressurization, and (c) shows a state in which pressurization has caused sufficient deformation.

FIG. 3 shows the amount of deformation in the thickness direction of the sintered metal powder layer when the sintered metal powder layer and the main electrode plate are brought into pressure contact, that is, the amount of change in height, electric resistance, and pressing force. The relationship was shown.

According to FIGS. 2 and 3, as shown in FIGS. 2 and 3 (a), the metal powder sintered layers or metal flake sintered layers 8, 9 are brought into contact with the main electrode plates 6, 7, respectively. It is in the state that it is.
In this state, the amount of deformation in the thickness direction of the metal powder sintered layer or the metal flake sintered layer is small, and the electric resistance is high.

When a load is applied between the sintered metal powder layers or sintered metal flake layers 8 and 9 and the main electrode plates 6 and 7, as shown in FIGS. Since the load concentrates on the portion in contact with 7 and the pressure becomes extremely high, the metal powder sintered layer or the metal flake sintered layers 8 and 9 easily start compressive deformation. As a result, the metal powder sintered layers or metal flake sintered layers 8, 9 which have started to be deformed are filled with the voids in the metal powder sintered layers or metal flake sintered layers 8, 9 while the main electrode plates 6, 7 are being filled. The contact interface with increases.
The contact interface formed at this time is in a state of very close contact. With this change, the distance between the two becomes shorter, the height of the metal powder sintered layer or the metal flake sintered layer decreases, and the contact interface increases, so that the electric resistance decreases.

Ultimately, the metal powder sintered layer or the metal flake sintered layer is sufficiently deformed, and as shown in FIGS.
To reach the state shown in. In principle, if an infinite load is applied, it is possible to deform to a state where the interface is completely buried, but in reality the load is limited and the metal powder sintered layer or metal flake sintered layer is spherical or Because of the flake shape, it cannot be completely filled, and some unfilled portions 10 remain, but there is no problem in electrical resistance and the like.

Also, the results of measurement of the thermal resistance show almost the same behavior as the electrical resistance. By default,
The amount of deformation in the thickness direction of the metal powder sintered layer or metal flake sintered layer is small, and the thermal resistance is high. In the deformation region of the metal powder sintered layer or metal flake sintered layer, as the amount of deformation increases, the contact interface increases, and the deformation increases and the oxide film on the metal surface is broken, resulting in a new surface. Good contact is obtained, and the thermal resistance is reduced. In a region where the metal powder sintering layer or the metal flake sintering layer was sufficiently deformed, the value of the thermal resistance exhibited the almost constant lowest value.

As described above, the most suitable metal powder sintering layer or metal flake sintering layer is determined depending on whether the thermal resistance, the electrical resistance, or the deformability is to be prioritized, depending on the usage of the semiconductor device. It is preferable to select the amount of deformation in the thickness direction. Actually, since warpage and undulation cannot be avoided on the entire electrode surface, it is necessary to have sufficient deformability to ensure good contact in a form including these.

The surface on which the metal powder sintering layer or the metal flake sintering layer is applied may be either one of the opposing electrode surfaces or both.

FIG. 4 shows an intermediate electrode plate having a sintered metal powder layer or a sintered metal flake layer formed by bonding. The adhesion of the metal powder sintering layer or metal flake sintering layer 8 to the intermediate electrode plate 5 by bonding is to prevent the metal powder or metal flakes 36 from dropping and to eliminate short circuits.

The optimum value and method of the sintered metal powder layer or the sintered metal flake layer are determined according to the required thermal resistance, electrical resistance and height change. The sintered material is made of soft metal such as gold, silver, copper, aluminum or solder.
In particular, it is preferable because deformation easily occurs.

Applying a metal powder sintered layer or a metal flake sintered layer to the intermediate electrode plate is particularly effective when a plurality of semiconductor chips are incorporated in parallel in the above-mentioned press-fit type package. This is suitable for the case where it is necessary to increase the change in In the process of assembling the semiconductor device or in the final process, if the semiconductor chip and the intermediate electrode plate are stacked on the common electrode plate and the package is pressed at room temperature or while heating, the height variation between the chip positions can be absorbed. Thus, the metal powder sintered layer or the metal flake sintered layer is plastically deformed such that the upper surfaces of the respective semiconductor chips are parallel and at the same height, and a uniform contact state can be realized. in this case,
The thickness of the metal powder sintering layer or the metal flake sintering layer must be in a range that can absorb the height variation between the positions of the plurality of semiconductor chips.

FIG. 5 shows an example applied to GTO. The semiconductor element substrate 10 is made of silicon (Si) and has at least one PN junction inside. The semiconductor element substrate 10 has a cathode electrode and a gate electrode made of aluminum (Al) formed on one main surface, and an anode electrode made of aluminum (Al) formed on the other main surface. An intermediate electrode plate 1 made of molybdenum (Mo) is provided above the cathode electrode and the anode electrode, respectively.
1 and 12 were arranged. This intermediate electrode plate is provided with Ag powder sintered layers 13 and 14 on one side with a thickness of 0.3 mm.

Further, the whole of the intermediate electrode plates 11 and 12 was pressed from outside the Ag powder sintered layers 13 and 14 using a pair of external electrodes 15 and 16 made of copper (Cu). A cap member 17 is disposed on a side surface of the semiconductor element substrate 10. A part of a gate lead 18 is arranged in contact with the gate electrode on the semiconductor substrate, and a part thereof is formed by a gate insulator 19 and a disc spring 20.
Is pressed against the gate electrode. All of the above parts are arranged in a security package surrounded by an insulator 21, a pair of external electrodes 15 and 16, and a flange 22. The other end of the gate lead 18 is provided via a seal structure.
It is led out of the insulator 21 as a gate terminal.

Intermediate electrode plate 1 provided with Ag powder sintered layer 14
As a result of measuring the on-voltage under the condition that the pressing force between the electrode 2 and the main electrode plate 16 was about 1 kg / mm ² , a normal Mo intermediate electrode (Rmax
1 μm, Ra 0.1 μm).
0% could be reduced. Thermal resistance was also reduced by about 30%.

FIG. 6 shows a flywheel diode (F) connected in anti-parallel with a switching device using IGBT23.
This shows an example in which the present invention is applied to a reverse conduction type switching device incorporating WD) 24. FIG. 5 shows a partial cross section from the outermost part of the press-contact type semiconductor device at the right end to the middle toward the center. The IGBT chip 23 has an emitter electrode formed on almost the entire first main surface on the upper surface side and a collector electrode on the second main surface on the lower surface side, and further has a control electrode (gate electrode) on the first main surface. Are formed.

In the FWD 24, an anode electrode is formed on the upper surface side of the silicon substrate, and a cathode electrode is formed on the lower surface side. On each of these semiconductor chips, intermediate electrodes 25 and 26 made of Mo for both heat dissipation and electrical connection are fixed in contact with each main electrode on the chip, and these are further connected to a first common main electrode plate. 27 (Cu) and the second common main electrode plate 28 (Cu). The surface in contact with the common main electrode 28 of the intermediate electrode 26 is provided with an Ag powder sintered layer 35. Incidentally, the surface of the common main electrode 27 which is in contact with the intermediate electrode 25 is processed with Rmax of 1 μm. The semiconductor chip and the intermediate electrode are fixed to each other by a Teflon frame 29. A wire is drawn out from the gate electrode of the IGBT chip 23 by a wire bond 30, and further connected to a gate electrode wiring board 31 formed on the common main electrode 28. In addition to this embodiment, it is of course possible to use a spring pin or the like for forming the gate wiring. The space between the pair of common main electrode plates 27 and 28 is externally insulated by an insulating outer cylinder 32 made of ceramic or the like, and the space between the common main electrode plates 27 and 28 and the insulating outer cylinder 32 is inside the package by a flange 33. Is hermetically sealed. The gate electrode wiring is drawn out of the package by a sealed wiring 34 penetrating the outer cylinder 32.

Then, the ON voltage was measured with the applied pressure between the intermediate electrode plate and the main electrode plate being 1 kg / mm ² , and as a result, it was found that the ON voltage was smaller than the case where the intermediate electrode provided with the Ag powder sintered layer 14 was used. A 30% reduction was achieved. Thermal resistance was also reduced by about 20%.

As the material for the intermediate electrode, a material having a thermal expansion coefficient between that of Si and the external main electrode material and having good thermal conductivity and electric conductivity is used. Specifically, tungsten
Metal such as (W) and molybdenum (Mo), or Cu-W, Ag-W, Cu-M using them as main constituent materials
o, Ag-Mo, Cu-FeNi or other composite materials or alloys, and further, composite materials of metals and ceramics or carbon, such as Cu / SiC, Cu / C, Al / SiC,
Al / AlN and the like are preferable.

The sintered metal powder layer or the sintered metal flake layer formed on the intermediate electrode has a required thermal resistance, electrical resistance,
The optimum value and method are determined according to the height change amount. The sintering material is made of a soft metal such as gold, silver, copper, aluminum, or solder, and is particularly preferable because it easily deforms.

On the other hand, it is preferable to use copper or aluminum having good electrical conductivity and thermal conductivity, or the above-mentioned alloy or composite material containing them for the main electrode. If the surface of the main electrode in contact with the metal powder sintered layer or metal flake sintered layer is roughened, the contact between the main electrode and the metal powder sintered layer or metal flake sintered layer is further improved, and the thermal resistance and electric resistance are reduced. Become.

In the present invention, the metal powder sintered layer or the metal flake sintered layer is formed on the intermediate electrode by applying a paste containing the metal powder or the metal flake on the intermediate electrode and drying the paste.
The thermocompression bonding is performed within a range where the metal powder or the metal flakes are not crushed, and the metal powder or the metal flakes are joined together, and the intermediate electrode and the metal powder or the metal flakes are joined.

In the present invention, not only a metal powder sintering layer or a metal flake sintering layer is formed on the entire surface of the intermediate electrode, but also a patterned metal having various shapes depending on necessary heat resistance, electric resistance and height change. A powder sinter layer or a metal flake sinter layer can be formed.

The mounting method of the present invention can of course be used for a pressure contact type semiconductor device consisting of only a switching semiconductor such as an IGBT without a diode. For example, a large number of diode chips alone can be used in a pressure contact type package by the above method. Implementation is of course also effective. In the above embodiment, GTO,
Although the present invention has been described using an IGBT, the present invention is intended for general semiconductor devices having at least a first main electrode on a first main surface and a second main electrode on a second main surface, and is an insulated gate transistor other than an IGBT. (MOS transistor), IG
The present invention can be similarly applied to a semiconductor element with a control electrode such as an insulated gate thyristor (MOS controlled thyristor) including a CT (Insulated Gate Controlled Thyristor) and a diode. In addition, SiC other than the Si element,
It is similarly effective for compound semiconductor devices such as GaN.

In the pressure contact type semiconductor device of the present invention, a stable contact interface between the electrodes can be obtained even when the size is increased, so that a semiconductor device having a small electric resistance and a small thermal resistance can be obtained. Therefore, by using this press-contact type semiconductor device, the converter volume,
In addition, a large-capacity converter whose cost is greatly reduced can be realized. Further, according to the present invention, uniform contact can be obtained even with a lower pressing force than in the prior art, so that the stack structure and the like can be simplified.

The pressure-contact type semiconductor device of the present invention is not particularly limited to the above example, and is particularly suitable for a self-excited large-capacity converter used in a power system and a large-capacity converter used as a converter for a mill.
Variable speed pumped storage power generation, substation facilities in buildings, substation facilities for railways,
It can also be used in converters for sodium-sulfur (NaS) battery systems and vehicles.

[0040]

According to the present invention, uniformity over a large area becomes increasingly difficult with the increase in the size of the package due to the increase in the diameter of the wafer and the parallelization of elements corresponding to the increase in the capacity. Pressure welding can be easily realized with relatively low pressure, that is, it absorbs variations in the height of the contact surface sufficiently,
In addition, the thermal resistance and electric resistance at the contact interface can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a basic configuration of the present invention.

FIG. 2 is a cross-sectional model diagram showing a microscopic shape of an electrode interface.

FIG. 3 is a view for explaining the relationship between the amount of deformation in the thickness direction of the sintered metal powder layer and the electrical resistance and the pressing force.

FIG. 4 is a diagram showing an embodiment of the present invention applied to a GTO.

FIG. 5 is a diagram showing an embodiment of the present invention applied to an IGBT.

FIG. 6 is a diagram showing an embodiment of the present invention applied to a reverse conduction type switching device.

[Explanation of symbols]

1. Semiconductor chip or wafer, 2, 3 ... Main electrode,
4, 5, 11, 12, 25, 26 ... intermediate electrode plate, 6, 7
... Main electrode plate, 8, 9, 13, 14, 35 ... Metal powder sintered layer, 10 ... Semiconductor element substrate, 15, 16 ... External electrode, 1
7 cap material, 18 gate lead, 19 gate insulator, 20 disc spring, 21 insulator, 22, 33 flange, 23 IGBT, 24 flywheel diode, 27, 28 common main electrode plate , 29 ... Teflon frame, 3
0: wire bond, 31: gate electrode wiring board, 32: insulating outer cylinder, 34: airtight through wiring, 36: metal powder, 37 ...
Vacancy.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 652Q

Claims (3)

[Claims] An intermediate electrode plate is disposed on each of the main surfaces of a semiconductor device having a first main electrode on a first main surface and a second main electrode on a second main surface. In the pressure-contact type semiconductor device incorporated between the plates, at least one surface of the main electrode plate and the intermediate electrode plate that are pressed against each other is provided with a metal powder sintered layer or a metal flake sintered layer. A pressure-contact type semiconductor device. 2. An intermediate electrode plate is disposed on each main surface of a semiconductor device having a first main electrode on a first main surface and a second main electrode on a second main surface. A press-contact type semiconductor device incorporated between plates, wherein at least one of two main surfaces of the intermediate electrode plate is provided with a metal powder sintered layer or a metal flake sintered layer. 3. The pressure-contact type semiconductor device according to claim 1, wherein the intermediate electrode plate is a composite material in which a sintered metal powder layer or a sintered metal flake layer is bonded onto the intermediate electrode plate. .