JPH11186299A - Pressure-contact semiconductor device and power converter provided therewith - Google Patents

Pressure-contact semiconductor device and power converter provided therewith

Info

Publication number
JPH11186299A
JPH11186299A JP34754397A JP34754397A JPH11186299A JP H11186299 A JPH11186299 A JP H11186299A JP 34754397 A JP34754397 A JP 34754397A JP 34754397 A JP34754397 A JP 34754397A JP H11186299 A JPH11186299 A JP H11186299A
Authority
JP
Japan
Prior art keywords
main
semiconductor device
soft metal
electrode plate
contact type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34754397A
Other languages
Japanese (ja)
Inventor
Hironori Kodama
弘則 児玉
Mitsuo Kato
光雄 加藤
Mamoru Sawahata
守 沢畠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP34754397A priority Critical patent/JPH11186299A/en
Publication of JPH11186299A publication Critical patent/JPH11186299A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62Protection against overvoltage, e.g. fuses, shunts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10272Silicon Carbide [SiC]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]
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    • H01L2924/1301Thyristor
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
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    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

PROBLEM TO BE SOLVED: To provide a method of keeping a uniform contact between a semiconductor device and electrodes in a pressure-contact semiconductor device and lessening the thermal resistance and electrical resistance. SOLUTION: Semiconductor devices 1 each provided with a first main electrode on its first main surface and a second main electrode on its second main surface are arranged in an array and built inside a flat package insulated from the outside by an insulating sheath and located between a pair of electrode plates 4 and 5 for the formation of a pressure-contact semiconductor device, wherein fine wires formed of soft metal or its assembly 6 is arranged between the semiconductor device 1 and the electrodes of the common electrode plates 4 and 5 or between the intermediate electrodes 2 and 3 arranged on the main surfaces of the semiconductor device 1 and the common electrode plates 4 and 5 respectively.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、加圧接触型半導体
装置に係り、特に半導体素子とパッケージ電極間の均一
な接触状態を確保し、かつ熱抵抗,電気抵抗を低減でき
る加圧接触型半導体装置、及びこれを用いた変換器に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type semiconductor device, and more particularly to a pressure contact type semiconductor device which can ensure a uniform contact state between a semiconductor element and a package electrode and can reduce heat resistance and electric resistance. The present invention relates to a device and a converter using the same.

【0002】[0002]

【従来の技術】半導体エレクトロニクスの技術を駆使し
て主回路電流を制御するパワーエレクトロニクスの技術
は、幅広い分野で応用され、さらにその適用拡大がなさ
れつつある。特に近年、MOS構造ゲートへの入力信号
により主電流を制御するMOS制御デバイスである絶縁
ゲート型バイポーラトランジスタ(以下IGBTと略す)
やMOS型電界効果トランジスタ(以下MOSFETと略す)
などが注目され、例えばIGBTは、パワースイッチン
グデバイスとしてモータPWM制御インバータの応用な
どに幅広く使われている。
2. Description of the Related Art The technology of power electronics, which controls the main circuit current by making full use of the technology of semiconductor electronics, has been applied in a wide range of fields, and its application is being expanded. In particular, in recent years, an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) which is a MOS control device that controls a main current by an input signal to a MOS structure gate
And MOS type field effect transistor (hereinafter abbreviated as MOSFET)
For example, IGBTs are widely used as power switching devices in applications such as motor PWM control inverters.

【0003】従来、IGBTでは主にモジュール型構造
と呼ばれる、ワイヤによる電極接続方式のパッケージ形
態により複数個のチップを実装していた。このようなモ
ジュール型パッケージの場合、素子内部で発生した熱は
パッケージの片面(ワイヤ接続しない面)、すなわちベ
ース基板上に直接マウントした電極側のみから逃がすこ
とになるため、一般に熱抵抗が大きく、一つのパッケー
ジに実装できるチップ数(発熱量,電流容量、または実
装密度)に制限があった。
Conventionally, in an IGBT, a plurality of chips are mounted mainly in a package form of an electrode connection system using wires, which is mainly called a module type structure. In the case of such a module-type package, heat generated inside the element is released only from one side of the package (the side not connected to the wire), that is, only from the electrode side directly mounted on the base substrate. The number of chips (heat generation, current capacity, or mounting density) that can be mounted on one package is limited.

【0004】最近、このような問題に対処し、さらに大
容量化の要求に応えるため、多数のIGBTチップを圧
接型のパッケージ内に組み込み、その主面に形成された
エミッタ電極,コレクタ電極をそれぞれパッケージ側に
設けた一対の外部共通電極板に面接触させて引き出すよ
うにした多チップ並列型加圧接触構造の半導体装置が注
目されている。この圧接型パッケージ構造によれば、上
記のモジュール型パッケージに比べて、1)半導体チッ
プを両面から冷却ができるので冷却効率を上げることが
できる、2)接続導体のインダクタンス、及び抵抗が小
さくなる、3)主電極の接続がワイヤボンドでなくなる
ために接続信頼性が向上する、等の改善がはかれる。
Recently, in order to cope with such a problem and to meet a demand for a larger capacity, a large number of IGBT chips are incorporated in a press-fit type package, and an emitter electrode and a collector electrode formed on the main surface thereof are respectively provided. Attention has been paid to a semiconductor device having a multi-chip parallel-type pressure contact structure in which a pair of external common electrode plates provided on the package side are brought into surface contact with each other and drawn out. According to this press-fit type package structure, 1) the semiconductor chip can be cooled from both sides, so that the cooling efficiency can be increased, and 2) the inductance and resistance of the connection conductor can be reduced as compared with the above-mentioned module type package. 3) Connection reliability of the main electrode is improved because the connection of the main electrode is no longer a wire bond.

【0005】ところが、この多チップ並列型の圧接型半
導体装置では、部材寸法ばらつきに起因するチップ位置
毎の高さのばらつきや共通電極板のそりやうねりによる
場所毎のばらつきが避けられず、これによりチップ毎に
加圧力が異なり均一な接触が得られない、すなわち熱抵
抗,電気抵抗がチップ位置毎に大きく異なり、全体とし
ての素子特性が安定しないという大きな問題があった。
最も単純には、寸法の厳密に揃った部材を用いることで
対処できるが、部品のコスト、および選別のコスト等の
アップが避けられない。この問題に対して、特開平8−8
8240号公報においては、Agなどの延性のある軟金属シ
ートを厚さ補正板として介在させる方法を開示してい
る。
However, in this multi-chip parallel type pressure contact type semiconductor device, variations in height at each chip position due to variations in member dimensions and variations in locations due to warpage or undulation of the common electrode plate are inevitable. As a result, there is a large problem that the pressing force varies from chip to chip and uniform contact cannot be obtained, that is, thermal resistance and electric resistance vary greatly from chip position to chip position, and the element characteristics as a whole are not stable.
In the simplest case, it is possible to cope with the problem by using members having strictly uniform dimensions. However, it is unavoidable to increase the cost of parts and the cost of sorting. To solve this problem,
No. 8240 discloses a method in which a ductile soft metal sheet such as Ag is interposed as a thickness correction plate.

【0006】[0006]

【発明が解決しようとする課題】上記多チップ並列型の
加圧接触型半導体装置におけるチップ間の均一接触の問
題に対処する方法として開示されている前述の軟金属シ
ートをはさむ方法は、本発明者らの検討によると、少な
くとも半導体チップを破壊しない実用の圧力範囲ではそ
の変形量がごくわずか(弾性変形による変形のみ)であ
り、チップ位置毎の高さ(及びチップを挟む中間電極部
材等を含めた高さ)のばらつきが大きい場合にはその変
形量が不十分で、均一な接触を確保できないことが明ら
かとなった。
The above-described method of sandwiching a soft metal sheet, which is disclosed as a method for coping with the problem of uniform contact between chips in the multi-chip parallel type pressure contact type semiconductor device, is disclosed by the present invention. According to the studies by the users, at least in a practical pressure range where the semiconductor chip is not destroyed, the deformation amount is very small (only deformation due to elastic deformation), and the height at each chip position (and the intermediate electrode member etc. It is clear that when the variation in height is large, the deformation amount is insufficient and uniform contact cannot be ensured.

【0007】この原因は図8に模式図で示したように軟
質金属シート面に厚さ方向に圧力を加えて横方向へ塑性
変形させようとした場合にも、軟質金属シート43を挟
む電極部材44,45との界面で発生する摩擦力(摩擦
抵抗)46のため、軟金属材料といえども横方向への変
形抵抗が非常に大きくなってしまうことによると考えら
れる。変形させるために加圧力を上げても、摩擦力も圧
力に比例して大きくなるので塑性変形は容易には起こら
ない。
The cause of this is that, as shown in the schematic diagram of FIG. 8, the electrode member sandwiching the soft metal sheet 43 even when the soft metal sheet surface is pressed in the thickness direction to be plastically deformed in the horizontal direction. It is considered that the frictional force (frictional resistance) 46 generated at the interface with 44 and 45 causes the deformation resistance in the lateral direction to become extremely large even for a soft metal material. Even if the pressing force is increased for deformation, the plastic deformation does not easily occur because the frictional force also increases in proportion to the pressure.

【0008】特にシート形状のような抵抗を受ける面積
に比べて厚さが非常に小さい場合には、この表面に発生
する摩擦力の影響が支配的となるため、一般に知られて
いる材料の降伏応力を超える圧力を加えても実際には実
質的な塑性変形(流動)が起こらず、軟金属シートの厚
さは加圧の前後でほとんど変わらない。この摩擦抵抗を
下げるために、電極部材表面の粗さを小さくする方法が
考えられるが、ラップ仕上げ等で得られる現実的な加工
粗さの範囲(Rmax1〜0.5μm、Ra0.05〜0.03
μm)では大きな変形は起こらない。
In particular, when the thickness is very small compared with the area receiving the resistance, such as a sheet shape, the influence of the frictional force generated on the surface becomes dominant, so that the generally known yielding of the material occurs. Even if a pressure exceeding the stress is applied, practically no plastic deformation (flow) actually occurs, and the thickness of the soft metal sheet hardly changes before and after pressing. In order to reduce the frictional resistance, a method of reducing the roughness of the electrode member surface is considered. However, a practical range of the processing roughness obtained by lapping or the like (Rmax1 to 0.5 μm, Ra0.05 to 0.5). 03
μm), no significant deformation occurs.

【0009】本発明の目的は、上記のような大容量化に
対応する素子の多チップ並列化に伴って、ますます困難
になる大面積領域での均一な加圧接触状態を確保する方
法、すなわち接触面の高さのばらつき(反り,うねり,
部材寸法ばらつき等による)を吸収し、かつ接触界面で
の熱抵抗,電気抵抗を低減できる方法を提供するもので
ある。
An object of the present invention is to provide a method for ensuring a uniform pressure contact state in a large area region, which becomes more and more difficult with the multi-chip parallelization of elements corresponding to the above-mentioned large capacity, That is, variations in the height of the contact surface (warpage, undulation,
It is intended to provide a method capable of absorbing thermal resistance and electrical resistance at the contact interface by absorbing variation in member dimensions.

【0010】また第2の目的は上記により得られる半導
体装置を用いることにより、特に大容量のシステムに好
適な変換器を提供することにある。
A second object of the present invention is to provide a converter which is particularly suitable for a large-capacity system by using the semiconductor device obtained as described above.

【0011】[0011]

【課題を解決するための手段】上記課題は、少なくとも
第一主面に第一の主電極、第二主面に第二の主電極を有
する半導体素子を一対の共通電極板の間に組み込んだ加
圧接触型半導体装置において、該半導体素子と共通電極
板の間の電極間に細線状に加工した軟質金属またはその
集合体を配置することにより解決できる。より好ましく
は、上記細線状に加工した軟質金属の表面により軟質、
または耐酸化性の良い金属層を形成するか、該細線状に
加工した軟質金属に対向する電極面に軟質金属膜を形成
する。
SUMMARY OF THE INVENTION The object of the present invention is to provide a pressurizing method in which a semiconductor element having at least a first main electrode on a first main surface and a second main electrode on a second main surface is incorporated between a pair of common electrode plates. In the contact type semiconductor device, the problem can be solved by disposing a soft metal processed into a thin line or an aggregate thereof between electrodes between the semiconductor element and the common electrode plate. More preferably, the surface of the soft metal processed into a fine wire is softer,
Alternatively, a metal layer having good oxidation resistance is formed, or a soft metal film is formed on the electrode surface facing the soft metal processed into the fine line shape.

【0012】[0012]

【発明の実施の形態】本発明の実施の代表的な形態を図
面に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described with reference to the drawings.

【0013】図1に本発明の基本的な適用形態をシート
状の細線状軟質金属集合体を用いた例で示す。半導体素
子1の第一主面には少なくとも第一の主電極、第二主面
には第二の主電極が形成されている。この両主電極面上
にMoやW等からなる中間電極板2,3が配置され、さ
らにこの中間電極板の外側部分に一対のCuなどからな
る共通電極板(主電極板)4,5が配置される。中間電
極板3と主電極板5の間には細線状に加工した軟質金属
の集合体6が挟まれており、全体が一括に加圧されて各
部材間が接触されている。図1では(a),(b),(c)
位置で部品1,2,3の厚さの合計が順に厚くなるケー
スを示している。これらの高さの差に対応して、加圧接
触させる前には一定の厚さを持っていた細線状軟質金属
集合体6の厚さが、加圧接触後には(a),(b),(c)
の順に薄くなっている。すなわち、細線状軟質金属集合
体の高さを含めた全体としての高さ(部品1,2,3,
6の厚さの合計)が(a),(b),(c)位置で同じにな
るように細線状軟質金属集合体の厚さが変化している。
FIG. 1 shows a basic application form of the present invention by using an example of a sheet-like fine-wire soft metal aggregate. At least a first main electrode is formed on the first main surface of the semiconductor element 1, and a second main electrode is formed on the second main surface. Intermediate electrode plates 2 and 3 made of Mo, W, or the like are arranged on both main electrode surfaces, and a pair of common electrode plates (main electrode plates) 4 and 5 made of Cu or the like are provided on outer portions of the intermediate electrode plates. Be placed. An assembly 6 of a soft metal processed into a thin line is sandwiched between the intermediate electrode plate 3 and the main electrode plate 5, and the whole is pressurized at once and the members are in contact with each other. In FIG. 1, (a), (b), (c)
The case where the sum of the thicknesses of the components 1, 2, and 3 increases in order at the position is shown. Corresponding to the difference between these heights, the thickness of the thin wire-shaped soft metal aggregate 6 having a constant thickness before the pressure contact is changed to the thickness (a), (b) after the pressure contact. , (C)
It becomes thin in order. That is, the overall height (the parts 1, 2, 3, and 3) including the height of the thin linear soft metal assembly
6 is the same at the positions (a), (b), and (c).

【0014】これにより、上記部材1,2,3に各々厚
さばらつきがあったり、主電極板4,5にそりやうねり
がある場合でも複数のチップ位置(a),(b),(c)間
で良好な加圧接触状態を確保して半導体素子を実装で
き、従って熱抵抗,電気抵抗のばらつきの少ない半導体
装置が実現できる。図1では主電極板5と中間電極板3
の対向して圧接される面に細線状軟質金属集合体6を挟
んだ例を示したが、この位置はもちろん他の接触面、す
なわち主電極板4と中間電極板2の間や素子1と中間電
極板2,3の間でも良く、また複数の界面に対して同時
に適用しても構わない。また電極間ごとに異なる材質の
細線状軟質金属を配置してもよい。
Thus, even when the members 1, 2, 3 have thickness variations, or the main electrode plates 4, 5 have warpage or undulation, a plurality of chip positions (a), (b), (c) The semiconductor element can be mounted while maintaining a good pressure contact state between the two), and a semiconductor device with less variation in thermal resistance and electric resistance can be realized. In FIG. 1, the main electrode plate 5 and the intermediate electrode plate 3
Although the example in which the thin linear soft metal assembly 6 is interposed between the surfaces which are pressed against each other is shown, this position is, of course, the other contact surface, that is, between the main electrode plate 4 and the intermediate electrode plate 2 and between the element 1 and the element 1. It may be between the intermediate electrode plates 2 and 3 or may be applied to a plurality of interfaces at the same time. Also, a thin linear soft metal of a different material may be arranged for each electrode.

【0015】図2には本発明の細線状に加工した軟質金
属、及びその集合体の各種形状の代表例を示す。図2
(a)は棒状の軟質金属7が平面状きれいにならんで配
列され、さらにこれらの軟質金属棒7同士が互いに接着
8されて一体の薄板状(シート状)に保持されているも
のである。この接着部分8をネック部と呼ぶこととす
る。これらのネック部を形成する方法としては、細線を
接触させた状態で高温で仮焼したり、有機物または半田
等の低温接着剤を用いて接着する方法がある。
FIG. 2 shows representative examples of the soft metal processed into a fine wire according to the present invention and various shapes of the aggregate thereof. FIG.
(A) is a diagram in which bar-shaped soft metals 7 are arranged neatly in a planar manner, and these soft metal bars 7 are adhered 8 to each other and held in an integrated thin plate (sheet shape). This bonded portion 8 is called a neck portion. As a method of forming these neck portions, there is a method of calcining at a high temperature in a state where the fine wires are in contact with each other, or a method of bonding using a low-temperature adhesive such as an organic substance or solder.

【0016】図2(b)は細線状の軟質金属7が平面で
渦巻き状に配列され、さらにこれらの軟質金属7同士が
互いに接着8されて一体の円形薄板状(シート状)に保
持された例である。軟質金属線7同士の接着は必ずしも
必要ではない。
FIG. 2 (b) shows that the thin linear soft metals 7 are spirally arranged in a plane, and these soft metals 7 are bonded to each other 8 to be held in an integrated circular thin plate (sheet shape). It is an example. Adhesion between the soft metal wires 7 is not always necessary.

【0017】図2(c)は細線状の軟質金属7が平面で
リング(円環)状に加工した例、図2(d)は径の異な
る軟質金属リング(円環)が複数個組み合わされた例で
ある。いずれも細線の断面形状は円形の例を示したが、
必ずしも円形である必要はなく、もちろん偏平な形状で
もよい。
FIG. 2 (c) shows an example in which the thin wire-shaped soft metal 7 is processed into a ring (annular shape) in a plane, and FIG. 2 (d) shows a combination of a plurality of soft metal rings (annular shapes) having different diameters. This is an example. In each case, the cross-sectional shape of the thin line was an example of a circle,
The shape need not necessarily be circular, but may be flat.

【0018】図3は本発明の細線状軟質金属の加圧によ
る変形過程をモデル図として示したもので、シート状の
細線状軟質金属集合体70を用いた例で示す。図3
(a)は加圧する前のわずかに接触した状態、(b)は
加圧途中の状態、(c)は加圧され変形が十分に起った
状態を示している。初期に荷重がかけられると各細線状
軟質金属7の丸い表面のうち加圧する電極9に接してい
る部分の面積が非常に小さいため、ここにかかる圧力が
非常に大きくなり、この部分が容易につぶれ始める。
FIG. 3 is a model diagram showing the deformation process of the thin linear soft metal of the present invention by pressurization, and shows an example using a sheet-like thin linear soft metal aggregate 70. FIG.
(A) shows a state of slight contact before pressurizing, (b) shows a state in the middle of pressurizing, and (c) shows a state of being pressurized and sufficiently deformed. When a load is initially applied, the area of the round surface of each thin wire-shaped soft metal 7 that is in contact with the electrode 9 to be pressed is very small, so that the pressure applied here becomes very large, and this part is easily formed. Start crushing.

【0019】図3(b)には、比較説明のために変形前
の状態を点線10で示した。つぶれて変形された軟質金
属材料部分11は、微視的には電極9との界面にしっか
り接触した(押し付けられた)状態で塑性変形12し、
接触界面が増加して行く。これとともに全体の高さ(細
線状軟質金属集合体70の厚さ)は減少する。最終的に
は変形が十分に起こって、図3(c)に示すような状態
まで達する。
FIG. 3B shows a state before deformation by a dotted line 10 for comparison. The crushed and deformed soft metal material portion 11 microscopically undergoes plastic deformation 12 in a state of firmly contacting (pressing) the interface with the electrode 9,
The contact interface increases. At the same time, the overall height (the thickness of the thin linear soft metal assembly 70) decreases. Eventually, sufficient deformation occurs to reach the state shown in FIG.

【0020】この場合、原理的には無限大の荷重を加え
られれば界面が完全に埋る状態まで変形させることが可
能であるが、現実には荷重の制限のため完全に埋めるこ
とのできる圧力域まで使用することは不可能である。こ
の細線状軟質金属7の変形により、接触界面の増加と細
線状軟質金属集合体の板厚の減少の効果により電気抵
抗,熱抵抗は減少する。これに対して、一様厚さの軟質
金属薄板の場合には前述したように(図8)、降伏応力
を越える圧力を加えても塑性変形による大きな変形は起
こらず、弾性変形分の小さな変形が起こるだけである。
In this case, in principle, if an infinite load is applied, the interface can be deformed to a state in which the interface is completely filled. However, in reality, the pressure which can be completely filled due to the limitation of the load can be obtained. It is impossible to use up to the area. Due to the deformation of the thin linear soft metal 7, the electric resistance and the thermal resistance decrease due to the effect of increasing the contact interface and reducing the thickness of the thin linear soft metal aggregate. On the other hand, in the case of a soft metal sheet having a uniform thickness, as described above (FIG. 8), even if a pressure exceeding the yield stress is applied, large deformation due to plastic deformation does not occur, and small deformation corresponding to elastic deformation is caused. Only happens.

【0021】このような細線状軟質金属の場合には、前
述の一様な厚さをもつ金属箔(薄板)の場合(図8)と異
なり、自身の表面に空隙を有し、ミクロにはこの部分に
変形する力を受けた材料が容易に移動できるため、加圧
方向の変形に対する抵抗が小さく比較的小さな圧力で大
きな変形が得られる。また、マクロに見た横方向には接
触面での摩擦力による抵抗から、変形は実質的に板厚方
向(加圧される方向)のみに起こる。
Unlike the case of the above-mentioned metal foil (thin plate) having a uniform thickness (FIG. 8), such a thin linear soft metal has voids on its own surface, Since the material receiving the deformation force can be easily moved to this portion, the resistance to the deformation in the pressing direction is small, and a large deformation can be obtained with a relatively small pressure. Further, deformation occurs substantially only in the plate thickness direction (direction in which pressure is applied) in the macro direction due to the resistance due to the frictional force at the contact surface in the horizontal direction.

【0022】これらの材料は弾塑性変形能を有するた
め、変形後に除荷すると弾性変形分の戻りが見られる
が、ほぼ実装部品間の高さのばらつきに対応した塑性変
形分は保持される。再度加圧する場合には、この弾性変
形分を利用して同じ圧力で十分な接触が確保できる。こ
の変形が起こる圧力、および弾塑性変形挙動は、金属の
種類や、密度(空隙率),線の太さ(表面の曲率)によ
りコントロールすることが可能で、使用状況に応じた最
適な圧力で変形が起こるように選択することができる。
Since these materials have elasto-plastic deformation ability, when unloaded after deformation, the amount of elastic deformation returns, but the amount of plastic deformation almost corresponding to the variation in height between mounted components is maintained. When pressurizing again, sufficient contact can be ensured at the same pressure by utilizing this elastic deformation. The pressure at which this deformation occurs and the elasto-plastic deformation behavior can be controlled by the type of metal, density (porosity), and wire thickness (surface curvature). The deformation can be selected to occur.

【0023】図4は、ネック部の長さと最大つぶれ量と
の関係を軟質金属細線の直径で規格化して示した。変形
量を大きく確保したい場合には、ネック部をできるだけ
少なくし、線形を太くするのが良い。これにより変形前
に確保される細線状軟質金属の表面の空隙率を大きくす
ることができるためである。熱抵抗,電気抵抗の低減の
観点からは線径はできるだけ細い方が好ましい。従っ
て、ネック部の長さと軟質金属細線の直径の比は0.5
以下、好ましくは0.35以下が望ましい。
FIG. 4 shows the relationship between the length of the neck portion and the maximum crush amount, normalized by the diameter of the soft metal thin wire. When it is desired to secure a large amount of deformation, it is preferable to reduce the neck portion as much as possible and make the line shape thick. This is because the porosity of the surface of the fine linear soft metal secured before deformation can be increased. It is preferable that the wire diameter is as small as possible from the viewpoint of reducing the thermal resistance and the electric resistance. Therefore, the ratio of the length of the neck portion to the diameter of the soft metal wire is 0.5.
Or less, preferably 0.35 or less.

【0024】細線状軟質金属を挟む電極との界面の接触
抵抗(電気,熱)も重要な要素となる。接触抵抗をより
小さくするためには、この軟質金属細線を挟む電極との
界面の接触抵抗を小さくすることも重要である。このた
め細線状軟質金属の表面に細線状軟質金属材料より軟
質、または耐酸化性の良い金属層を印刷,めっき,蒸
着。
The contact resistance (electricity, heat) at the interface with the electrode sandwiching the thin linear soft metal is also an important factor. In order to further reduce the contact resistance, it is also important to reduce the contact resistance at the interface between the soft metal fine wire and the electrode. Therefore, a metal layer softer or more resistant to oxidation than the fine linear soft metal material is printed, plated, and vapor-deposited on the surface of the fine linear soft metal.

【0025】図5は、IGBT21を用いたスイッチングデバ
イスと逆並列に接続したフライホイールダイオード(F
WD)22を組み込んだ逆導通型スイッチングデバイス
に適用した例を示したものである。図には、右端の圧接
型半導体装置の最外部から中央に向かった途中までの一
部断面を示している。IGBTチップ21には上面側の
第一主面のほぼ全面にエミッタ電極、下面側の第二主面
にはコレクタ電極が形成されており、さらに第一主面に
は制御用電極(ゲート電極)が形成されている。また、
FWD22には、シリコン基板の上面側にアノード電
極,下面側にカソード電極が形成されている。
FIG. 5 shows a flywheel diode (F) connected in anti-parallel with a switching device using IGBT21.
1 shows an example in which the present invention is applied to a reverse conduction type switching device incorporating WD) 22. The figure shows a partial cross section from the outermost part of the press-contact type semiconductor device at the right end to the middle part toward the center. The IGBT chip 21 has an emitter electrode formed on substantially the entire first main surface on the upper surface side and a collector electrode on the second main surface on the lower surface side, and further has a control electrode (gate electrode) on the first main surface. Are formed. Also,
The FWD 22 has an anode electrode formed on the upper surface side of the silicon substrate and a cathode electrode formed on the lower surface side.

【0026】これらの各半導体チップの下側の主電極
(コレクタ、カソード)はAu電極とし、あらかじめA
uめっき膜が1〜3μm形成された中間電極24と加圧
接触されている。一方、中間電極23の表面にはAuめ
っき膜が2〜3μm形成され、各半導体チップと接着さ
れている。これらがさらに表面にNiめっき膜が2〜4
μm形成されている第1の共通主電極板(Cu)25と第
2の共通主電極板(Cu)26に挟まれている。ゲート制
御電極をチップから取り出すためのピン27がIGBT
チップの中央に形成されている。高さばらつきを吸収す
る為の線径1mmの金のOリング35が、中間電極板23
と共通電極板25の間の、上記ピン27、およびピンの
絶縁用部材28の周りに配置される。
The lower main electrodes (collector, cathode) of each of these semiconductor chips are Au electrodes.
The u-plated film is in pressure contact with the intermediate electrode 24 having a thickness of 1 to 3 μm. On the other hand, an Au plating film having a thickness of 2 to 3 μm is formed on the surface of the intermediate electrode 23 and is bonded to each semiconductor chip. These further have a Ni plating film on the surface of 2 to 4
It is sandwiched between a first common main electrode plate (Cu) 25 and a second common main electrode plate (Cu) 26 formed in μm. The pin 27 for taking out the gate control electrode from the chip is an IGBT.
It is formed in the center of the chip. A gold O-ring 35 having a wire diameter of 1 mm for absorbing height variations is provided on the intermediate electrode plate 23.
And the common electrode plate 25 and the pin 27 and the pin insulating member 28.

【0027】この方法では個別の軟質金属のOリング3
5は中央のピンの絶縁用部材28によりその位置ずれを
防止できるので、組立作業性等がよい。ゲート配線29
は、第1の共通主電極板(Cu)25に設けられた溝3
0に収納されてパッケージの外周部に引き出され、さら
に配線31,33によりパッケージ外部に取り出されて
いる。上記一対の共通主電極板25,26の間は、セラ
ミック製等の絶縁性の外筒32により外部絶縁され、さ
らに共通主電極板と絶縁外筒の間を金属板34によりパ
ッケージ内部をシール封止したハーメチック構造となっ
ている。ゲート電極配線は外筒32を貫通するシールさ
れた配線33によりパッケージ外に引き出されている。
In this method, an individual soft metal O-ring 3
The position 5 can be prevented from being displaced by the insulating member 28 of the center pin, so that assembling workability and the like are good. Gate wiring 29
Are grooves 3 provided in the first common main electrode plate (Cu) 25.
And is drawn out to the outer peripheral portion of the package, and further taken out of the package by wirings 31 and 33. The space between the pair of common main electrode plates 25 and 26 is externally insulated by an insulating outer cylinder 32 made of ceramic or the like, and the interior of the package is sealed and sealed between the common main electrode plate and the insulating outer cylinder by a metal plate 34. It has a stopped hermetic structure. The gate electrode wiring is led out of the package by a sealed wiring 33 penetrating the outer cylinder 32.

【0028】本実施例で実装したチップ位置毎の厚さば
らつきを最大100μmとしたが、中間電極板24と共
通主電極板26間に感圧紙を挟んで圧力分布を測定した
結果、圧力差は小さく、ほぼ均一に加圧されていること
がわかった。
Although the thickness variation at each chip position mounted in this embodiment was set to a maximum of 100 μm, the pressure difference was measured with a pressure-sensitive paper sandwiched between the intermediate electrode plate 24 and the common main electrode plate 26. It was found that the pressure was small and almost uniform.

【0029】高さの補正と電気抵抗,熱抵抗の低減を最
適に実現するために、電極間に細線状に加工した軟質金
属またはその集合体を挟むだけでなく、軟質の金属箔と
同時に配置してもよい。例えば、上側の主電極板と中間
電極板の間にはAu箔を挿入し、下側の主電極板と中間
電極板の間に軟質金属細線集合体を挿入する等の方法も
有効である。また上記の様に種類の異なる半導体チップ
を一つのパッケージ内に並列実装する場合で、種類毎に
その厚さが大きく異なる場合には、チップ種に応じて中
間電極板の平均厚さを変えたものを準備しチップ厚さの
大きな違いを調整し、さらに本発明の細線状に加工した
軟質金属またはその集合体による変形を主に中間電極板
および半導体チップの厚さのばらつきの吸収に用いる方
法も有効である。
In order to optimally realize the height correction and the reduction of the electric resistance and the thermal resistance, not only the soft metal or the aggregate thereof formed into a thin wire shape is sandwiched between the electrodes, but also the soft metal foil is arranged at the same time. May be. For example, a method of inserting an Au foil between the upper main electrode plate and the intermediate electrode plate, and inserting a soft metal thin wire assembly between the lower main electrode plate and the intermediate electrode plate is also effective. In the case where different types of semiconductor chips are mounted in parallel in one package as described above, when the thickness differs greatly for each type, the average thickness of the intermediate electrode plate was changed according to the type of chip. A method of preparing a material, adjusting a large difference in chip thickness, and further using the deformation caused by the soft metal processed into a fine wire shape or the aggregate thereof according to the present invention mainly for absorbing thickness variations of the intermediate electrode plate and the semiconductor chip. Is also effective.

【0030】従来、一般に共通電極板、及び中間電極板
の表面は接触抵抗を低減する為にその表面粗さ(Rmax)
を1μm以下に仕上げることが必要だったが、上記細線
状に加工した軟質金属またはその集合体を挟む共通電極
板、及び中間電極板の表面は最大表面粗さ(Rmax)1μ
mを越える粗い凹凸状態でも、材料が表面凹凸にあわせ
て変形し、接触面積がミクロに増大して接触抵抗を低減
できるので、加工コストの低減が図れる。むしろ変形の
為の空隙が増加するので、変形量を特に多く確保したい
場合等には好適である。この場合には共通電極板、及び
中間電極板の表面は最大表面粗さ(Rmax)3μmを越え
るものが好ましい。
Conventionally, the surface of the common electrode plate and the intermediate electrode plate generally have a surface roughness (Rmax) in order to reduce the contact resistance.
Was required to be finished to 1 μm or less, but the surface of the common electrode plate and the intermediate electrode plate sandwiching the soft metal processed into the fine wire or the aggregate thereof and the intermediate electrode plate had a maximum surface roughness (Rmax) of 1 μm.
Even in a rough state exceeding m, the material is deformed according to the surface unevenness, the contact area is microscopically increased, and the contact resistance can be reduced, so that the processing cost can be reduced. Rather, since the space for deformation increases, it is suitable when a particularly large amount of deformation is desired. In this case, the surfaces of the common electrode plate and the intermediate electrode plate preferably have a maximum surface roughness (Rmax) exceeding 3 μm.

【0031】軟質金属としては、銅,アルミニウム,
銀,金,半田等が特に好ましく、半導体装置の使用形態
に応じて、熱抵抗,電気抵抗の低減、または変形能の向
上のどちらを優先するかによって最適な材質,表面処理
を選択するのが好ましい。
As soft metals, copper, aluminum,
Silver, gold, solder, etc. are particularly preferred. Depending on the usage of the semiconductor device, it is important to select the most suitable material and surface treatment depending on whether thermal resistance, electrical resistance is reduced, or the deformability is improved. preferable.

【0032】上記中間電極の材料としては、熱膨張係数
がSiと外部主電極材料の中間で、熱伝導性,電気伝導
性の良好な材料が用いられる。具体的にはタングステン
(W)やモリブデン(Mo)等の単体金属、またはそれら
を主たる構成材料とするCu−W,Ag−W,Cu−M
o,Ag−Mo,Cu−FeNi等の複合材料または合
金、さらには金属とセラミックスやカーボンとの複合材
料、たとえばCu/SiC,Cu/C,Al/SiC,
Al/AlN等が好ましい。一方、主電極には電気伝導
性で熱伝導性の良い銅やアルミニウム、またはそれらを
含む前述のような合金または複合材料を使用するのが好
ましい。
As the material for the intermediate electrode, a material having a thermal expansion coefficient between that of Si and the external main electrode material and having good thermal conductivity and electric conductivity is used. Specifically, tungsten
Metal such as (W) and molybdenum (Mo), or Cu-W, Ag-W, Cu-M using them as main constituent materials
o, Ag-Mo, Cu-FeNi or other composite materials or alloys, and further, composite materials of metals and ceramics or carbon, such as Cu / SiC, Cu / C, Al / SiC,
Al / AlN and the like are preferable. On the other hand, for the main electrode, it is preferable to use copper or aluminum having good electrical conductivity and thermal conductivity, or the above-mentioned alloy or composite material containing them.

【0033】本発明の実装方式は、もちろんダイオード
を含まないIGBT等のスイッチング半導体のみからな
る圧接型半導体装置にも用いることができる他、例えば
ダイオードチップのみを多数個上記の方法で圧接型パッ
ケージに実装することももちろん有効である。また、上
記実施例では、主としてIGBTを用いて説明したが、
本発明は少なくとも第一主面に第一の主電極と第二主面
に第二の主電極を有する半導体素子全般を対象としてお
り、IGBT以外の絶縁ゲート形トランジスタ(MOS
トランジスタ)や、IGCT(Insulated Gate Control
led Thyristor)などを含む絶縁ゲート形サイリスタ(M
OS制御サイリスタ)や、GTO,サイリスタ、及びダ
イオードなどに対しても同様に実施できる。また、Si
素子以外のSiC,GaNなどの化合物半導体素子に対
しても同様に有効である。
The mounting method of the present invention can of course be used for a pressure contact type semiconductor device comprising only a switching semiconductor such as an IGBT which does not include a diode. For example, a large number of diode chips alone can be used in a pressure contact type package by the above method. Implementation is of course also effective. Further, in the above embodiment, the description has been made mainly using the IGBT.
The present invention is directed to a general semiconductor device having at least a first main electrode on a first main surface and a second main electrode on a second main surface, and uses an insulated gate transistor (MOS) other than an IGBT.
Transistor), IGCT (Insulated Gate Control)
led Thyristor) and other insulated gate thyristors (M
An OS control thyristor), a GTO, a thyristor, a diode, and the like can be similarly implemented. In addition, Si
The present invention is similarly effective for compound semiconductor devices such as SiC and GaN other than the device.

【0034】本発明の圧接型半導体装置では、大型化
(大容量化)しても安定した電極間の接触状態が得られる
ため、電気抵抗,熱抵抗の小さな半導体装置が得られ
る。従って、この圧接型半導体装置を用いることによ
り、変換器容積、及びコストを大幅に削減した大容量変
換器が実現できるようになる。図6に本発明によるIG
BTの圧接型半導体装置を主変換素子として電力用変換
器に応用した場合の1ブリッジ分の構成回路図を示す。
In the press-contact type semiconductor device of the present invention,
Even if (capacity is increased), a stable contact state between the electrodes can be obtained, so that a semiconductor device having small electric resistance and thermal resistance can be obtained. Therefore, by using this press-contact type semiconductor device, it becomes possible to realize a large-capacity converter in which the volume and cost of the converter are greatly reduced. FIG. 6 shows an IG according to the present invention.
FIG. 3 is a circuit diagram showing a configuration of one bridge in a case where a pressure contact type semiconductor device of BT is applied to a power converter as a main conversion element.

【0035】主変換素子となるIGBT素子40とダイ
オード素子41が逆並列に配置され、これらがn個直列
に接続された構成となっている。これらIGBTとダイ
オードは、本発明による多数の半導体チップを並列実装
した圧接型半導体装置を示している。上記図5の実施例
の逆導通型IGBT圧接型半導体装置の場合には図中の
IGBTチップとダイオードチップがまとめて一つのパ
ッケージに収められた形となる。これにスナバ回路4
2、及び限流回路が設けてある。
An IGBT element 40 and a diode element 41 serving as main conversion elements are arranged in anti-parallel, and n pieces are connected in series. These IGBTs and diodes represent a press-contact type semiconductor device in which a number of semiconductor chips according to the present invention are mounted in parallel. In the case of the reverse conducting IGBT pressure contact type semiconductor device of the embodiment shown in FIG. 5, the IGBT chip and the diode chip in the drawing are put together in one package. This is a snubber circuit 4
2, and a current limiting circuit.

【0036】図7は、図6の3相ブリッジを4多重した
自励式変換器の構成を示したものである。本発明の圧接
型半導体装置は、複数個をその主電極板外側と面接触す
る形で水冷電極を挟んで直列接続するスタック構造と呼
ぶ形に実装され、スタック全体を一括で加圧する。本発
明によれば、従来より低い加圧力でも均一な接触が得ら
れるので、上記スタック構造等を簡略化できるという効
果もある。
FIG. 7 shows the configuration of a self-excited converter in which the three-phase bridge of FIG. 6 is multiplexed by four. The press-contact type semiconductor device of the present invention is mounted in a so-called stack structure in which a plurality of the press-contact semiconductor devices are connected in series with a water-cooled electrode interposed therebetween so as to make surface contact with the outside of the main electrode plate, and pressurize the entire stack at once. According to the present invention, uniform contact can be obtained even with a lower pressing force than in the past, so that the stack structure and the like can be simplified.

【0037】本発明の圧接型半導体装置は、上記の例に
限らず電力系統に用いられる自励式大容量変換器やミル
用変換器として用いられる大容量変換器に特に好適で、
可変速揚水発電,ビル内変電所設備,電鉄用変電設備,
ナトリウム硫黄(NaS)電池システム,車両等の変換
器にも用いることができる。
The pressure-contact type semiconductor device of the present invention is not particularly limited to the above example, and is particularly suitable for a self-excited large-capacity converter used in a power system or a large-capacity converter used as a converter for a mill.
Variable speed pumped storage power generation, substation facilities in buildings, substation facilities for railways,
It can also be used in converters for sodium-sulfur (NaS) battery systems and vehicles.

【0038】[0038]

【発明の効果】本発明によれば、ウエハの大口径化によ
るパッケージの大型化や、大容量化に対応する素子の多
チップ並列化に伴って、ますます困難になる大面積域で
の均一圧接を比較的低圧力で簡単に実現することができ
る、すなわち接触面の高さのばらつきを十分に吸収し、
かつ接触界面での熱抵抗,電気抵抗を低減できる。
According to the present invention, uniformity over a large area becomes increasingly difficult with the increase in the size of the package due to the increase in the diameter of the wafer and the parallelization of elements corresponding to the increase in the capacity. Pressure welding can be easily realized with relatively low pressure, that is, it absorbs variations in the height of the contact surface sufficiently,
In addition, the thermal resistance and electric resistance at the contact interface can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の基本構成である加圧接触型半導体装置
を示す断面図。
FIG. 1 is a sectional view showing a pressure contact type semiconductor device which is a basic configuration of the present invention.

【図2】軟質金属細線集合体の実施形態の代表例を示す
図。
FIG. 2 is a diagram showing a typical example of an embodiment of a soft metal fine wire aggregate.

【図3】図2の軟質金属細線材料の変形挙動を示すモデ
ル図。
FIG. 3 is a model diagram showing a deformation behavior of the soft metal fine wire material of FIG. 2;

【図4】規格化したネック部の長さと最大つぶれ量との
関係を示す特性図。
FIG. 4 is a characteristic diagram showing a relationship between a normalized neck length and a maximum crushing amount.

【図5】IGBTに適用した本発明の実施例を示す側断
面図。
FIG. 5 is a side sectional view showing an embodiment of the present invention applied to an IGBT.

【図6】本発明の半導体装置を用いた1ブリッジ分の構
成回路図。
FIG. 6 is a configuration circuit diagram of one bridge using the semiconductor device of the present invention.

【図7】図6の3相ブリッジを4多重した自励式変換器
の構成図。
FIG. 7 is a configuration diagram of a self-excited converter in which the three-phase bridge of FIG.

【図8】従来方式で加圧した場合の軟質金属の変形挙動
を説明する図。
FIG. 8 is a diagram illustrating the deformation behavior of a soft metal when pressurized by a conventional method.

【符号の説明】[Explanation of symbols]

1…半導体素子、2,3,23,24…中間電極板、
4,5,25,26…共通電極板、6,17,30,3
6…細線状に加工した軟質金属またはその集合体、7…
軟質金属細線、8…接着部(ネック部)、9…加圧電
極、10…変形前の状態、11…変形された軟質金属材
料部分、12…塑性変形した部分、21…IGBT、2
2…フライホイールダイオード、27…ピン、28…絶
縁用部材、29,31,33…ゲート配線、30…溝、
32…絶縁性外筒、34…金属板、35…Oリング、4
0…IGBT素子、41…ダイオード素子、42…スナ
バ回路、43…軟質金属シート、44,45…電極部
材、46…摩擦力(摩擦抵抗)、70…細線状軟質金属
集合体。
1: semiconductor element, 2, 3, 23, 24 ... intermediate electrode plate
4, 5, 25, 26 ... common electrode plate, 6, 17, 30, 3
6 ... Soft metal processed into a thin wire or its aggregate, 7 ...
Soft metal fine wire, 8: bonded portion (neck portion), 9: pressurized electrode, 10: state before deformation, 11: deformed soft metal material portion, 12: plastically deformed portion, 21: IGBT, 2
2 ... flywheel diode, 27 ... pin, 28 ... insulating member, 29, 31, 33 ... gate wiring, 30 ... groove,
32: insulating outer cylinder, 34: metal plate, 35: O-ring, 4
0: IGBT element, 41: Diode element, 42: Snubber circuit, 43: Soft metal sheet, 44, 45: Electrode member, 46: Friction force (friction resistance), 70: Fine linear soft metal aggregate.

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】両面に露出する一対の共通電極板の間を絶
縁性の外筒により外部絶縁した平型パッケージの中に、
第一主面に少なくとも第一の主電極、第二主面に第二の
主電極を有する複数個の半導体素子を並置して組み込ん
だ半導体装置であって、該半導体素子と共通電極板の電
極間に細線状に加工した軟質金属またはその集合体を配
置したことを特徴とする加圧接触型半導体装置。
A flat package in which a pair of common electrode plates exposed on both sides is externally insulated by an insulating outer cylinder.
A semiconductor device in which a plurality of semiconductor elements having at least a first main electrode on a first main surface and a second main electrode on a second main surface are juxtaposed and incorporated, and the electrodes of the semiconductor element and a common electrode plate are provided. A pressure contact type semiconductor device, wherein a soft metal processed into a fine wire or an aggregate thereof is disposed between the soft metal and the soft metal.
【請求項2】両面に露出する一対の共通電極板の間を絶
縁性の外筒により外部絶縁した平型パッケージの中に、
第一主面に少なくとも第一の主電極、第二主面に第二の
主電極を有する複数個の半導体素子を並置して組み込ん
だ半導体装置であって、各半導体素子の主電極とこれに
対向する共通電極板との間に導電、及び放熱を兼ねた中
間電極板を介装し、さらに少なくとも一方の該中間電極
板とこれに対向する共通電極板間に細線状に加工した軟
質金属またはその集合体を配置したことを特徴とする加
圧接触型半導体装置。
2. A flat package in which a pair of common electrode plates exposed on both sides are externally insulated by an insulating outer cylinder.
A semiconductor device in which a plurality of semiconductor elements having at least a first main electrode on a first main surface and a second main electrode on a second main surface are juxtaposed and incorporated, and the main electrode of each semiconductor element and the Conductive, between the opposing common electrode plate, and an intermediate electrode plate also serving as heat dissipation is interposed, further soft metal processed into a thin wire between at least one of the intermediate electrode plate and the common electrode plate opposed thereto A pressure contact type semiconductor device wherein the aggregate is arranged.
【請求項3】前記細線状に加工した軟質金属の集合体が
平面状に配列されて一体の薄板状に保持されていること
を特徴とする請求項1及び2記載の加圧接触型半導体装
置。
3. The pressure contact type semiconductor device according to claim 1, wherein the aggregate of the soft metal processed into a thin wire is arranged in a plane and held as an integral thin plate. .
【請求項4】前記細線状に加工した軟質金属またはその
集合体がリング形状になっていることを特徴とする1乃
至3記載の加圧接触型半導体装置。
4. The pressure contact type semiconductor device according to claim 1, wherein the soft metal processed into a fine wire or an aggregate thereof is formed in a ring shape.
【請求項5】前記細線状に加工した軟質金属が主として
Cu,Al,Ag,Auまたは半田からなることを特徴
とする請求項1乃至4記載の加圧接触型半導体装置。
5. The pressure contact type semiconductor device according to claim 1, wherein said soft metal processed into a fine wire shape is mainly made of Cu, Al, Ag, Au or solder.
【請求項6】前記軟質金属の表面に、より軟質、または
耐酸化性の良い金属層が形成されていることを特徴とす
る請求項1乃至5記載の加圧接触型半導体装置。
6. A pressure contact type semiconductor device according to claim 1, wherein a softer or better oxidation-resistant metal layer is formed on the surface of said soft metal.
【請求項7】前記各半導体素子の主電極,中間電極板、
及び共通電極板のうち互いに対向する少なくとも一つの
接触面間に、さらに軟質金属箔を介装することを特徴と
する請求項1乃至6記載の加圧接触型半導体装置。
7. A main electrode and an intermediate electrode plate of each of the semiconductor elements,
7. The pressure contact type semiconductor device according to claim 1, further comprising a soft metal foil interposed between at least one contact surface of the common electrode plate and the contact surface facing each other.
【請求項8】前記中間電極、または共通電極板の少なく
とも一方の面に、軟質金属薄膜を形成することを特徴と
する請求項1乃至7記載の加圧接触型半導体装置。
8. A pressure contact type semiconductor device according to claim 1, wherein a soft metal thin film is formed on at least one surface of said intermediate electrode or common electrode plate.
【請求項9】前記共通電極板、及び中間電極板の少なく
とも一面が最大表面粗さ(Rmax)1μmを越える粗い凹
凸加工がなされていることを特徴とする請求項1乃至8
記載の加圧接触型半導体装置。
9. A method according to claim 1, wherein at least one surface of said common electrode plate and said intermediate electrode plate is roughened to have a maximum surface roughness (Rmax) exceeding 1 μm.
The pressure contact type semiconductor device according to the above.
【請求項10】前記半導体素子が第一主面に第一主電極
と制御電極、第二主面に第二主電極を有する絶縁ゲート
形素子であり、さらに同一の圧接型パッケージ内には第
一主面に第一主電極、第二主面に第二主電極を有するフ
ライホイールダイオードを、上記絶縁ゲート形素子と逆
並列に各々複数個ずつ並置して組み込んだことを特徴と
する請求項1乃至9記載の加圧接触型半導体装置。
10. The semiconductor device is an insulated gate device having a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface. A flywheel diode having a first main electrode on one main surface and a second main electrode on a second main surface, a plurality of flywheel diodes each being incorporated in parallel in anti-parallel with the insulated gate element. 10. A pressure contact type semiconductor device according to any one of 1 to 9.
【請求項11】両面に露出する一対の共通電極板の間を
絶縁性の外筒により外部絶縁した平型パッケージの中
に、第一主面に少なくとも第一の主電極、第二主面に第
二の主電極を有複数個の半導体素子を並置して組み込
み、さらに該半導体素子と共通電極板の間に細線状に加
工した軟質金属またはその集合体を配置した加圧接触型
半導体装置を主変換素子として用いたことを特徴とする
電力変換器。
11. A flat package in which a pair of common electrode plates exposed on both sides are externally insulated by an insulating outer cylinder, at least a first main electrode on a first main surface and a second main electrode on a second main surface. A pressure contact type semiconductor device in which a plurality of semiconductor elements are juxtaposed and incorporated, and a soft metal or an aggregate thereof formed into a thin wire between the semiconductor element and a common electrode plate is used as a main conversion element. A power converter characterized by using:
【請求項12】両面に露出する一対の共通電極板の間を
絶縁性の外筒により外部絶縁した平型パッケージの中
に、第一主面に少なくとも第一の主電極、第二主面に第
二の主電極を有する複数個の半導体素子を並置して組み
込み、かつ各半導体素子の主電極とこれに対向する共通
電極板との間に導電、及び放熱を兼ねた中間電極板を介
装し、さらに該中間電極板とこれに対向する共通電極板
間の少なくとも一方に細線状に加工した軟質金属または
その集合体を配置した加圧接触型半導体装置を主変換素
子として用いたことを特徴とする電力変換器。
12. A flat package in which a pair of common electrode plates exposed on both sides are externally insulated by an insulating outer cylinder, at least a first main electrode on a first main surface and a second main electrode on a second main surface. A plurality of semiconductor elements having main electrodes are juxtaposed and incorporated, and an intermediate electrode plate that also serves as a conductive and heat radiator is interposed between the main electrode of each semiconductor element and a common electrode plate opposed thereto, Further, a pressure contact type semiconductor device in which a soft metal processed into a fine wire or an aggregate thereof is disposed on at least one between the intermediate electrode plate and a common electrode plate opposed thereto is used as a main conversion element. Power converter.
JP34754397A 1997-12-17 1997-12-17 Pressure-contact semiconductor device and power converter provided therewith Pending JPH11186299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34754397A JPH11186299A (en) 1997-12-17 1997-12-17 Pressure-contact semiconductor device and power converter provided therewith

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34754397A JPH11186299A (en) 1997-12-17 1997-12-17 Pressure-contact semiconductor device and power converter provided therewith

Publications (1)

Publication Number Publication Date
JPH11186299A true JPH11186299A (en) 1999-07-09

Family

ID=18390945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34754397A Pending JPH11186299A (en) 1997-12-17 1997-12-17 Pressure-contact semiconductor device and power converter provided therewith

Country Status (1)

Country Link
JP (1) JPH11186299A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016019995A1 (en) * 2014-08-06 2016-02-11 Siemens Aktiengesellschaft Electric safety arrangement comprising a metal foam, and method for interrupting an electric current using said safety arrangement
EP3324432A1 (en) * 2016-11-17 2018-05-23 Infineon Technologies AG Method of electrically contacting a plurality of semiconductor chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016019995A1 (en) * 2014-08-06 2016-02-11 Siemens Aktiengesellschaft Electric safety arrangement comprising a metal foam, and method for interrupting an electric current using said safety arrangement
EP3324432A1 (en) * 2016-11-17 2018-05-23 Infineon Technologies AG Method of electrically contacting a plurality of semiconductor chips

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