JPH1197463A - Pressure joint semiconductor device - Google Patents

Pressure joint semiconductor device

Info

Publication number
JPH1197463A
JPH1197463A JP25644197A JP25644197A JPH1197463A JP H1197463 A JPH1197463 A JP H1197463A JP 25644197 A JP25644197 A JP 25644197A JP 25644197 A JP25644197 A JP 25644197A JP H1197463 A JPH1197463 A JP H1197463A
Authority
JP
Japan
Prior art keywords
main
electrode
semiconductor device
main electrode
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25644197A
Other languages
Japanese (ja)
Inventor
Mitsuo Kato
光雄 加藤
Ryoichi Kajiwara
良一 梶原
Hironori Kodama
弘則 児玉
Mamoru Sawahata
守 澤畠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP25644197A priority Critical patent/JPH1197463A/en
Publication of JPH1197463A publication Critical patent/JPH1197463A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To absorb dispersion in heigh of a contact surface, thermal resistance, and electric resistance in a contact interface, by combining a main electrode of a semiconductor element, and at least one of intermediate electrode plates through a plurality of metallic bumps. SOLUTION: In a pressure joint semiconductor device, a first main electrode 2 is formed in a first main surface of a semiconductor chip or a wafer 1, and a second main electrode 3 is formed in a second main surface. An assembly wherein the first main electrode 2 and an intermediate electrode plate 4 formed of Mo and W are joined by a metallic bump 7 is arranged in a first main surface of the wafer 1. Furthermore, a pair of Cu main electrode plates 8, 9 are arranged in an outside part of the intermediate electrode plate 4 and are pressed at once, thus bringing members into contact with each other. As a result, parallelism of intermediate electrode plates 4, 5 is corrected during junction and dispersion in height of a contact surface (irregularities due to warp, undulation, in size of members, etc.) is absorbed and thermal and electric resistance can be reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、圧接型半導体装置
に係り、特に半導体素子とパッケージ電極間の熱抵抗,
電気抵抗を低減し、均一な接触を確保できる圧接型半導
体装置、及びこれを用いた変換器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pressure contact type semiconductor device, and more particularly, to a thermal resistance between a semiconductor element and a package electrode.
The present invention relates to a press-contact type semiconductor device capable of reducing electric resistance and ensuring uniform contact, and a converter using the same.

【0002】[0002]

【従来の技術】半導体エレクトロニクスの技術を駆使し
て主回路電流を制御するパワーエレクトロニクスの技術
は、幅広い分野で応用され、さらにその適用拡大がなさ
れつつある。パワー用半導体素子としては、サイリス
タ,光サイリスタ,ゲートターンオフサイリスタ(GT
O)や、MOS制御デバイスである絶縁ゲート型バイポ
ーラトランジスタ(以下IGBTと略す)やMOS型電
界効果トランジスタ(以下MOSFETと略す)などがある。
これらのデバイスでは、主に半導体チップの第一主面上
に主電極(カソード,エミッタ電極)、第二主面側には
もう一方の主電極(アノード,コレクタ電極)が形成さ
れる。
2. Description of the Related Art The technology of power electronics, which controls the main circuit current by making full use of the technology of semiconductor electronics, has been applied in a wide range of fields, and its application is being expanded. Thyristors, optical thyristors, gate turn-off thyristors (GT)
O), an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) or a MOS field effect transistor (hereinafter abbreviated as MOSFET) which are MOS control devices.
In these devices, a main electrode (cathode, emitter electrode) is mainly formed on a first main surface of a semiconductor chip, and another main electrode (anode, collector electrode) is formed on a second main surface side.

【0003】GTO,光サイリスタ等の大電力用の半導
体装置においては、素子を1枚のウエハ毎にパッケージ
ングしている。上記素子の両主電極は、MoまたはWか
らなる熱緩衝用電極板を介してパッケージの一対の外部
主電極により加圧接触される構造となっている。スイッ
チング動作の均一性や大電流の遮断特性の向上等の為に
は、上記素子電極,熱緩衝板,外部主電極間の接触状態
をできるだけ均一化し、かつ接触熱抵抗,電気抵抗を下
げることが重要である。
In a high-power semiconductor device such as a GTO or an optical thyristor, elements are packaged for each wafer. The two main electrodes of the above-mentioned element are structured to be brought into pressure contact with a pair of external main electrodes of the package via a heat buffer electrode plate made of Mo or W. In order to improve the uniformity of the switching operation and the breaking characteristics of large currents, it is necessary to make the contact state between the above-mentioned element electrode, thermal buffer plate and external main electrode as uniform as possible, and to lower the contact thermal resistance and electric resistance. is important.

【0004】このため、一般にはパッケージ部品の加工
精度(平面度,平坦度)を上げて反りやうねりを低減す
る対策がとられている。さらに金属間の接触熱抵抗に関
しては、接触する面の粗さが粗くなるにつれて接触熱抵
抗は大きくなることが知られている。従来は、この観点
から接触熱抵抗、及び電気抵抗を下げる方法として表面
粗さをできるだけ小さくする方向で対策が進められてき
た。
For this reason, measures are generally taken to increase the processing accuracy (flatness, flatness) of package components and reduce warpage and undulation. Further, with respect to the contact thermal resistance between metals, it is known that the contact thermal resistance increases as the roughness of the contact surface increases. Conventionally, from this viewpoint, countermeasures have been promoted as a method of reducing the contact thermal resistance and the electric resistance in a direction of reducing the surface roughness as much as possible.

【0005】一方、IGBT等ではこれまで主にモジュ
ール型構造と呼ばれる、ワイヤによる電極接続方式のパ
ッケージ形態により複数個のチップを実装していた。こ
のようなモジュール型パッケージの場合、素子内部で発
生した熱はパッケージの片面、すなわち金属ベース上に
直接マウントしたコレクタ側のみから逃がすことになる
ため、一般に熱抵抗が大きく、一つのパッケージに実装
できるチップ数(発熱量、または電流容量)に制限があ
った。
On the other hand, in IGBTs and the like, a plurality of chips have been mounted so far mainly in a package form of an electrode connection system using wires, which is called a module type structure. In the case of such a modular package, heat generated inside the element is released only from one side of the package, that is, only from the collector side directly mounted on the metal base, so that the thermal resistance is generally large and can be mounted in one package. The number of chips (calorific value or current capacity) was limited.

【0006】最近、このような問題に対処し大容量化の
要求に応えるため、特開平8−88240号公報等に提案され
ているようなIGBT素子複数個をGTOのパッケージ
に類似した平型のパッケージ内に並列に組み込み、その
主面に形成されたエミッタ電極,コレクタ電極をそれぞ
れパッケージ側に設けた一対の外部主電極板に面接触さ
せて引き出すようにした多チップ並列型加圧接触構造の
半導体装置が注目されている。この多チップ並列型の圧
接型半導体装置では、部材寸法ばらつきに起因するチッ
プ位置毎の高さのばらつきが避けられず、これによりチ
ップ毎に加圧力が異なり均一な接触が得られないという
問題があった。この問題に対して、特開平8−88240号公
報においては、Agなどの延性のある軟金属シートの厚
さ補正板を介在させる方法を開示している。
Recently, in order to cope with such a problem and respond to a demand for a large capacity, a plurality of IGBT elements proposed in Japanese Patent Application Laid-Open No. 8-88240 and the like are formed in a flat type similar to a GTO package. A multi-chip parallel type pressure contact structure in which the emitter electrode and collector electrode formed on the main surface of the package are brought into surface contact with a pair of external main electrode plates provided on the package side, respectively, and pulled out in parallel in the package. Semiconductor devices are receiving attention. In this multi-chip parallel type pressure contact type semiconductor device, there is an unavoidable variation in height at each chip position due to a variation in member dimensions, which results in a problem in that the pressure is different for each chip and uniform contact cannot be obtained. there were. To cope with this problem, Japanese Patent Application Laid-Open No. 8-88240 discloses a method of interposing a thickness correcting plate made of a ductile soft metal sheet such as Ag.

【0007】[0007]

【発明が解決しようとする課題】上記GTO等のパッケ
ージにおいては、今後ますます大容量化のために素子サ
イズ(ウエハサイズ)が大型化し、この大口径化に伴っ
てウエハ、およびパッケージ部品(電極部品)の反りも
大きくなる傾向にある。
In a package such as the above-mentioned GTO, the element size (wafer size) has been increased in order to increase the capacity in the future. Parts) tend to increase.

【0008】前述のようなパッケージ部品の加工精度
(平面度,平坦度)を上げて反りやうねりを低減し、さ
らに表面粗さを小さくするという対策には加工上の限界
があり、また加工コスト面での問題も大きい。従って素
子サイズ(ウエハサイズ)全面にわたって、ウエハ及び
パッケージ部品(電極)間の均一な接触を確保し、熱抵
抗,電気抵抗を低減することがますます困難になってき
ている。
[0008] There is a limit in the processing to increase the processing accuracy (flatness, flatness) of the package parts as described above to reduce warpage and undulation, and to further reduce the surface roughness. The problem in terms of aspect is also great. Therefore, it has become increasingly difficult to ensure uniform contact between the wafer and package components (electrodes) over the entire element size (wafer size), and to reduce thermal resistance and electrical resistance.

【0009】一方、多チップ並列型の圧接型半導体装置
におけるチップ間の均一接触の問題に対処する方法とし
て開示されている前述の軟金属シートをはさむ方法は、
本発明者らの検討によると、少なくとも半導体チップを
破壊しない実用の圧力範囲ではその変形量がごくわずか
(弾性変形による変形のみ)であり、チップ間の高さ
(及びチップを挟む中間電極部材を含めた高さ)のばら
つきが大きい場合にはその厚さばらつき吸収能が不十分
であることが明らかとなった。軟質金属シート面に厚さ
方向の圧力を加えて、横方向へ塑性変形させようとした
場合、軟質金属シートを挟む電極部材との界面で発生す
る摩擦力(摩擦抵抗)のため、軟金属材料の横方向への
変形抵抗が非常に大きくなってしまうことによると考え
られる。変形させるために加圧力を上げても、摩擦力も
圧力に比例して大きくなるので塑性変形は容易には起こ
らない。特にシート形状のような抵抗を受ける面積に比
べて厚さが非常に小さい場合には、この表面に発生する
摩擦力の影響が支配的となるため、一般に知られている
材料の降伏応力を超える圧力を加えても実際には実質的
な塑性変形(流動)が起こらず、軟金属シートの厚さは
ほとんど変わらない。本発明の第1の目的は、上記のよ
うなウエハの大口径化によるパッケージの大型化や、大
容量化に対応する素子の多チップ並列化に伴って、ます
ます困難になる大面積での均一な圧接状態を確保する方
法、すなわち接触面の高さのばらつき(反り,うねり,
部材寸法ばらつき等による)を吸収し、かつ接触界面で
の熱抵抗,電気抵抗を低減できる方法を提供するもので
ある。
On the other hand, the above-described method of sandwiching a soft metal sheet disclosed as a method for coping with the problem of uniform contact between chips in a multi-chip parallel type pressure contact type semiconductor device is as follows.
According to the study of the present inventors, at least in a practical pressure range where the semiconductor chip is not destroyed, the deformation amount is very small (only deformation due to elastic deformation), and the height between the chips (and the intermediate electrode member sandwiching the chip is reduced). It was found that when the variation in height included was large, the thickness variation absorption capacity was insufficient. When applying pressure in the thickness direction to the soft metal sheet surface to cause plastic deformation in the horizontal direction, the frictional force (friction resistance) generated at the interface between the soft metal sheet and the electrode member sandwiches the soft metal material. Is considered to be due to the fact that the deformation resistance in the lateral direction becomes extremely large. Even if the pressing force is increased for deformation, the plastic deformation does not easily occur because the frictional force also increases in proportion to the pressure. Especially when the thickness is very small compared to the area receiving the resistance like the sheet shape, the influence of the frictional force generated on this surface becomes dominant, so it exceeds the yield stress of commonly known materials Even if pressure is applied, practically no plastic deformation (flow) occurs, and the thickness of the soft metal sheet hardly changes. A first object of the present invention is to increase the size of a package by increasing the diameter of a wafer as described above, and to increase the number of chips in a large area, which becomes increasingly difficult with the parallelization of elements corresponding to the increase in capacity. A method of ensuring a uniform pressure contact state, that is, variations in the height of the contact surface (warpage, undulation,
It is intended to provide a method capable of absorbing thermal resistance and electrical resistance at the contact interface by absorbing variation in member dimensions.

【0010】本発明の第2の目的は上記により得られる
半導体装置を用いることにより、特に大容量のシステム
に好適な変換器を提供することにある。
A second object of the present invention is to provide a converter particularly suitable for a large-capacity system by using the semiconductor device obtained as described above.

【0011】[0011]

【課題を解決するための手段】上記課題は、少なくとも
第一主面に第一の主電極、第二主面に第二の主電極を有
する半導体素子の各主面上に中間電極を配置し、さらに
これらを一対の主電極板の間に組み込んだ圧接型半導体
装置において、上記半導体素子の主電極と中間電極板の
少なくとも一方が複数の金属バンプによって接合された
構造とすることにより実現できる。
SUMMARY OF THE INVENTION The object of the present invention is to provide a semiconductor device having at least a first main electrode on a first main surface and a second main electrode on a second main surface, wherein an intermediate electrode is arranged on each main surface. Further, in a press-contact type semiconductor device in which these are incorporated between a pair of main electrode plates, it can be realized by a structure in which at least one of the main electrode and the intermediate electrode plate of the semiconductor element is joined by a plurality of metal bumps.

【0012】[0012]

【発明の実施の形態】本発明の実施の代表的な形態を図
面に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described with reference to the drawings.

【0013】図1に圧接型半導体装置の基本構成に対し
て本発明を適用した例を示す。圧接型の半導体装置にお
いては、半導体チップ、またはウエハ1の第一主面に第
一の主電極2、第二主面に第二の主電極3が形成され、
このウエハ1の第一主面に第一の主電極2とMoやWか
らなる中間電極板4とが金属バンプ7によって接合され
たアセンブリが配置され、さらにこの中間電極板の外側
部分に一対のCuの主電極板8,9が配置されて、一括
に加圧されて各部材間が接触される圧接型半導体装置で
ある。
FIG. 1 shows an example in which the present invention is applied to the basic structure of a pressure contact type semiconductor device. In a press-contact type semiconductor device, a first main electrode 2 is formed on a first main surface of a semiconductor chip or a wafer 1, and a second main electrode 3 is formed on a second main surface.
An assembly in which a first main electrode 2 and an intermediate electrode plate 4 made of Mo or W are joined to each other by a metal bump 7 on a first main surface of the wafer 1 is further provided. This is a pressure-contact type semiconductor device in which Cu main electrode plates 8 and 9 are arranged, and are pressed together and each member is brought into contact.

【0014】本発明では、この形態において形成される
界面のうち、上記ウエハ1の第一主面に第一及び第二の
主電極2及び3とMoやWからなる中間電極板4,5と
が接合された構造であり、とくに上記ウエハ1の第一主
面に第一の主電極2とMoやWからなる中間電極板4と
が複数の金属バンプ7によって接合され、上記主電極板
8,9と中間電極板4,5のそれぞれ対向して圧接され
る構造であることを特徴とする。
In the present invention, among the interfaces formed in this embodiment, the first and second main electrodes 2 and 3 and the intermediate electrode plates 4 and 5 made of Mo or W are formed on the first main surface of the wafer 1. The first main electrode 2 and the intermediate electrode plate 4 made of Mo or W are bonded to the first main surface of the wafer 1 by a plurality of metal bumps 7, and the main electrode plate 8 , 9 and the intermediate electrode plates 4, 5 are pressed against each other.

【0015】この状態で加圧力が加えられると(下
図)、上記ウエハ1の第一主面に第一の主電極2とMo
やWからなる中間電極板4とを接合している複数の金属
バンプ7が圧縮変形し、上記中間電極板4,5と主電極
板8,9の表面と接触し、2面間の良好なコンタクトが
完了する。
When a pressing force is applied in this state (shown below), the first main electrode 2 and Mo are applied to the first main surface of the wafer 1.
The plurality of metal bumps 7 joining the intermediate electrode plate 4 made of W and W are compressed and deformed, and come into contact with the surfaces of the intermediate electrode plates 4 and 5 and the main electrode plates 8 and 9 to provide a good contact between the two surfaces. Contact is completed.

【0016】本発明では、上記ウエハ1の第一主面に第
一の主電極2とMoやWからなる中間電極板4とが複数
の金属バンプ7によって接合された構造であるため、接
合時に中間電極板4,5の平行度を補正するとともに接
触面の高さのばらつき(反り,うねり,部材寸法ばらつ
き等による)を吸収し、かつ接触界面が少なくなるため
熱抵抗,電気抵抗を低減できる。また圧接型半導体装置
に印加する圧接力も低減できる。
The present invention has a structure in which the first main electrode 2 and the intermediate electrode plate 4 made of Mo or W are bonded to the first main surface of the wafer 1 by a plurality of metal bumps 7. The parallelism of the intermediate electrode plates 4 and 5 is corrected, and variations in the height of the contact surface (due to warpage, undulation, variations in member dimensions, etc.) are absorbed, and the number of contact interfaces is reduced, so that thermal resistance and electrical resistance can be reduced. . Further, the pressing force applied to the pressing-type semiconductor device can be reduced.

【0017】図2に本発明の圧接型半導体装置の製造過
程をモデル図として示した。図2では、(a)はウエハ
1の第二主面に第二の主電極3とMoやWからなる中間
電極板5とを熱圧着によって接合された状態、(b)は
中間電極板4にボンディングによって複数の金属バンプ
7を形成した状態、(c)はウエハ1の第一主面に第一
の主電極2とMoやWからなる中間電極板4の複数の金
属バンプ7とを熱圧着によって接合された状態を示して
いる。
FIG. 2 is a model diagram showing a process of manufacturing the press contact type semiconductor device of the present invention. 2A shows a state in which the second main electrode 3 and an intermediate electrode plate 5 made of Mo or W are joined to the second main surface of the wafer 1 by thermocompression bonding, and FIG. (C) heats the first main electrode 2 and the plurality of metal bumps 7 of the intermediate electrode plate 4 made of Mo or W on the first main surface of the wafer 1. The state joined by crimping is shown.

【0018】図3には、図2の変形例として、(a)は
ウエハ1の第二主面に第二の主電極3とMoやWからな
る中間電極板5とを熱圧着によって接合された状態、
(b)はさらにウエハ1の第一主面に第一の主電極2に
ボンディングによって複数の金属バンプ7を形成した状
態、(c)はウエハ1の第一主面に第一の主電極2にボ
ンディングによって設けた複数の金属バンプ7とMoや
Wからなる中間電極板4とを熱圧着によって接合された
状態を示している。
FIG. 3 shows, as a modification of FIG. 2, (a) a second main electrode 3 and an intermediate electrode plate 5 made of Mo or W joined to the second main surface of the wafer 1 by thermocompression bonding. State,
(B) shows a state in which a plurality of metal bumps 7 are formed on the first main surface of the wafer 1 by bonding to the first main electrode 2, and (c) shows a state where the first main electrode 2 is formed on the first main surface of the wafer 1. 2 shows a state in which a plurality of metal bumps 7 provided by bonding and an intermediate electrode plate 4 made of Mo or W are joined by thermocompression bonding.

【0019】図2,図3によれば、図2,図3(a)に
示すように、ウエハ1の第二主面に第二の主電極3とM
oやWからなる中間電極板5とを熱圧着によって接合さ
れる。次に、図2,図3(b)に示すように、中間電極
板4またはウエハ1の第一主面に第一の主電極2にボン
ディングによって複数の金属バンプ7を設ける。さら
に、図2,図3(c)に示すように、ボンディングによ
って設けた複数の金属バンプ7を介して、中間電極板4
と第一主面に第一の主電極2とを熱圧着または超音波ボ
ンディングによって接合し、アセンブリを製造する。
According to FIGS. 2 and 3, as shown in FIGS. 2 and 3A, the second main electrode 3 and the M
The intermediate electrode plate 5 made of o or W is joined by thermocompression bonding. Next, as shown in FIGS. 2 and 3 (b), a plurality of metal bumps 7 are provided on the first main electrode 2 on the intermediate electrode plate 4 or the first main surface of the wafer 1 by bonding. Further, as shown in FIGS. 2 and 3 (c), the intermediate electrode plate 4 is provided via a plurality of metal bumps 7 provided by bonding.
And the first main electrode 2 on the first main surface by thermocompression bonding or ultrasonic bonding to manufacture an assembly.

【0020】このアセンブリは、複数の金属バンプ7が
接合時に変形し、アセンブリ全体の平行度を補正すると
ともに接合部が形成されるため従来よりも接触界面が少
なくなるため熱抵抗,電気抵抗を低減できる。また金属
バンプ7の数をさらに増加させると熱抵抗,電気抵抗が
低減できる。
In this assembly, a plurality of metal bumps 7 are deformed at the time of joining, correct the parallelism of the whole assembly and form a joint, so that the number of contact interfaces is smaller than in the prior art, so that thermal resistance and electric resistance are reduced. it can. Further, when the number of the metal bumps 7 is further increased, the thermal resistance and the electric resistance can be reduced.

【0021】最終的には金属バンプ7の変形が十分に起
こって、接合界面が完全に埋る状態まで変形させること
も可能であるが、現実には荷重の制限により完全に埋め
ることは不可能で、未接触部分が残るが電気抵抗等には
問題が生じない。
Finally, it is possible to deform the metal bumps 7 sufficiently to completely fill the bonding interface, but in reality, it is impossible to completely fill them due to the limitation of the load. Thus, a non-contact portion remains, but there is no problem in electrical resistance and the like.

【0022】上記より、半導体装置の使用形態に応じ
て、熱抵抗,電気抵抗の低減、または変形能の向上のど
ちらを優先するかによって、最適な金属バンプ7の数及
び厚さ方向の変形量を選択するのが好ましい。
As described above, the optimum number of metal bumps 7 and the amount of deformation in the thickness direction depend on whether the thermal resistance, the electric resistance, or the improvement of the deformability is prioritized according to the usage mode of the semiconductor device. It is preferred to select

【0023】金属バンプは、必要な熱抵抗,電気抵抗,
高さ変化量により最適な値、方法に決定される。金属バ
ンプの材料は金,銀,銅,アルミニウム,ニッケルある
いははんだ等の軟質金属よりなっており、特に変形が起
こりやすいので好適である。特に、芯材が可塑性樹脂か
らなり、表面層が金属からなる複合構造の金属バンプに
すると、芯材が可塑性樹脂であるため、主電極板に加え
た荷重を除去しても復元することから再使用が可能とな
る。
The metal bumps have the necessary thermal resistance, electrical resistance,
The optimum value and method are determined according to the height change amount. The material of the metal bump is made of a soft metal such as gold, silver, copper, aluminum, nickel or solder, and is particularly preferable because it is easily deformed. In particular, if the core material is made of a plastic resin and the surface layer is made of a metal bump having a composite structure made of a metal, the core material is a plastic resin. It can be used.

【0024】例えば、前述の圧接型パッケージに複数個
の半導体チップを並列に組み込む場合には、本発明のア
センブリを用いるとアセンブリの寸法精度(高さ方向)
が良いため好適である。
For example, when a plurality of semiconductor chips are incorporated in parallel in the above-mentioned press-contact type package, the dimensional accuracy (in the height direction) of the assembly can be obtained by using the assembly of the present invention.
Is preferable because it is good.

【0025】図4に圧接型半導体装置の基本構成に対し
て本発明を応用した例を示す。圧接型の半導体装置にお
いては、半導体チップ、またはウエハ1の第一主面に第
一の主電極2、第二主面に第二の主電極3が形成され、
この両電極面とMoやWからなる中間電極板4,5とが
金属バンプ7によって接合されたアセンブリが配置さ
れ、さらにこの中間電極板の外側部分に一対のCuの主
電極板8,9が配置されて、一括に加圧されて各部材間
が接触される圧接型半導体装置である。
FIG. 4 shows an example in which the present invention is applied to the basic structure of a pressure contact type semiconductor device. In a press-contact type semiconductor device, a first main electrode 2 is formed on a first main surface of a semiconductor chip or a wafer 1, and a second main electrode 3 is formed on a second main surface.
An assembly in which the two electrode surfaces and the intermediate electrode plates 4 and 5 made of Mo or W are joined by a metal bump 7 is arranged. Further, a pair of Cu main electrode plates 8 and 9 are provided on the outer portion of the intermediate electrode plate. This is a press-contact type semiconductor device which is arranged, pressurized at once, and brought into contact with each other.

【0026】本発明では、この形態において形成される
界面のうち、上記ウエハ1の第一主面に第一の主電極
2,3とMoやWからなる中間電極板4,5とが接合さ
れた構造であり、とくに上記ウエハ1の両電極面2,3
とMoやWからなる中間電極板4,5とが複数の金属バ
ンプ7によって接合され、上記主電極板8,9と中間電
極板4,5のそれぞれ対向して圧接される構造であるこ
とを特徴とする。
In the present invention, of the interfaces formed in this embodiment, the first main electrodes 2 and 3 and the intermediate electrode plates 4 and 5 made of Mo or W are joined to the first main surface of the wafer 1. In particular, both electrode surfaces 2 and 3 of the wafer 1 are
And the intermediate electrode plates 4 and 5 made of Mo or W are joined by a plurality of metal bumps 7, and the main electrode plates 8 and 9 and the intermediate electrode plates 4 and 5 are pressed against each other. Features.

【0027】本発明の圧接型半導体装置を用いると、動
作時の圧接力を従来の圧接型半導体装置よりも低減でき
る。
When the press-contact type semiconductor device of the present invention is used, the press-contact force during operation can be reduced as compared with the conventional press-contact type semiconductor device.

【0028】図5は、IGBT10を用いたスイッチングデバ
イスと逆並列に接続したフライホイールダイオード(F
WD)11を組み込んだ逆導通型スイッチングデバイス
に適用した例を示したものである。図5には、右端の圧
接型半導体装置の最外部から中央に向かった途中までの
一部断面を示している。IGBTチップ10には上面側
の第一主面のほぼ全面にエミッタ電極12、下面側の第
二主面にはコレクタ電極13が形成されており、さらに
第一主面には制御用電極(ゲート電極)14が形成され
ている。また、FWD11には、シリコン基板の上面側
にアノード電極15、下面側にカソード電極16が形成
されている。
FIG. 5 shows a flywheel diode (F) connected in anti-parallel with a switching device using IGBT10.
This shows an example in which the present invention is applied to a reverse conduction type switching device incorporating WD) 11. FIG. 5 shows a partial cross section from the outermost part of the press-contact type semiconductor device at the right end to the middle toward the center. The IGBT chip 10 has an emitter electrode 12 formed on almost the entire first main surface on the upper surface side and a collector electrode 13 on the second main surface on the lower surface side, and further has a control electrode (gate) on the first main surface. An electrode 14 is formed. In the FWD 11, an anode electrode 15 is formed on the upper surface side of the silicon substrate, and a cathode electrode 16 is formed on the lower surface side.

【0029】これらの各半導体チップには、放熱と電気
的接続を兼ねたMoからなる中間電極4,5がチップ上
の各主電極と金属バンプ7及び接合層6によって接合さ
れており、これらがさらに第1の共通主電極板(Cu)8
と第2の共通主電極板(Cu)9に挟まれている。
In each of these semiconductor chips, intermediate electrodes 4 and 5 made of Mo for both heat dissipation and electrical connection are joined to the main electrodes on the chip by metal bumps 7 and joining layers 6, respectively. Further, a first common main electrode plate (Cu) 8
And a second common main electrode plate (Cu) 9.

【0030】ちなみに共通主電極8,9と中間電極4,
5との接触面はRmax 1μmの加工が施されている。
Incidentally, the common main electrodes 8, 9 and the intermediate electrodes 4,
The surface contacting with No. 5 is Rmax 1 μm.

【0031】上記半導体チップ、及び中間電極はテフロ
ン枠17により互いに固定されている。また、IGBT
チップ10のスプリングピンによるゲート電極からはゲ
ート電極配線板19に接続され、ワイヤボンド18によ
り接続端子20配線が引き出され、ゲート電極配線は外
筒21を貫通するシールされた配線22によりパッケー
ジ外に引き出される。上記一対の共通主電極板8,9の
間は、セラミック製等の絶縁性の外筒21により外部絶
縁され、さらに共通主電極板8,9と絶縁外筒21の間
をフランジ23によりパッケージ内部をシール封止した
ハーメチック構造となっている。
The semiconductor chip and the intermediate electrode are fixed to each other by a Teflon frame 17. Also, IGBT
The gate electrode is connected to the gate electrode wiring board 19 by the spring pin of the chip 10, the connection terminal 20 wiring is drawn out by the wire bond 18, and the gate electrode wiring is put out of the package by the sealed wiring 22 penetrating the outer cylinder 21. Drawn out. The space between the pair of common main electrode plates 8 and 9 is externally insulated by an insulating outer cylinder 21 made of ceramic or the like, and the space between the common main electrode plates 8 and 9 and the insulating outer cylinder 21 is inside the package by a flange 23. Is hermetically sealed.

【0032】そこで中間電極板と主電極板間の加圧力を
0.3kg/mm2にしてオン電圧を測定した結果、従来の圧
接構造の半導体装置に比べて電気抵抗が約30%低減す
ることができた。また熱抵抗も約20%低減した。
Then, the on-voltage was measured with the applied pressure between the intermediate electrode plate and the main electrode plate being 0.3 kg / mm 2. As a result, it was found that the electric resistance was reduced by about 30% as compared with the conventional semiconductor device having the pressure contact structure. Was completed. Also, the thermal resistance was reduced by about 20%.

【0033】上記中間電極の材料としては、熱膨張係数
がSiと外部主電極材料の中間で、熱伝導性,電気伝導
性の良好な材料が用いられる。具体的にはタングステン
(W)やモリブデン(Mo)等の単体金属、またはそれら
を主たる構成材料とするCu−W,Ag−W,Cu−M
o,Ag−Mo,Cu−FeNi等の複合材料または合
金、さらには金属とセラミックスやカーボンとの複合材
料、たとえばCu/SiC,Cu/C,Al/SiC,
Al/AlN等が好ましい。
As the material of the intermediate electrode, a material having a thermal expansion coefficient between Si and the external main electrode material and having good thermal conductivity and electric conductivity is used. Specifically, tungsten
Metal such as (W) and molybdenum (Mo), or Cu-W, Ag-W, Cu-M using them as main constituent materials
o, Ag-Mo, Cu-FeNi or other composite materials or alloys, and further, composite materials of metals and ceramics or carbon, such as Cu / SiC, Cu / C, Al / SiC,
Al / AlN and the like are preferable.

【0034】一方、主電極には電気伝導性で熱伝導性の
良い銅やアルミニウム、またはそれらを含む前述のよう
な合金または複合材料を使用するのが好ましい。
On the other hand, it is preferable to use copper or aluminum having good electrical conductivity and thermal conductivity, or the above-mentioned alloy or composite material containing them for the main electrode.

【0035】本発明のアセンブリ実装方式は、もちろん
ダイオードを含まないIGBT等のスイッチング半導体
のみからなる圧接型半導体装置にも用いることができる
他、例えばダイオードチップのみを多数個上記の方法で
圧接型パッケージに実装することももちろん有効であ
る。また、上記実施例では、制御電極付き半導体素子と
してIGBTを用いて説明したが、本発明は少なくとも
第一主面に第一の主電極と第二主面に第二の主電極を有
する半導体素子全般を対象としており、IGBT以外の
絶縁ゲート形トランジスタ(MOSトランジスタ)や、
IGCT(Insulated Gate Controlled Thyristor )な
どを含む絶縁ゲート形サイリスタ(MOS制御サイリス
タ)などの制御電極付き半導体素子、及びダイオードな
どに対しても同様に実施できる。また、Si素子以外の
SiC,GaNなどの化合物半導体素子に対しても同様
に有効である。
The assembly mounting system of the present invention can be used for a pressure-contact type semiconductor device consisting of only a switching semiconductor such as an IGBT without a diode. Of course is also effective. In the above embodiments, the IGBT is used as the semiconductor device with the control electrode. However, the present invention provides a semiconductor device having at least a first main electrode on a first main surface and a second main electrode on a second main surface. It is intended for the whole, including insulated gate transistors (MOS transistors) other than IGBTs,
The present invention can be similarly applied to a semiconductor element with a control electrode such as an insulated gate thyristor (MOS control thyristor) including an IGCT (Insulated Gate Controlled Thyristor), a diode, and the like. Further, the present invention is similarly effective for compound semiconductor devices such as SiC and GaN other than the Si device.

【0036】本発明の圧接型半導体装置では、大型化し
ても安定した電極間の接触界面が得られるため、電気抵
抗,熱抵抗の小さな半導体装置が得られる。従って、こ
の圧接型半導体装置を用いることにより、変換器容積、
及びコストを大幅に削減した大容量変換器が実現できる
ようになる。また本発明によれば、従来より低い加圧力
でも均一な接触が得られるので、上記スタック構造等を
簡略化できるという効果もある。
In the pressure contact type semiconductor device of the present invention, a stable contact interface between the electrodes can be obtained even when the size is increased, so that a semiconductor device having a small electric resistance and a small thermal resistance can be obtained. Therefore, by using this press-contact type semiconductor device, the converter volume,
In addition, a large-capacity converter whose cost is greatly reduced can be realized. Further, according to the present invention, uniform contact can be obtained even with a lower pressing force than in the prior art, so that the stack structure and the like can be simplified.

【0037】本発明の圧接型半導体装置は、上記の例に
限らず電力系統に用いられる自励式大容量変換器やミル
用変換器として用いられる大容量変換器に特に好適で、
可変速揚水発電,ビル内変電所設備,電鉄用変電設備,
ナトリウム硫黄(NaS)電池システム,車両等の変換
器にも用いることができる。
The pressure-contact type semiconductor device of the present invention is not particularly limited to the above example, and is particularly suitable for a self-excited large-capacity converter used in a power system or a large-capacity converter used as a converter for a mill.
Variable speed pumped storage power generation, substation facilities in buildings, substation facilities for railways,
It can also be used in converters for sodium-sulfur (NaS) battery systems and vehicles.

【0038】[0038]

【発明の効果】本発明によれば、ウエハの大口径化によ
るパッケージの大型化や、大容量化に対応する素子の多
チップ並列化に伴って、ますます困難になる大面積域で
の均一圧接を比較的低圧力で簡単に実現することができ
る、すなわち接触面の高さのばらつきを十分に吸収し、
かつ接触界面での熱抵抗,電気抵抗を低減できる。
According to the present invention, uniformity over a large area becomes increasingly difficult with the increase in the size of the package due to the increase in the diameter of the wafer and the parallelization of elements corresponding to the increase in the capacity. Pressure welding can be easily realized with relatively low pressure, that is, it absorbs variations in the height of the contact surface sufficiently,
In addition, the thermal resistance and electric resistance at the contact interface can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例として示した圧接型半導体装置
の断面図。
FIG. 1 is a sectional view of a press-contact type semiconductor device shown as an embodiment of the present invention.

【図2】図1の圧接型半導体装置の製造過程を説明する
図。
FIG. 2 is a view for explaining a manufacturing process of the press-contact type semiconductor device of FIG. 1;

【図3】図1の圧接型半導体装置の製造過程を説明する
図。
FIG. 3 is a view for explaining a manufacturing process of the press contact type semiconductor device of FIG. 1;

【図4】本発明の圧接型半導体装置の応用例を示す断面
図。
FIG. 4 is a cross-sectional view showing an application example of the press contact type semiconductor device of the present invention.

【図5】本発明の実施例として示すIGBTの断面図。FIG. 5 is a cross-sectional view of an IGBT shown as an example of the present invention.

【符号の説明】[Explanation of symbols]

1…ウエハ、2,3…第一及び第二主電極、4,5…中
間電極板、6…接合層、7…金属バンプ、8,9…主電
極板、10…IGBT、11…フライホイールダイオー
ド、12…エミッタ電極、13…コレクタ電極、14…
ゲート電極、15…アノード電極、16…カソード電
極、17…テフロン枠、18…ワイヤボンド、19…ゲ
ート電極配線板、20…接続端子、21…絶縁外筒、2
2…気密貫通配線、23…フランジ。
DESCRIPTION OF SYMBOLS 1 ... Wafer, 2, 3 ... 1st and 2nd main electrode, 4, 5 ... Intermediate electrode plate, 6 ... Bonding layer, 7 ... Metal bump, 8, 9 ... Main electrode plate, 10 ... IGBT, 11 ... Flywheel Diode, 12: Emitter electrode, 13: Collector electrode, 14 ...
Gate electrode, 15: Anode electrode, 16: Cathode electrode, 17: Teflon frame, 18: Wire bond, 19: Gate electrode wiring board, 20: Connection terminal, 21: Insulated outer cylinder, 2
2: airtight through wiring, 23: flange.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 澤畠 守 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Mamoru Sawahata 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】第一主面に第一の主電極、第二主面に第二
の主電極を有する半導体素子の各主面上に中間電極板を
配置し、さらにこれらが一対の主電極板の間に組み込ま
れた圧接型半導体装置において、半導体素子の主電極と
中間電極板の少なくとも一方が複数の金属バンプによっ
て接合されたことを特徴とする圧接型半導体装置。
An intermediate electrode plate is disposed on each of the main surfaces of a semiconductor device having a first main electrode on a first main surface and a second main electrode on a second main surface. A press-contact type semiconductor device incorporated between plates, wherein at least one of a main electrode of a semiconductor element and an intermediate electrode plate is joined by a plurality of metal bumps.
【請求項2】前記金属バンプはAg,Ag合金、Au,
Au合金、Cu,Cu合金、Al,Al合金、Ni,N
i合金、はんだのいずれかであることを特徴とする請求
項1記載の圧接型半導体装置。
2. The method according to claim 1, wherein the metal bumps are made of Ag, Ag alloy, Au,
Au alloy, Cu, Cu alloy, Al, Al alloy, Ni, N
2. The pressure-contact type semiconductor device according to claim 1, wherein the semiconductor device is one of an i-alloy and a solder.
【請求項3】前記第一主面に第一の主電極、第二主面に
第二の主電極を有する半導体素子が、複数個並置されて
一対の主電極板の間に組み込まれていることを特徴とす
る請求項1記載の圧接型半導体装置。
3. A semiconductor device having a first main electrode on the first main surface and a second main electrode on a second main surface, wherein a plurality of semiconductor elements are juxtaposed and incorporated between a pair of main electrode plates. 2. The pressure-contact type semiconductor device according to claim 1, wherein:
【請求項4】前記半導体素子が第一主面に第一主電極と
制御電極、第二主面に第二主電極を有する絶縁ゲート形
素子であり、さらに同一の圧接型パッケージ内には第一
主面に第一主電極、第二主面に第二主電極を有するフラ
イホイールダイオードを、上記絶縁ゲート形素子と逆並
列に各々複数個ずつ組み込んだことを特徴とする請求項
1記載の圧接型半導体装置。
4. The semiconductor device is an insulated gate device having a first main electrode and a control electrode on a first main surface, and a second main electrode on a second main surface. 2. A flywheel diode having a first main electrode on one main surface and a second main electrode on a second main surface, and a plurality of flywheel diodes are respectively incorporated in anti-parallel with the insulated gate element. Pressure contact type semiconductor device.
JP25644197A 1997-09-22 1997-09-22 Pressure joint semiconductor device Pending JPH1197463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25644197A JPH1197463A (en) 1997-09-22 1997-09-22 Pressure joint semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25644197A JPH1197463A (en) 1997-09-22 1997-09-22 Pressure joint semiconductor device

Publications (1)

Publication Number Publication Date
JPH1197463A true JPH1197463A (en) 1999-04-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP25644197A Pending JPH1197463A (en) 1997-09-22 1997-09-22 Pressure joint semiconductor device

Country Status (1)

Country Link
JP (1) JPH1197463A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093855A (en) * 2000-09-18 2002-03-29 Toshiba Corp Semiconductor device
JP2009267246A (en) * 2008-04-28 2009-11-12 Honda Motor Co Ltd Pressure contact semiconductor device
CN113078090A (en) * 2021-03-23 2021-07-06 长江存储科技有限责任公司 Wafer preparation method, bonding device and bonding equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002093855A (en) * 2000-09-18 2002-03-29 Toshiba Corp Semiconductor device
JP2009267246A (en) * 2008-04-28 2009-11-12 Honda Motor Co Ltd Pressure contact semiconductor device
CN113078090A (en) * 2021-03-23 2021-07-06 长江存储科技有限责任公司 Wafer preparation method, bonding device and bonding equipment
CN113078090B (en) * 2021-03-23 2024-04-12 长江存储科技有限责任公司 Wafer preparation method, bonding device and bonding equipment

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