JPH10301543A - Driving device for liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make write-in and read-out operations with respect to respective blocks performed in good order by generating the destinations to be written to and to read from of data in the block of a memory and mediating a write operation to the memory and a read-out operation from the memory. SOLUTION: A write address generator 70 generates a write address signal 212 for writing data by using a frame signal for write-out 206 from a frame signal generator 60. A read address generator 80 generates a read address signal 213 for reading data by using a frame signal for read-out 207 from the frame signal generator 60. A memory control signal generator 90 generates a memory address signal 215 to output to memory devices while properly changing over the write address signal 212 and the read address signal 213 and a memory device control signal 214 for write or read-out.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a liquid crystal display device which is suitable for driving a liquid crystal display device which responds at high speed. In particular, the present invention relates to a driving device suitable for a liquid crystal display device driven by a multiple line simultaneous selection method.

[0002]

2. Description of the Related Art An STN liquid crystal element is a liquid crystal display element which responds depending on the effective value of an applied voltage. A phenomenon that the change is small and the contrast is reduced, that is, a so-called frame response occurs. Therefore, if a simple line-sequential driving method is used to drive the liquid crystal display element, there is a limit in increasing the speed of driving the STN liquid crystal element.

In order to drive the STN liquid crystal element at a higher speed, a multiple line simultaneous selection method (MLA method) has been proposed. The MLA method is a method in which a plurality of scanning electrodes (row electrodes) are collectively selected and driven. In the MLA method, a predetermined voltage pulse train is applied to each of the simultaneously driven row electrodes in order to independently control a column display pattern supplied to data electrodes (column electrodes). A voltage pulse voltage group (selection pulse group) applied to each row electrode can be represented by a matrix of L rows and K columns. Hereinafter, this matrix is referred to as a selection matrix (A).
L is the number of simultaneous selections. The voltage pulse voltage group is represented as a group of vectors orthogonal to each other. Therefore, a matrix including those vectors as elements is an orthogonal matrix. Each row vector in the matrix is orthogonal to each other. In the orthogonal matrix, each row corresponds to each line of the liquid crystal display device. For example, the first element of the selection matrix (A) is applied to the first line of the L selection lines. That is, the selection pulse is applied to the first row electrode in the order of the first column element and the second column element.

FIG. 16 is an explanatory diagram showing how to determine the sequence of the voltage waveform applied to the column electrode. Here, a Hadamard matrix of 4 rows and 4 columns is taken as an example of the selection matrix (A). In the selection matrix (A) in FIG. 16, "1" means a positive selection pulse, and "-1" means a negative selection pulse. It is assumed that the display data to be displayed on the column electrodes i and j are as shown in FIG. Then
The column display pattern is represented by a vector (d) as shown in FIG. In FIG. 16B, “−1” corresponds to ON display, and “1” corresponds to OFF display. The voltage pattern to be sequentially applied to the column electrodes i and j is shown in FIG.
Vector (v) shown in (b) is obtained. This vector corresponds to a vector obtained by performing an exclusive OR operation on a column display pattern (image display pattern) and a corresponding row selection pattern for each bit, and calculating the sum of the results. The waveform is as shown in FIG.
In FIG. 16C, the vertical axis represents the voltage applied to the column electrodes, and the horizontal axis represents time, but the units are arbitrary.

When driving a liquid crystal display device by the MLA method, in order to suppress the frame response of the liquid crystal display element,
It is desirable that the voltage applying elements are dispersed within one display cycle. For this purpose, specifically, for example, the first element of the vector (v) for the first row electrode group (hereinafter, referred to as a subgroup) selected at the same time is applied, and then, the first row electrode group is simultaneously selected. A sequence is executed such that the first element is applied to the second sub-group.

Incidentally, the basic pulse width of the waveform for driving the liquid crystal display element is often determined to be about 10 to several tens μsec from the viewpoint of the degree of multiplexing of the scanning lines and the visibility of the display. Therefore, the frequency of one display cycle on the liquid crystal display element side is often about 70 to 200 Hz. On the other hand, the frequency of an input image signal is often about 60 Hz. Therefore, in the liquid crystal driving device, it is necessary to adjust the speed of the input signal and the speed of the signal output to the liquid crystal display element side.

This adjustment is generally realized by a memory. That is, it is realized by writing the input image data into the memory once and reading out the written data asynchronously with the writing operation. For example, when the frequency of the input image signal is 60 Hz and the frequency of one display cycle on the liquid crystal display element side is 120 Hz, two readings are performed from the memory for writing data of one screen. Need to be In the case of the MLA method, it is necessary to handle one screen of data K times. Therefore, for writing one screen of data to the memory, it is necessary to read 2K times from the memory.

In the MLA method, the same display data is distributed and used a plurality of times during a display frame period. Therefore, it is necessary to keep the same data for a certain period,
It is essential to have a memory. Therefore, it is necessary to prepare more memory as the amount of display information increases, and a new memory control method is required to apply the MLA method to high-density display such as VGA, SVGA, and XGA. Come.

The prior art relating to the memory control method will be described. Here, FRC (Fra
A system that adopts the “me Rate Control” method and does not use amplitude modulation, pulse width modulation, or the like will be described as an example. In the line sequential driving method (APT or IAPT), which is a conventional STN driving method, the display data of each pixel is used only once in a display frame. Therefore, when the input frame and the output frame are synchronized, the display is possible if there is a memory having the following size, and data can be managed by simple memory management.

Input frame = output Input = 2 output frames 1 screen drive Memory not required 2 screens memory 2 screens drive 1/2 screen memory 1/2 screen memory

In this table, one-screen drive refers to a drive method for scanning the screen in one continuous scan, and two-screen drive refers to drive for scanning the upper and lower sides of the screen in independent one scans. Method. "Input = 2 output frames"
Means that one input frame corresponds to two output frames, but the data output in the output frame is FRC
The two frames differ from each other due to the gradation processing.

In general, in one screen driving of the line sequential driving method,
When the length of the frame to be written to the memory is set to be n times the length of the frame to be read from the memory (n is a natural number), the drive can be performed by preparing a memory for n screens. This is because the process of writing the next data to the memory can be performed immediately after reading the data from the memory once.
In particular, when the output frame and the input frame match, the speed of reading from the memory and the speed of writing to the memory match, which is a special case in which the memory for one screen can be further omitted. That is, if the output frame matches the input frame, no memory is required. However, even in this case, the asynchronous type in which the input frame and the output frame are not synchronized requires a memory for one screen.
When two-screen driving is performed, the phase is shifted by a half cycle between the upper screen and the lower screen as compared with the case of one-screen driving, so that a half screen can be saved. In particular, when one input frame corresponds to two output frames, since the speed of reading from the memory and the speed of writing to the memory match, a special case in which the memory for one screen can be further omitted is obtained. All you need is enough memory.

On the other hand, in the MLA method, the data of each pixel is repeated several times in a frame (four times when L = 4, L
= 7), the data is stored in memory as 1
It is not possible to write the next data to the memory immediately after reading the data. Therefore, it is necessary to hold the data while strictly managing the read and write of the memory,
The required amount of memory is increased as compared with the conventional driving method.

Hereinafter, a memory management method in the MLA method will be described. FIG. 17 is a block diagram illustrating an example of the liquid crystal display device 10 equipped with a driving device that realizes the MLA method. 17, the MLA driving device 11 inputs image data 100 and a control signal 101 such as a dot clock signal, a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal indicating a valid period of the image data 100.
A column data signal 102 and a column driver control signal 103 for the upper screen of the liquid crystal panel 15;
A column data signal 106 and a column driver control signal 107 for the lower screen are generated. Then, the MLA driving device 11 outputs the column data signal 102 and the column driver control signal 103 to the column driver 12 for the upper screen, and outputs the column data signal 106 and the column driver control signal 107 to the column driver 13 for the lower screen.
Further, it outputs a row selection pattern signal 104 and a row driver control signal 105 to the row driver 14. The upper screen column driver 12, the lower screen column driver 13, and the row driver 14 output a voltage corresponding to the input signal,
The voltage is applied to the column electrodes and the row electrodes of the liquid crystal panel 15.

FIG. 18 is a block diagram showing the internal configuration of the MLA driving device 11. As shown in the figure, image data 10 having gradation information input to the MLA driving device 11 is provided.
0 is input to the frame modulation circuit 21. The frame modulation circuit 21 converts the input image data 100 into 1-bit ON / OFF data for each display frame and outputs the data to the write data buffer 22. The write data buffer 22 writes data to the frame memory 23 when the input data has accumulated for a predetermined number of bits. The data written in the frame memory 23 is held here until it is read a plurality of times in order to perform MLA driving.

The data read from the frame memory 23 is input to a read data buffer 25. The read data buffer 25 converts the input data into a data format that allows the MLA operation processing in the column data signal generator 26 at the next stage. The column data signal generator 26 performs MLA arithmetic processing on the row selection pattern from the row selection pattern generator 28 and the output of the read data buffer 25, and determines the voltage level to be applied to the column electrodes of the liquid crystal panel 15. These are referred to as an upper screen column data signal 102 and a lower screen column data signal 106, respectively.
2. Output to the lower screen column driver 13. The row selection pattern 104 from the row selection pattern generator 28 is
It is supplied to the row driver 14.

The driver control signal generator 29 supplies the column driver control signal 103 to the upper screen column driver 12, the lower screen column driver 13 and the row driver 14.
107 and a row driver control signal 105 are supplied to control their driving timing. The memory control circuit 24 controls writing of data from the write data buffer 22 to the frame memory 23 and reading of data from the frame memory 23 to the read data buffer 25. The timing control circuit 27
Receives a control signal 101 such as a dot clock signal, a vertical synchronizing signal, a horizontal synchronizing signal, and a data enable signal indicating a valid period of the image data 100, and from these signals, a control signal required inside the MLA driving device 11. Generate

Next, the division of blocks in the frame memory 23 will be described. As described above, in MLA driving, data written in the frame memory 23 is read out a plurality of times, and during that time, the written data must be held. Therefore, a method of dividing the frame memory 23 into blocks for writing and blocks for reading is used. An example of the simplest block division of the frame memory 23 will be described with reference to the timing chart of FIG.

FIG. 19 is a timing chart under the following driving conditions. (1) The liquid crystal display device 10 having the MLA driving device 11
As in the configuration shown in FIG. 17, the upper half and the lower half of the display screen are of the dual scan type, which are simultaneously driven by the upper screen column driver 12 and the lower screen column driver 13, respectively. (2) As for the input image data 100 of one frame, the lower half data is transmitted following the upper half data of the display screen. (3) The frequency of the output frame is twice the frequency of the input frame. For example, input frame frequency 60
The output frame frequency is 120 Hz with respect to Hz. (4) MLA drive for simultaneous selection of four lines (L = 4). In this case, the data written in the frame memory 23 is read out four times, subjected to MLA calculation, and sent to the upper screen column driver 12 and the lower screen column driver 13. Here, the periods during which four readings are performed are referred to as one subframe, two subframes, three subframes, and four subframes.

FIG. 19A shows a vertical synchronizing signal (VSYNC) input to the MLA driving device 11 and an input frame number. (B) is an MLA driving device 1
1, image data (U is upper screen data, L is lower screen data) 100 is input. (C) shows the output frame number of the display data output from the MLA driving device 11. (D) shows the subframe number of the display data output from the MLA driving device 11. (E)-(L)
The state of the write operation and the read operation in each block when the frame memory 23 is divided into eight is shown. WR_U1 writes the data for the first frame of the upper screen, WR_U2 writes the data for the second frame of the upper screen, WR_L1 writes the data for the first frame of the lower screen, and WR_L2 writes the second frame of the lower screen. Write data. Also, R
D_1, RD_2, RD_3, and RD_4 indicate that data on the upper screen or the lower screen is read four times.

Image data 100 having gradation information input to the MLA driving device 11 is input to a frame modulation circuit 21. The frame modulation circuit 21 converts the input image data 100 into 1-bit on / off data.
In this example, since the output frame frequency is twice the input frame frequency, the frame modulation circuit 21 needs to convert the image data 100 of one input frame into 1-bit ON / OFF data of two output frames. There is. Therefore, two frames of ON / OFF signals are output from the frame modulation circuit 21.
The OFF data is output to the write data buffer 22. The write data buffer 22 writes the data into a predetermined block of the frame memory 23 when the input data has accumulated for a predetermined number of bits. Of the data of the two output frames, the data of the first output frame is written to block 1 (see (E) period of WR_U1 of block 1 in FIG. 19), and the data of the second output frame is written to block 2 (FIG. 19). 19 (F) WR_ of block 2
U2 period). When the input data changes from the data for the upper screen to the data for the lower screen, the data of the first output frame is written to the block 3 (see the period of WR_L1 of (G) block 3 in FIG. 19), and the second output frame Is written to the block 4 (refer to the period of WR_L2 of (H) block 4 in FIG. 19).

For the next input frame ((A) VSYNC input frame 2 area in FIG. 19), the data of the first output frame is written in block 5 (FIG. 19).
In (I) period of WR_U1 of block 5),
The data of the second output frame is written to the block 6 (see (J) period WR_U2 of the block 6 in FIG. 19). When the input data is changed from the data for the upper screen to the data for the lower screen, the data of the first output frame is written into the block 7 (see (K) period WR_L1 of block 7 in FIG. 19), and the second output frame is output. Is written in the block 8 (see the period of WR_L2 in (L) block 8 in FIG. 19).

In the next input frame ((A) VSYNC input frame 3 in FIG. 19), the data of the first output frame is written in block 1 and the data of the second output frame is written in block 2. And
This is the same as in the case of input frame 1.

The reading of the data written in each block is performed as follows. Reading of the upper screen data for the first output frame is started from block 1 and reading of the lower screen data is started from block 3, and reading is repeated four times from each block ((E) in FIG. 19, RD_1 to RD_1 of block 1). RD_4 and (G) period of RD_1 to RD_4 of block 3). Next, the upper screen data for the second output frame is read from block 2 and the lower screen data is read from block 4, and the reading is repeated four times from each block ((F) in FIG. 19).
RD_1 to RD_4 of block 2 and (H) period of RD_1 to RD_4 of block 4). Thereafter, FIG.
As shown in FIG. 7, reading is performed from blocks 5 and 7, and then from blocks 6 and 8.

As described above, if the frame memory 23 is composed of eight blocks with a block having a capacity of a half screen as one unit, writing and reading of data to and from the memory are performed in separate blocks. Data is not rewritten during the four reading periods.
Further, the memory control circuit 24 that controls the write operation and the read operation of each block can be realized with a simple configuration. However, in the case of this configuration, the frame memory 2
The size of 3 is equivalent to 4 screens (１ ／ screen × 8 blocks), and requires many memory devices. Therefore, there is a disadvantage that the cost of the MLA driving device 11 increases.

The example shown in FIG. 19 is an example in which the frame memory 23 is composed of eight blocks with one block having a capacity of a half screen as one unit. A case in which a frame memory is composed of 14 blocks with each block as one unit will be described. FIG.
Shows a state in which the display screen is divided into four areas, upper and lower, respectively. As shown in FIG. 20, the divided areas are defined as U1, U2,
The symbols U3, U4 and L1, L2, L3, L4 will be used. Hereinafter, a write operation and a read operation when the frame memory 23 is composed of 14 blocks will be described with reference to a timing chart of FIG.

FIG. 21A shows a vertical synchronizing signal (VSYNC) input to the MLA driving device 11 and an input frame number. (B) is an MLA driving device 1
1, image data (U is upper screen data, L is lower screen data) 100 is input. (C) shows the output frame number of the display data output from the MLA driving device 11. (D) shows the subframe number of the display data output from the MLA driving device 11. (E)-(R)
The state of the write operation and the read operation in each of the 14 blocks constituting the frame memory 23 is shown.

WR_U11, WR_U12, WR_U1
3, WR_U14 are U1, U2, U on the upper screen, respectively.
3, WR_U21, W4, indicating that the data for the first frame in the area of U4 is to be written to the frame memory 23.
R_U22, WR_U23, and WR_U24 indicate that the data for the second frame in the areas U1, U2, U3, and U4 on the upper screen are written in the frame memory 23, respectively. Also, WR_L11, WR_L12, WR_L1
3, WR_L14 are L1, L2, L on the lower screen, respectively.
3 and L4, the first frame data is written to the frame memory 23, and WR_L21, W
R_L22, WR_L23, and WR_L24 indicate that the data for the second frame in the areas of L1, L2, L3, and L4 on the lower screen is written to the frame memory 23, respectively. RD_U1, RD_U2, RD_U3, RD_U
4 indicates that the data in the areas U1, U2, U3, and U4 on the upper screen are read from the frame memory 23, respectively, and RD_L1, RD_L2, RD_L3, and RD_L4
Indicates that the data in the areas L1, L2, L3, and L4 on the lower screen are read from the frame memory 23, respectively.

First, for the U1 area on the upper screen, 2
Out of the data of one output frame, the data of the first output frame is written to the block 1 of the frame memory 23 (see (E) period of WR_U11 of the block 1 in FIG. 21), and the data of the second output frame is written to the block 6. (WR_ of (J) block 6 in FIG. 21)
U21 period). Next, regarding the area of U2, the first
The output frame data is written to block 2 (FIG. 2).
1 (refer to the period of WR_U12 of block 2), the data of the second output frame is written to block 7 ((K) of FIG. 21 WR_U2 of block 7)
2 period). Similarly, the area of U3 is written in blocks 3 and 8, and the area of U4 is written in blocks 4 and 9.

The area L1 is first written into the blocks 5 and 10 of the frame memory 23. Thereafter, as shown in FIG. 21, the data of the first output frame is sequentially written on the side of the blocks 1 to 5, and the second output data is written on the sides of the blocks 6 to 14.

Data reading is performed as follows. In the period of output frame 1 and output subframe 1,
As shown in FIG. 21, U1, U2, U3, U4 on the upper screen
As the data of the area, the second from the blocks 7, 8, 9, 10
The data of the output frame is read, and L1 and L
Blocks 2, 3, as data in the 2, L3, L4 areas
The data of the first output frame is read from 4,5.
Subsequently, in the period of the output sub-frame 2, since the writing of the data in the U1 area to the block 1 has been completed,
Data of the first output frame is read from block 1 as data of one area. Then, data of the second output frame is read from the blocks 8, 9, and 10 as data of the U2, U3, and U4 areas. In addition, L1,
The data of the second output frame is read from block 1 as the data of the L2, L3, and L4 areas,
The data of the first output frame is read from 4,5.
Thereafter, as shown in FIG. 21, writing and reading operations in each block are performed.

According to the writing operation to the frame memory 23 composed of 14 blocks and the reading operation from the frame memory 23, the data of the first output frame is written in the blocks 1 to 5, and the writing is completed. Thereafter, a read operation is performed from these blocks in the immediately next output subframe. On the other hand, in blocks 6 to 14, the data of the second output frame is written, and after reading of the data of the first output frame from blocks 1 to 5 is performed for 4 subframes, Reading of the data of the second output frame is started. In the case of this configuration, the size of the frame memory 23 is 1.75 screens (１ ／ screen × 14 blocks). That is, (1 /
In the case of the configuration of (2 screens × 8 blocks), the memory size for four screens is required, which is much smaller than that required. The smaller the amount of memory devices used, the more MLA
Since the cost of the driving device 11 is reduced, it is very effective in realizing an actual circuit device.

[0033]

However, in such a method, if the order of the write operation and the read operation for each block is not performed correctly as shown in FIG. Display occurs. Upper screen data and lower screen data are mixed between blocks,
Areas U1 to U4 and L1 to L4 for each output subframe
The data of the first output frame and the data of the second output frame are mixed. As described above, the order of writing and reading for each block is complicated, and the configuration of the memory control circuit 24 is extremely complicated. That is, the frame memory 2 in the MLA driving device 11
Frame memory 23 to minimize the size of
It is effective to divide the data into 14 blocks. However, in realizing such a system, a memory control circuit in which writing and reading with respect to each block are performed accurately and in order, and which does not require a complicated circuit. There is a problem that it is difficult to realize No. 24.

The present invention solves such a problem, and even if the frame memory is divided into a number of blocks in order to reduce the overall size as much as possible, writing and reading for each block are performed in order, and the display image is displayed. It is an object of the present invention to provide a driving device of a liquid crystal display device by an MLA driving device having a memory control circuit which does not cause a missing or an incorrect display.

[0035]

According to the present invention, there is provided a driving apparatus for a liquid crystal display device, wherein an input frame number of image data input to the liquid crystal display device and an image data currently input are input to the liquid crystal display device. A write frame / block number generating means for generating a block number indicating which area the data corresponds to when the data is divided into a plurality of areas; Reading frame number generating means for generating a reading frame number indicating a period for reading the minute once and a display frame number indicating a period for displaying one screen;
Memory control means for controlling data write from the write data buffer to the memory according to the input frame number and block number and controlling data read from the memory to the read data buffer according to the read frame number and display frame number; and writing from the write data buffer. When a request signal is input, a write enable signal that permits data output from the write data buffer to the memory is output. When a read request signal is input from the read data buffer, a read enable signal that enables data output from the memory to the read data buffer is output. Arbitration means for outputting.

The writing frame / block number generating means and the reading frame number generating means are configured to generate respective numbers from a vertical synchronizing signal input to the liquid crystal display device and a data enable signal indicating a valid period of image data. May be.

The read frame number generating means may be configured to generate a display frame number synchronized with the input frame number.

The memory control means may have a write address generating means for generating a write address for writing data from a write data buffer to a block of the memory according to the input frame number and the block number.

The memory control means may have a read address generation means for generating a read address for reading data from the block to the read data buffer according to the read frame number and the display frame number.

When a write permission signal is generated, the memory control means outputs a memory address signal and a control signal for writing to the memory device in accordance with the write address from the write address generation means, and the write operation to the memory device ends. Then, a write end signal is output, and when a read permission signal is generated, a memory address signal and a control signal for reading are output to the memory device in accordance with the read address from the read address generation means, and a read operation from the memory device is performed. A configuration may be provided that includes a memory device control unit that outputs a read end signal when the process is completed.

The write address generating means may update the write address when the write end signal is output, and the read address generating means may update the read address when the read end signal is output. .

[0042]

Embodiments of the present invention will be described below. FIG. 1 shows an MLA according to this embodiment.
It is a block diagram showing an example of memory control circuit 24A in a drive. The configuration of the liquid crystal display device according to the present embodiment is different from the conventional configuration of the MLA driving device 11, but has a configuration as shown in FIG. Is different from the conventional memory control circuit 24 in the configuration of the memory control circuit 24A,
The configuration is as shown in FIG. In this embodiment, an inexpensive DRAM is used as the frame memory 23.
Is used.

The memory control circuit 2 shown in FIG.
4A, the memory write / read arbitration circuit 50
8 arbitrates between a request for an operation of writing data from the write data buffer 22 to the frame memory 23 and a request for an operation of reading data from the frame memory 23 to the read data buffer 25. Upon receiving the memory write request signal 200 output from the write data buffer 22, the memory write / read arbitration circuit 50 returns a write enable signal 201 for permitting the write operation to the frame memory 23, and confirms that the write operation is in progress. The write cycle signal 208 shown in FIG. When a memory read request signal 202 output from the read data buffer 25 is input, a read enable signal 203 for permitting a read operation from the frame memory 23 is returned, and a read cycle signal 210 indicating that a read operation is being performed is output. Output.

The frame signal generator 60 receives a vertical synchronization signal (VSYNC) 20 inputted to the MLA driving device 11.
4. A write frame signal 206 and a read frame signal 207 are generated using a data enable signal (DE) 205 indicating a valid period of the image data 100.
The write address generator 70 includes the frame signal generator 6
A write address signal 212 for writing data to the frame memory 23 is generated using the write frame signal 206 from 0. Read address generator 80
Generates a read address signal 213 for reading data from the frame memory 23 using the read frame signal 207 from the frame signal generator 60. The memory control signal generator 90 receives the write cycle signal 208 and the read cycle signal 210 and performs a write operation and a read operation on the frame memory 23.
Then, a write end signal 209 indicating that the write operation to No. 3 has ended or a read end signal 211 indicating that the read operation from 23 to the frame memory has ended is output. Further, the memory control signal generator 90 outputs a memory address signal 215 to be output to the memory device while appropriately switching between the write address signal 212 and the read address signal 213 during a write operation or a read operation to the memory, and a write or read operation. To generate a memory device control signal 214.

Here, the frame / block number generating means and the read frame number generating means are realized by the frame signal generator 60. The memory control means is realized by a write address generator 70, a read address generator 80, and a memory control signal generator 90. The arbitration means is realized by the memory write / read arbitration circuit 50.

Next, the operation of the memory write / read arbitration circuit 50 and the memory control signal generator 90 will be described with reference to the timing chart of FIG. The image data 100 having the gradation information input to the MLA driving device 11 is shown in FIG.
As shown in FIG. 8, the signal is input to the frame modulation circuit 21.
The frame modulation circuit 21 turns on / off the input image data.
Convert to off 1-bit data. In this embodiment, it is assumed that the output frame frequency is twice the input frame frequency. Therefore, the frame modulation circuit 21 converts the image data of one input frame into 1-bit ON / OFF data of two output frames. Accordingly, on / off data for two frames is generated and output to the write data buffer 22.

The write data buffer 22 outputs a write request signal 200 when the input data has accumulated for a predetermined number of bits, for example, 40 pixels for each of RGB (see FIG. 2A). Memory write / read arbitration circuit 50
Receives a write request signal 200, returns a write enable signal 201 to the write data buffer 22, and outputs a write cycle signal 208 to the memory control signal generator 90 (see (B) and (C) in FIG. 2). ). The memory control signal generator 90 performs a write operation on the frame memory 23 when the write cycle signal 208 becomes active. At this time, the data of the two output frames are written into the predetermined memory blocks, respectively. In the first half of the write cycle, an address for writing the data for the first output frame is output, and in the latter half, the data for writing the second output frame is written. Output address (Fig. 2
WR_1st and WR_2nd periods of (I) in FIG. Also, a memory device control signal 2 such as a write signal
14 is output. When the write operation is completed, a write end signal 209 is output ((D) in FIG. 2).
reference). When the memory write / read arbitration circuit 50 receives the write end signal 209, the write cycle signal 2
08 is turned off (see (C) in FIG. 2).

Read data buffer 25 shown in FIG.
Outputs a read request signal 202 when it becomes empty. When receiving the read request signal 202 from the read data buffer 25, the memory write / read arbitration circuit 50 returns a read permission signal 203 to the read data buffer 25 unless a write operation is in progress ((E) in FIG. 2,
(F), and outputs a read cycle signal 210 to the memory control signal generator 90 (see (G) in FIG. 2). During a write operation, the memory write / read arbitration circuit 50 outputs a read enable signal 203 and a read cycle signal 210 after the operation is completed.

When the read cycle signal 210 becomes active, the memory control signal generator 90 performs a read operation from the frame memory 23. At this time, since the display data to be sent to the upper screen column driver 12 and the lower screen column driver 13 must be read from predetermined memory blocks, an address for reading the upper screen data is output in the first half of the read cycle. Then, in the latter half, an address for reading the lower screen data is output (RD_upper, RD_lo in (I) of FIG. 2).
wer period). Also, it outputs a memory device control signal 214 such as a read signal. The memory control signal generator 90 outputs four addresses in each of the periods RD_upper and RD_lower.

When the read operation is completed, the memory control signal generator 90 outputs a read end signal 211 (see (H) in FIG. 2). Upon receiving the read end signal 211, the memory write / read arbitration circuit 50 turns off the read cycle signal 210 (see (G) in FIG. 2). By the operation of the memory write / read arbitration circuit 50 and the memory control signal generation circuit 90, the writing of the first frame data and the second frame data from the write data buffer 22 to a predetermined block in the frame memory 23 is performed. The data buffer 2 is read from a predetermined block in the frame memory 23.
The reading of the display data for the upper screen and the display data for the lower screen to 5 is performed sequentially.

FIG. 3 is a block diagram showing the structure of the frame signal generator 60. The write frame synchronizing signal generator 61 receives the data enable signal (DE) 205 and the vertical synchronizing signal (VSYNC) 204 and receives the write frame counter synchronizing signal (WR_SYNC) 30.
Generates 0. The write block counter 62 determines that the DE2
05 and WR_SYNC 300, and outputs a write block count signal 301. The light frame counter A63 counts the WR_SYNC 300 to generate a light frame count A signal 302,
The write frame counter B64 is WR_SYNC300
To generate a light frame count B signal 303.

The lead frame synchronization signal generator 65
E205 and VSYNC 204 are input, and a synchronization signal (RD_SYNC) 30 for a readout frame counter is input.
4 is generated. RD_S
YNC 304 is counted and selection time timing signal 3
05, and the subframe counter 67 counts the selection time timing signal 305 to generate a subframe count signal 306. Also, the lead frame counter A68 and the lead frame counter B69
SYNC 304 and subframe count signal 306
To generate a lead frame count A signal 307 and a lead frame count B signal 308. Here, the write block count signal 301 corresponds to the block number generated by the write frame / block number generation means, and the write frame count A signal 302 and the write frame count B signal 303 are input signals generated by the write frame / block number generation means. Corresponds to the frame number. The read frame number generated by the read frame number generating means corresponds to the subframe count signal 306, and the frame count A signal 307 and the read frame count B signal 308 correspond to the display frame number generated by the read frame number generating means. .

FIG. 4 is a timing chart showing each signal shown in FIG. 4A shows a vertical synchronization signal (VSYNC) 20 input to the MLA driving device 11. FIG.
4 is shown. 3B illustrates a data enable (DE) signal 205 indicating a valid period of the image data 100 input to the MLA driving device 11. (C) shows a synchronization signal (WR_SYNC) 300 for a write frame counter. (D) shows a synchronization signal (RD_SYNC) 304 for a read frame counter. (E) shows the write block count signal 301. (F) shows a light frame count A signal 302 and a light frame count B signal 303. (G) shows the subframe count signal 306. (H) shows the lead frame count A signal 307 and the lead frame count B signal 308.

Next, the operation of the frame signal generator 60 will be described with reference to the timing charts of FIGS. The write frame synchronization signal generator 61 receives the VSYNC 204 input to the MLA driving device 11 and the DE 205 indicating the valid period of the image data 100, and
The WR_SYNC 300 is generated at the rising timing of the first DE 205 after the YNC 204 (see (C) in FIG. 4).

The write block counter 62 is an octal counter that counts the DE 205 after the WR_SYNC 300 to indicate which of the eight areas of the display screen the current image data is. For example, VSYNC2
When there are 480 DEs 205 in the low-level period of 04, the write block counter 62 determines that 60 (=
480/8) When the number of shots is counted, the count value is increased by one. Then, the write block counter 62 outputs a write block count signal 301 which is the count value (see (E) in FIG. 4). In order to return the write control to block 5 to the initial state, it is a quinary counter that counts WR_SYNC 300. The write frame counter B64 is used to write data to blocks 6 to 14 of the frame memory 23 after 9 input frames have elapsed. In order to return the writing control to the initial state, the writing frame counter A63 and the writing frame counter B64 count a WR_SYNC 300. The writing frame counter A63 and the writing frame counter B64 respectively include a writing frame count A signal 302 and a writing frame The count B signal 303 is output (see (F) in FIG. 4).

The lead frame synchronization signal generator 65 outputs V
First DE of lower screen data after SYNC signal 204
RD_SYNC 30 at the rising timing of 205
4 (see (D) in FIG. 4). The sub-group counter 66 counts the reference clock in the MLA driving device 11 and applies a voltage to the row electrode and the column electrode from the row driver 14, the upper screen column driver 12 and the lower screen column driver 13 during one selection period. A selection time timing signal 305 indicating the time of application is generated. Then, the sub-frame counter 67 counts the selection time timing signal 305, performs a count-up operation every time one screen time (one sub-frame time) elapses, and outputs a sub-frame count signal 306 that is the count value. Is output. In this embodiment, the value of the subframe count signal 306 takes a value of 0 to 3 (see (G) in FIG. 4).

The read frame counter A68 counts the read frame using the RD_SYNC 304 and the subframe count signal 306 in order to return the read control from the blocks 1 to 5 of the frame memory 23 to the initial state after 10 output frames have elapsed. It is a decimal counter to count. The read frame counter B69 counts the read frames using the RD_SYNC 304 and the subframe count signal 306 in order to return the read control from the blocks 6 to 14 of the frame memory 23 to the initial state after the lapse of 18 output frames. Octal counter. Lead frame counter A68 and lead frame counter B6
9 is a lead frame count A signal 307 and a lead frame count B signal 3
08 (see (H) in FIG. 4).

In order to synchronize the count-up operation with the write frame counter A 63 and the write frame counter B 64, the read frame counter A
A write frame count A signal 302 is input to 68, and a write frame count B signal 303 is input to the read frame counter B69. As shown in FIG. 5, the count value of the light frame counter A63 is 0.
When the RD_SYNC 304 occurs, the read frame counter A68 forcibly resets the count value to "0". Also, when the count value of the write frame counter B64 is 0 and RD_SYNC 304 occurs, the read frame counter B69 forcibly sets the count value to "".
The count value of the write frame counter and the read frame counter may deviate halfway due to a count error caused by noise in the MLA driving device 11 or extra counting operation. As described above, if the lead frame counter A68 and the lead frame counter B69 are configured to be forcibly reset, the synchronization of each counter can be restored.

FIG. 6 is a block diagram showing the configuration of the write address generator 70. The first frame write address generator 71 uses a write frame count A signal 302, a write block count signal 301 from the frame signal generator 60, and a write end signal 209 from the memory control signal generator 90 to generate a write data buffer. 22 to generate an address for writing data for the first frame to a predetermined block in the frame memory 23, and generates an address signal for the first frame (WR_1st).
Output as 400. That is, the first frame write address generator 71 outputs the frame count A signal 3
When 02 or the value of the write block count signal 301 changes, an address corresponding to the value of the frame count A signal 302 and the value of the write block count signal 301 is generated. This address is the head address of a block (one of blocks 1 to 5) corresponding to the value of the frame count A signal 302 and the value of the write block count signal 301 in the frame memory 23. Thereafter, the first frame write address generator 71
Updates the address when the write end signal 209 is generated.

The second frame write address generator 72 uses the write frame count B signal 303, write block count signal 301 from the frame signal generator 60 and the write end signal 209 from the memory control signal generator 90. And write data buffer 2
2 to generate an address for writing data for the second frame into a predetermined block in the frame memory 23;
The second frame address signal (WR_2nd) 401 is output. That is, when the value of the frame count B signal 303 or the write block count signal 301 changes, the second frame write address generator 72 changes the address corresponding to the value of the frame count B signal 303 and the value of the write block count signal 301. Generate. This address is a block (block 6) corresponding to the value of the frame count B signal 303 and the value of the write block count signal 301 in the frame memory 23.
To any one of the blocks 14). Thereafter, when the write end signal 209 is generated, the second frame write address generator 72 updates the address. The write block count signal 301, write frame count A signal 302, and write frame count B signal 303 correspond to the write frame signal 206 shown in FIG. Also, the first frame address signal 400 and the second frame address signal 40
1 corresponds to the write address signal shown in FIG.

FIG. 7 is a timing chart for explaining the operation of the write address generator 71 for the first frame. FIG. 7A shows a write frame count A signal 302. (B) shows the write block count signal 301. (C) to (G) show the data writing states of the blocks 1 to 5, which are five blocks for writing the data of the first frame when the frame memory 23 is divided into 14 blocks. WR
_U11, WR_U12, WR_U13, WR_U14
Indicates that the data for the first frame is to be written in the areas U1, U2, U3, and U4 of the upper screen, respectively.
R_L11, WR_L12, WR_L13, WR_L1
4 indicates that the data for the first frame is to be written in the areas L1, L2, L3, and L4 on the lower screen.

Next, the address generated by the first frame write address generator 71 will be specifically described with reference to FIG. As shown in FIG. 7, the first frame write address generator 71 indicates the area of the block 1 when the value of the write frame count A signal 302 is 0 and the value of the write block count signal 301 is 0. Generate an address (WR_U1 in (C) of FIG. 7)
1). Therefore, data writing is started from block 1. Then, each time the write end signal 209 is issued, the address is updated so that data is written to each address in the block 1. Subsequently, when the value of the write block count signal 301 becomes 1, the first frame write address generator 71 generates an address indicating the area of the block 2 so that writing to the block 2 is started ( (Refer to the period of WR_U12 in (D) of FIG. 7). The address is updated every time the write end signal 209 is issued, and the block 2 is updated.
So that data is written to each address.

Therefore, one address is outputted as the first frame address signal 400 before the first write end signal 209 is issued from the first frame write address generator 71. The first frame address signal 400 is input to the memory control signal generator 90 as a write address signal 212. The memory control signal generator 90 uses the address based on the write address signal 212 as the memory address signal 215 to store the frame memory 2.
3, and at the same time, a write signal is supplied to the frame memory 23 as a memory device control signal 214. Therefore, data is written to the corresponding address in the frame memory 23.

Thereafter, the value of the write frame count A signal 302 and the write block count signal 301
, The address of the block to be written is generated. As described above, the first frame write address generator 71 sets the write frame count A
Based on the value (0 to 4) of the signal 302 and the value (0 to 7) of the write block count signal 301, a block address is generated so that writing as shown in FIG. 7 is performed.

FIGS. 8 to 10 are timing charts for explaining the operation of the write address generator 72 for the second frame. 8A to 10, (A) shows a light frame count B signal 303. (B) shows the write block count signal 301. (C)-(K)
Indicates a data write state of the blocks 6 to 14, which are nine blocks for writing data of the second frame when the frame memory 23 is divided into 14 blocks. WR_U21, WR_U22, WR_U
23, WR_U24 are U1, U2,
WR_L21, WR_L22, WR_L indicate that the data for the second frame is to be written in the areas U3 and U4.
L23 and WR_L24 are L1 and L on the lower screen, respectively.
This indicates that the data for the second frame is to be written in the areas 2, L3 and L4.

Next, the address generated by the second frame write address generator 72 will be specifically described with reference to FIGS. As shown in FIG. 8, when the value of the write frame counter B is 0 and the value of the write block counter is 0, the second frame write address generator 72 generates an address indicating the area of the block 6. (Refer to the period of WR_U21 in FIG. 8C). Therefore, writing is started from block 6. And
Each time the write end signal 209 is issued, the address is updated so that data is written to each address in the block 6. Subsequently, the write block count signal 3
When the value of 01 becomes 1, an address indicating the area of the block 7 is generated, and writing to the block 7 is started (see the period of WR_U22 in (D) of FIG. 8). Then, each time the write end signal 209 is issued, the address is updated so that data is written to each address in the block 2.

Therefore, one address is also output from the second frame write address generator 72 as the second frame address signal 401 before one write end signal 209 is issued. The second frame address signal 401 is input to the memory control signal generator 90 as a write address signal 212. The memory control signal generator 90 outputs the address based on the first frame address signal 400 from the first frame write address generator 71 to the frame memory 23, and then converts the address based on the write address signal 212 into the memory address signal 215 as the frame address. The signal is supplied to the memory 23 (see (I) memory address signal in FIG. 2). At the same time, a write signal is given to the frame memory 23 as a memory device control signal 214. Therefore, data is written to the corresponding address in the frame memory 23. When the memory control signal generator 90 outputs an address based on the second frame address signal 401 from the second frame write address generator 72 to the frame memory 23, the memory control signal generator 90 issues a write end signal 209 ((FIG. F)).

Thereafter, the value of the write frame count B signal 303 and the write block count signal 301
The address of the block to be written is generated based on the value of. As described above, the write address generator 72 for the second frame performs the operation shown in FIG. 8 based on the value (0 to 8) of the write frame count B signal 303 and the value (0 to 7) of the write block count signal 301. To generate a block address so as to perform writing as shown in FIG.

FIG. 11 is a block diagram showing a configuration of the read address generator 80. The upper screen read address generator 81 and the lower screen read address generator 82 shown in FIG. 11 correspond to the read frame count A signal 307, the read frame count B signal 308, the subframe count signal 306 from the frame signal generator 60,
Using the read end signal 211 from the memory control signal generator 90, an address for reading the upper screen data and the lower screen data from a predetermined block of the frame memory 23 is generated, and an upper screen read address signal is generated. 500 and lower screen read address signal 50
Output as 1. That is, the upper screen read address generator 81 and the lower screen read address generator 8
When the value of the lead frame count A signal 307, the lead frame count B signal 308, or the subframe count signal 306 changes, the lead frame count A signal 307 or the lead frame count B signal 3
An address corresponding to the value of 08 and the value of the subframe count signal 306 is generated. This address corresponds to the value of the lead frame count A signal 307 or the lead frame count B signal 308 and the value of the subframe count signal 306.
Is the start address of a block (one of blocks 1 to 14) corresponding to. The subframe count signal 306 and the lead frame count A signal 3
07 and the read frame count B signal 308 correspond to the read frame signal shown in FIG. The upper screen read address signal 500 and the lower screen read address signal 501 correspond to the read address signal 213 shown in FIG.

FIGS. 12 to 15 are timing charts for explaining addresses generated by the upper screen read address generator 81. FIG. In FIG. 12, (A) shows a lead frame count A signal 307. (B) shows the subframe count signal 306. (C)-(G)
Indicates a state of reading data of blocks 1 to 5 when the frame memory 23 is divided into 14 blocks. 13A to 15A show the lead frame count B signal 308. FIG. (B)
7 shows a subframe count signal 306. (C) ~
(K) shows the state of reading data from block 6 to block 14 when the frame memory 23 is divided into 14 blocks. 12 to 15, RD_U
1, RD_U2, RD_U3, and RD_U4 indicate that data in the areas U1, U2, U3, and U4 on the upper screen are read, respectively, and RD_L1, RD_L2, and RD_L
3, RD_L4 are L1, L2, L on the lower screen, respectively.
3 and L4 are read out.

Next, a method for reading the upper screen data from the blocks 1 to 5 in the upper screen read address generator 81 will be specifically described with reference to FIG. When the value of the read frame counter A is 0 and the value of the subframe counter is 0, the upper screen read address generator 81 generates an address so as to read the data in the U1 area of the upper screen from the block 1 ( FIG.
(Refer to the period of RD_U1 when the read frame count A is 0 and the subframe count is 0 in (C)), the address is updated each time the read end signal 211 is issued, and data is read from each address in the block 1. To be In addition, an address is generated so as to read data in the U2 area on the upper screen from the block 2 (FIG. 12).
(Refer to the period of RD_U2 when the read frame count A is 0 and the subframe count is 0 in (D)), the address is updated each time the read end signal 211 is issued, and data is read from each address in the block 2. To be Similarly, the upper screen read address generator 81 generates an address such that data in the U3 area of the upper screen from block 3 is read and data in the U4 area of the upper screen is read from block 4 (see FIG. 12). (See periods RD_U3 and RD_U4 when the read frame count A is 0 and the subframe count is 0 in (E) and (F).)

The memory control signal generator 90 sequentially supplies these addresses to the frame memory 23 as a memory address signal 215. Also, each memory address signal 21
5 in synchronization with the memory device control signal 2
14 to the frame memory 23. Therefore, the areas U1, U2, U3, U
4 is read out.

Subsequently, when the sub-frame count value becomes 1, an address for reading the data in the areas U2, U3, and U4 of the upper screen from the blocks 2, 3, and 4 is generated (FIG. 12D ), (E),
RD_U2, RD_U3, R when lead frame counter A is 0 and subframe counter is 1 in (F)
D_U4 period). Thereafter, the upper screen read address generator 81 performs reading based on the value (0 to 9) of the read frame count A signal 307 and the value (0 to 3) of the subframe count signal 306 as shown in FIG. Generate the address of the block to be performed.

Next, referring to FIGS. 12 to 15, blocks 6 to 14 in the upper screen read address generator 81 will be described.
The method of reading the upper screen data from the CPU will be described. When the value of the read frame counter B is 0 and the value of the sub-frame counter is 0, reading of data for the upper screen is not performed from blocks 6 to 14,
5 (see the period when the read frame counter B is 0 and the subframe counter is 0 in FIGS. 12 and 13). If the value of the lead frame counter B is 0,
When the value of the sub-frame counter becomes 1, the upper screen read address generator 81 outputs the upper screen U
An address is generated so as to read data of one area (see the period of RD_U1 when the read frame count B is 0 and the subframe count is 1 in FIG. 13C), and every time the read end signal 211 is issued. The address is updated so that data is read from each address in the block 6. When the sub-frame count value is 2, the upper screen U1, U
An address for reading data in the area No. 2 is generated (RD_U when the read frame count B is 0 and the subframe count is 2 in FIGS. 13C and 13D).
1, period RD_U2). The operation of the memory control signal generator 90 when the address from the upper screen read address generator 81 is input is as described above.

Thereafter, the upper screen read address generator 8
1 generates an address of a block to be read based on the value (0 to 17) of the read frame count B signal 308 and the value (0 to 3) of the subframe count signal 306 as shown in FIGS. . As described above, the upper screen read address generator 81 performs the operations shown in FIGS. 12 to 15 on the basis of the value of the lead frame count A signal 307, the value of the lead frame count B signal 308, and the value of the subframe count signal 306. A block address as shown in FIG.

The lower screen read address generator 8
2 also, like the upper screen read address generator 81,
The value of the lead frame count A signal 307 (0 to 9),
Value of lead frame count B signal 308 (0 to 17)
And the value of the subframe count signal 306 (0 to 3)
12 to 15, RD_L1, R
An address is generated so as to read data in the areas of L1, L2, L3, and L4 on the lower screen from the blocks indicated by D_L2, RD_L3, and RD_L4, respectively.

After supplying the upper screen read address signal 500 from the upper screen read address generator 81 to the frame memory 23, the memory control signal generator 90
Each address based on the lower screen read address signal 501 is sequentially given to the frame memory 23 as a memory address signal 215 (see (I) memory address signal in FIG. 2). In addition, in synchronization with each memory address signal 215, a read signal is provided to the frame memory 23 as a memory device control signal 214. Therefore, the corresponding data of the areas L1, L2, L3, and L4 are sequentially read from the frame memory 23. And a memory control signal generator 9
0 outputs a read end signal 211 when each address according to the lower screen read address signal 501 is output to the frame memory 23 (see (H) in FIG. 2).

As described above, the write address generator 70 generates data based on the write block count signal 301, the write frame count A signal 302 and the write frame count B signal 303 generated by the frame signal generator 60. Generate the address of the block to be written. Also, the read address generator 80
Generates an address of a block to be read based on a lead frame count A signal 307, a lead frame count B signal 308, and a subframe count signal 306 generated by the frame signal generator 60.

The frame signal generator 60 for generating each of these count signals outputs the light frame count A signal 3
02 (0 to 4) and the order (0 to 9) of the read frame count A signal 307 and the order (0 to 17) of the read frame count B signal 308 with respect to the order (0 to 8) of the write frame count B signal 303. Generate the count signals while synchronizing them so that they are in the correct order. Therefore, by the memory control circuit 24A having the above-described configuration, the writing operation and the reading operation for each block when the frame memory is divided into 14 blocks are performed regularly in the order shown in FIG.

[0080]

As described above, according to the present invention, the driving device of the liquid crystal display device is provided with the writing frame /
The block number generation means and the read frame number generation means each independently generate a data write destination and a data read destination in a block of the memory, and the arbitration means arbitrates a write operation to the memory and a read operation from the memory. Therefore, when the memory control means starts the write control, it determines whether or not the read control from the block is completed, and when the read control is started, it determines whether the write to the block is completed. And the configuration of the memory control circuit can be simplified.

If the read-out frame number generating means is configured to generate a display frame number synchronized with the input frame number, a count error may occur due to noise or the like or an extra counting operation may be performed. As a result, it is possible to prevent the count values of the input frame number and the display frame number from being shifted halfway, thereby preventing a display image from being lost or being incorrectly displayed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a memory control circuit in an MLA driving device according to the present invention.

FIG. 2 is a timing chart for explaining operations of a memory write / read arbitration circuit and a memory control signal generator shown in FIG. 1;

FIG. 3 is a block diagram showing a configuration of a frame signal generator shown in FIG.

FIG. 4 is a timing chart for explaining an operation of the frame signal generator shown in FIG. 1;

FIG. 5 is a timing chart showing a part of FIG. 4 in an enlarged manner.

FIG. 6 is a block diagram showing a configuration of a write address generator shown in FIG.

FIG. 7 is a timing chart for explaining an operation of the first frame write address generator shown in FIG. 6;

FIG. 8 is a timing chart for explaining an operation of the second frame write address generator shown in FIG. 6;

FIG. 9 is a timing chart for explaining an operation of the second frame write address generator shown in FIG. 6;

FIG. 10 is a timing chart for explaining an operation of the second frame write address generator shown in FIG. 6;

FIG. 11 is a block diagram showing a configuration of a read address generator shown in FIG.

FIG. 12 is a timing chart for explaining an address generated by an upper screen read address generator shown in FIG. 11;

FIG. 13 is a timing chart for explaining an address generated by the upper screen read address generator shown in FIG. 11;

FIG. 14 is a timing chart for explaining an address generated by an upper screen read address generator shown in FIG. 11;

FIG. 15 is a timing chart for explaining an address generated by an upper screen read address generator shown in FIG. 11;

FIG. 16 is an explanatory diagram showing how to determine a sequence of a voltage waveform applied to a column electrode of a liquid crystal display device by the MLA method.

FIG. 17 is a block diagram illustrating an example of a liquid crystal display device equipped with a driving device that realizes the MLA method.

FIG. 18 is a block diagram showing an internal configuration of the MLA driving device.

FIG. 19 is a timing chart for explaining the operation of the conventional MLA driving device.

FIG. 20 shows the display screen of the liquid crystal display device in the upper and lower directions respectively.
FIG. 4 is an explanatory diagram showing a state where the image is divided into two regions.

FIG. 21 is a timing chart for explaining the operation of another conventional MLA driving device.

[Explanation of symbols]

 24A Memory control circuit 50 Memory write / read arbitration circuit 60 Frame signal generator 70 Write address generator 80 Read address generator 90 Memory control signal generator

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takeshi Kuwata 1150 Hazawacho, Kanagawa-ku, Yokohama-shi, Kanagawa Prefecture Asahi Glass Co., Ltd.

Claims (7)

[Claims] 1. A liquid crystal display having a plurality of row electrodes and a plurality of column electrodes is collectively selected from a plurality of row electrodes, a predetermined voltage is applied to each of the selected row electrodes, and a selected voltage is applied via a write data buffer. A driving device for a liquid crystal display device that reads image data stored in a memory through a read data buffer and applies a voltage based on the read data to each column electrode, wherein an input frame number of the image data, Writing frame / block number generation means for generating a block number indicating which area the input image data corresponds to when the image data input to the liquid crystal display device is divided into a plurality of areas; A read frame number indicating a period for reading one screen once when reading the image data for one screen a plurality of times from the memory. Read frame number generation means for generating a display frame number indicating a period for displaying one screen, and performing data write control from the write data buffer to the memory in accordance with the input frame number and the block number. Memory control means for performing data read control from the memory to the read data buffer according to a frame number and a display frame number; and when a write request signal is input from the write data buffer, data output from the write data buffer to the memory is performed. An arbitration unit that outputs a write enable signal for enabling and, when a read request signal is input from the read data buffer, outputs a read enable signal for allowing data output from the memory to the read data buffer. A driving device for a liquid crystal display device, comprising: a step; 2. The writing frame / block number generating means and the reading frame number generating means generate respective numbers from a vertical synchronizing signal input to the liquid crystal display device and a data enable signal indicating a valid period of image data. Item 2. A driving device for a liquid crystal display device according to item 1. 3. The driving device for a liquid crystal display device according to claim 1, wherein the read frame number generating means generates a display frame number synchronized with the input frame number. 4. The memory is divided into a plurality of blocks, and the memory control means has a write address generation means for generating a write address for writing data from a write data buffer to the block according to an input frame number and a block number. The driving device for a liquid crystal display device according to claim 1. 5. The liquid crystal display device according to claim 4, wherein the memory control means has a read address generation means for generating a read address for reading data from the block to the read data buffer according to the read frame number and the display frame number. Drive. 6. When a write enable signal is generated, the memory control means generates a memory address signal in accordance with a write address from the write address generation means, and supplies the memory address signal to the memory device constituting the memory. A write end signal is output when a write operation to the memory device is completed, and when a read enable signal is generated, a memory address signal is generated in accordance with a read address from a read address generating means. 6. A liquid crystal display device according to claim 5, further comprising a memory device control means for outputting a memory address signal and a control signal for reading to the memory device, and outputting a read end signal when the reading operation from the memory device is completed. Drive. 7. The liquid crystal according to claim 6, wherein the write address generation means updates the write address when the write end signal is output, and the read address generation means updates the read address when the read end signal is output. A driving device for a display device.