JPH10294394A - Semiconductor package and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a fragile interface between compounds or a compound layer from being formed on a joint interface, by a method wherein Cu contained in a lead and solder contained in a solder bump are bonded together through the intermediary of a Cu-Sn-Au alloy layer. SOLUTION: An inner lead 7 composed of a Cu core lead 11 and an Au plating film 12 deposited as thick as 1.5 μm on the lead 11 and an Al pad 2 are bonded directly together by pressure through a hot ultrasonic bonding method, whereby the Al pad 2 and the Cu core lead 11 are metallically bonded together. A soldering pad 6 is arranged on the base of an opening bored in a polyimide film 4, and the surface of Cu bonded to the polyimide film 4 is plated with Au. At a soldered joint, solder is bonded directly to the surface of a Cu land. Furthermore, a package is subjected to an aging process which is carried out at temperature of 125 deg.C for 48 hours after it is assembled, and Au that is melted and diffused once into solder coheres at a joint interface again, whereby a stable alloy layer 14 of Cu-Sn-Au is formed on the joint interface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BGA type semiconductor package comprising a semiconductor chip, an organic printed circuit board or an organic tape substrate and solder ball bumps, and more particularly, to an inner bonding portion of a BGA substrate and formation of solder bumps. The present invention relates to a plating specification for a solder pad and a bonding interface structure of a solder ball bonding portion excellent in high-temperature reliability and temperature cycle life.

[0002]

2. Description of the Related Art Conventionally, a chip is bonded to an organic printed board in a face-up state, an Al pad of the chip and a bonding pad of the board are connected by wire bonding, and the chip and a wire portion are sealed with a mold resin.
There is known a BGA package in which solder balls are reflowed and mounted on pads on the other surface of a substrate. The structure of the pad on the substrate of this package is a structure of wiring Cu land / Ni plating / Au plating, and from the viewpoint of wire bonding property, Ni plating thickness: 5 to 20 μm, Au plating thickness: 0.5 to 1.5. 5 μm is employed.

[0003] The wiring leads of the organic tape substrate and the Al pad or the Au bump pad of the chip are thermocompression-bonded or ultrasonic thermocompression-bonded, the periphery of the lead is sealed with a resin, and solder balls are reflowed and mounted on the pads on the substrate. A known tape BGA package is also known. The structure of the lead of this package and the pad on the substrate is Cu lead or C lead.
After applying a Ni base plating on the u land, A
u plating is applied. Ni plating thickness: 0.5 to 1.0
μm, and an Au plating thickness of 0.5 to 2.0 μm is employed.

[0004]

SUMMARY OF THE INVENTION A semiconductor package comprises:
How to keep costs low can be a key requirement in the market, so BGA packages have excellent performance and characteristics, such as high-speed signal transmission and miniaturization of package dimensions. Is a necessary condition. At the same time, the long-term reliability of the package is also an absolute condition for realizing a product, and it is necessary to simultaneously satisfy low cost and high reliability.

In a conventional tape BGA package, the pads of the chip and the inner leads of the tape substrate are joined by gang bonding of a thermocompression bonding method via Au bumps or single point lead bonding by ultrasonic thermocompression bonding. The plating specification of the tape is such that a base Ni plating is applied on the Cu pattern and an Au plating is applied on the outermost surface. As the Au plating thickness on the outermost surface, a thickness sufficient to prevent the surface diffusion of the base material from deteriorating the inner lead bonding property due to the heat process of manufacturing the tape substrate and the heat process of assembling the package before the bonding process is adopted. Specifically, Au bump or A bump
A thickness of at least 0.5 μm, at which stable bonding strength can be obtained by bonding to the l pad, is used, and the average is 1.0 μm.

In a conventional BGA package, a pad pitch is 1.0 mm and a pad for mounting a solder ball has a diameter of 0.6 mm as a sample.
When a solder ball is bonded to a pad surface having an Au plating thickness of 0.5 μm to 5 μm, the initial solder bonding strength is about 47 ± 5 MPa in shear strength, and sufficient strength can be obtained. However, when this package is subjected to an aging treatment at a high temperature of 120 ° C. or more, at most １ ／ of the initial strength (23
The strength decreases to ± 2 MPa), and the fracture mode changes from partially ductile fracture to complete brittle fracture.
Strength reliability is significantly reduced. With the above pad dimensions, since the initial strength is 1300 gf and the strength is 650 gf even after aging, the package is not damaged in a short time by thermal stress in a thermal shock test or a temperature cycle test when the package is mounted on a motherboard, and as a package. Required reliability: 10 at -55-125 ° C temperature cycle
It can have a life of more than 00 cycles. However, when the pitch of the solder bumps becomes 0.8 to 0.5 mm due to the narrow pitch, the pad diameter becomes 0.4 to 0.2 mm, the solder ball diameter becomes 0.5 to 0.25 mm, and the bonding strength becomes initial. 590-1
50 gf, it decreases to 250 to 70 gf after aging, and at the same time, the thermal stress generated in the solder joint increases due to the decrease in solder height. Temperature cycle life: There is a problem that it is difficult to secure 500 cycles or more.

In order to prevent the solder ball joint from being deteriorated at high temperatures, the thickness of the Au plating may be set to 0.3 to 0.1 μm or less. At the same time, the thickness of the soft Au buffer becomes thinner, so that damages such as cracks tend to occur easily under the pads of the chip. The above problem can be solved by changing the Au plating thickness of the pad for the solder ball and the inner lead, but there is a problem that the manufacturing cost of the tape substrate increases.

In a conventional single-sided molded BGA package using an organic printed circuit board, a structure of a pad for joining an Au wire or a solder ball is formed of Au plating (top surface) / Ni base plating / Cu pattern (substrate side). The structure is known. Even if there is Ni plating on the Au plating base of the bonding pad, the Au plating thickness is 0.3μ.
If it is less than m, the Ni underlayer is diffused and deposited on the Au surface under the heating condition of 180 ° C. for 60 minutes, so that the wire bonding property is greatly reduced. For this reason, in mass-produced products, the Au plating thickness is set to 0.5 μm or more, and a substrate having an average thickness of about 1 μm is actually used. The solder bump pitch of the conventional BGA package is
1.27mm or 1mm, pad opening diameter is 0.6mm
Has been adopted. In this type of package, as the number of pins increases and the size of the package increases due to the increase in speed, and when a product with a pad pitch of 0.8 to 0.5 mm is required, the solder joints are formed in the same manner as described above. There is a problem that the strength at the time of high-temperature deterioration is reduced, the joint interface is broken by thermal stress generated at the time of temperature cycling, and the temperature cycle life is significantly reduced. Further, as a problem inherent in this type, when wire bonding to a pad on an organic substrate, the pad of the portion pressed by the wire is dented due to the soft organic substrate, and the tip of the capillary opposite to the wire contacts the pad. Since there is a problem that the bonding state becomes insufficient and bond peeling failure occurs due to the state, the Ni plating thickness is a thickness sufficient to prevent dents: at least 5 μm or more, and about 10 μm on average.
m is adopted. In this case, since the rigidity of Ni is high and the thermal expansion difference between the solder and the solder is large, the thermal strain of the Ni and the solder is applied to the solder joint together with the thermal strain between the mounting board and the package, so that the strength of the solder joint deteriorates. Is an even more serious problem for temperature cycle life.

In order to solve these problems, the thickness of the Au plating may be reduced to 0.3 to 0.1 μm or less in order to prevent the solder ball joint from being deteriorated at high temperatures. There is a problem that the base material diffuses and deposits on the Au surface due to the heating of the hardening treatment of the agent to form an oxide film, thereby significantly reducing wire bonding properties and causing bonding failure. As another solution, if the substrate is manufactured by changing the Au plating thickness of the pad for the solder ball and the pad for the wire bonding, the above problem is eliminated, but the manufacturing cost of the substrate increases and the package cost increases. Problems arise.

The present invention has been made in consideration of the above problems, and specific objects of the present invention are as follows.

It is an object of the present invention to provide a tape BGA package in which even if a package is assembled using a tape substrate having a lead and a solder pad plated with Au having a sufficient thickness so as not to impair the inner lead bonding property, An object of the present invention is to provide a plating specification of a tape BGA substrate and a structure of a solder joint, which can prevent a decrease in strength due to a high temperature of the bump joint.

Another object of the present invention is to provide a BGA package that, even when the solder ball bump size of the external connection terminal is reduced, prevents the solder joint from deteriorating at high temperatures and increases the temperature cycle life. An object of the present invention is to provide a low-cost and highly reliable tape BGA type semiconductor package.

Still another object of the present invention is to reduce the difference in thermal expansion between a pad and a solder in a BGA package assembled by a wire bonding method using an organic printed circuit board, to reduce the wire bonding property and to reduce the solder joint. It is an object of the present invention to provide a low cost and highly reliable BGA type semiconductor package having a wire bonding structure in which a wire bonding pad and a solder pad which can prevent high-temperature deterioration of the semiconductor package have the same plating specifications.

[0014]

According to the present invention, in order to achieve the above object, Ni plating as a base for Au plating is made sufficiently thin or eliminated, and the thickness of Au plating is set to 0.3 μm to 5 μm. With the same plating specifications for the bonding pads or inner leads and the pads for solder bumps connected to the electrodes on the chip, the board can be manufactured in a single plating process, and solder balls are mounted at the final stage of semiconductor package assembly Later, aging treatment is performed, and Sn-
An ternary alloy layer of Cu-Au is formed.

A study on the high-temperature deterioration of the soldered joint by the present inventors, which is the basis of the above means, will be described.

FIG. 10 shows the relationship between the shear strength of the joint after leaving at 125 ° C. and high temperature and the thickness of the Au plating when the underlying Ni plating is formed to 0.5 μm in the tape BGA package.
As can be seen from the figure, when the thickness of the Au plating is 0.5 mm or more, a significant decrease in strength is caused by leaving it at high temperature, and at the time of the maximum decrease, it is reduced to half of the initial strength. In order to prevent the strength from decreasing, it is necessary to make the Au thickness 0.3 to 0.2 μm or less.

FIG. 11 shows the results of X-ray diffraction measurement of the fracture surface of the solder joint at the Ni base. This is a sample having an Au film thickness of 1.5 μm. From the fracture surface on the solder ball side, AuSn ₄
And the compound of Ni ₃ Sn ₄ is detected from the fracture surface on the substrate pad side. According to the elemental analysis of the same fracture surface, Au and Sn are strongly detected from the solder ball side, and Ni, Sn and Cu are detected from the substrate pad side. As for Cu on the substrate pad side, Cu in the Cu pattern under Ni is detected. From these facts, it is presumed that the cause of the high-temperature deterioration is that a two-layered compound of Au-Sn and Ni-Sn is formed at the bonding interface, and the interface strength between the two is weak, so that the interface is separated and the strength is reduced. You. In other words, it is considered that if Ni is eliminated or a heat treatment corresponding to the thickness of Ni is applied to prevent the interface from being formed, a decrease in the strength of the solder ball joint due to leaving at high temperature can be prevented.

FIG. 12 is a graph based on the above considerations.
This shows the strength of a solder joint after leaving at high temperature when Au plating is applied directly on a Cu pattern without i. The high temperature standing temperature is 125 ° C. From the figure, it can be seen that when there is no underlying Ni plating, even if the Au thickness is as thick as 2.5 μm, the strength does not decrease due to high temperature storage.

FIG. 13 shows the relationship between the high-temperature storage temperature and the shear strength for the Au plating with a thickness of 1.5 μm and with and without the underlying Ni plating. The standing time is constant for 500 hours. It can be seen that even when the temperature is changed, there is almost no decrease in strength with Ni-less.

According to the study of the present inventor, at the joint interface, in the case of the above-mentioned Ni-less, Cu-Sn-Au
And a ternary alloy layer of Cu-Sn on the Cu side. At low condition or time is short condition temperature, first the ternary layers of Cu-Sn-Au is formed, the present Au traces in the compound layer of Cu-Sn (Cu ₃ Sn) X-ray microanalyzer, X-ray diffraction, secondary ion mass spectrometry (SIMS)
Was confirmed from the results. That is, conventionally, Cu ₃ Sn
Is known to be hard and brittle, but it has been newly discovered that adding Au thereto can improve the strength of the compound. In this case, the necessary Au amount is C
If the amount enough to form earlier than Cu-Sn-Au forms a u ₃ Sn, it is was found that the strength improvement effect.

On the other hand, even when there is Ni plating, there is a case where the strength does not decrease due to high temperature storage as seen under the condition of 175 ° C. in FIG. This is because, as a result of analyzing the structure of the joint, Cu // Cu-Sn /
It was found that each layer of Sn-Au-Cu / Sn-Au-Ni // solder was formed and the interface of Au-Sn / Ni-Sn was not formed. In other words, it can be seen that even if there is a Ni underlayer, if the heat treatment conditions for forming Sn-Au-Cu are selected, a combination of compound layers having a low interfacial strength is not necessarily formed, and it is possible to prevent a decrease in strength due to high temperature storage. It was.

According to the above experiments and considerations, in the case of a tape BGA or a BGA with a wine bonding structure, when thick Au plating is required from the viewpoint of inner boding properties, the underlying Ni plating is omitted as the plating specification of the substrate, and the Cu plating is omitted. Change the specification to form an Sn-Au-Cu layer by heat treatment after assembling the package by directly applying Au plating on the pattern, or by performing sufficient heat treatment after mounting the solder balls when applying a base Ni plating.
It has been found that selecting conditions for forming the u-Cu layer is effective for improving the reliability of the package.

FIG. 14 shows prototypes of various types of substrate plating specifications for organic substrate type BGA (wire bonding bonding system) and tape BGA (inner lead bonding system), and the yield in each package assembly process. Pass or Fail was judged by × or × by the bonding strength.
If the evaluation result was just before the passing line, and it was difficult to judge the pass / fail, it was indicated by a triangle. From the results shown in the figure, with Ni plating as the base, the plating specifications that clear all of the bonding properties and the shear strength of the solder joints at the initial stage and after standing at high temperature are as follows: organic wiring board type BGA with Au thickness: 0.3 μm, With no heat history, Ni thickness on tape BGA: 0.5μ
m, Au thickness 1.5 μm or more, heat treatment condition: 175 ° C.
This is the case for 48 hours or more. However, in the former case, in the actual package assembly process, after bonding the chip to the substrate, the step of heating and curing the adhesive is indispensable,
Heat history cannot be eliminated. In the latter,
175 ° C-48 which is considerably higher than the aging treatment temperature
The heat treatment of h may cause thermal damage to the product, and is difficult to apply to the product. Therefore, in the actual process, in the organic wiring board type BGA, the base N
There is no plating specification for a substrate that satisfies all of the bonding properties and the strength of the solder joint at the initial stage and after standing at high temperature with i-plating. In the case of the tape BGA, only in the case of extremely thin Ni plating, when the Au is 1.5 μm or more, by combining with the appropriate heat treatment conditions, the bonding property and the strength of the solder joint at the initial stage and after standing at high temperature are all improved. There are satisfactory substrate plating specifications. On the other hand, in the case of Ni-less, all the items are passed when the organic wiring board type BGA is Au: 0.8 μm or more and the tape BGA type is Au: 0.5 μm or more. Assuming that the curing temperature of the chip adhesive is lowered, the bonding property in the figure may change from △ to ○, Au: 0.5 μm or more in organic wiring board type BGA, tape B
For the GA type, Au: 0.3 μm or more is preferable.

FIG. 15 shows a sample in which the solder pad size and solder ball diameter of the substrate and the plating specifications of the pad were variously changed, and the strength immediately after solder reflow and the temperature of 125 ° C.-50
The result of evaluating the strength after leaving for 0 h at a high temperature is shown. The Au concentration when the Au plating film is completely dissolved in the solder is also calculated and shown in the figure. If the Au concentration exceeds 4% by weight, a needle-like AuSn compound precipitates in the solder and the strength of the solder itself is reduced, and the reliability of the package is reduced. With the base Ni, if the Au concentration is 0.16 wt% or less, there is no problem in both initial strength and strength after standing at high temperature. In the case of the undercoat Ni-less, sufficient strength was obtained both in the initial stage and after the high-temperature storage in the Au concentration range of 0.08 to 3.78 wt%, which indicates that there is no problem. From these results, it was found that Au dissolved in the solder
Preferably, the concentration is 3.78 wt% or less.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of a sectional structure of a chip-size tape BGA package according to the present invention. The figure also shows an enlarged cross-sectional structure of the solder ball bonding portion and the inner lead bonding portion. In the figure, a tape substrate is attached to a circuit forming surface of an LSI chip 1 via an organic elastic body 3. The tape substrate is 30-100μm thick
And a patterned Cu wiring 5, an Au-plated solder pad 6, and an Au-plated inner lead 7. The Al pad 2 on the chip is arranged at the center of the chip, and the inner lead of the tape substrate is formed corresponding to the Al pad 2. The inner lead 7 has a thickness of 1.
A 5 μm Au plating film 12 is provided. The inner lead and the Al pad are directly press-bonded by a thermosonic bonding method, and the Al pad and the Cu lead are metallically joined via an Au plating layer. The solder pad is located on the bottom surface of the open polyimide film 4 and has a structure in which the Cu surface on the side to be bonded to the polyimide film is plated with Au. Although the bonding surface of the inner lead and the pad surface for soldering are in the relationship of the front and back of the Cu core lead 11, the plating is performed in the same process, and therefore the Au plating thickness is almost the same. However, when solder balls are reflowed and mounted at the solder joints, Au
Since the entire plating film is dissolved in the molten solder, the bonding structure immediately after the solder balls are mounted is a structure in which the solder is directly bonded to the Cu land surface. The enlarged cross-sectional structural view of the solder joint of the present invention is shown in FIG.
The state after performing the aging process for 48 h is depicted.
By this aging treatment, Au once dissolved and diffused in the solder is again aggregated at the bonding interface, and the Au—Cu—
An alloy layer 14 of stable Sn is formed. At this time, depending on the heat treatment conditions, a thin Cu-Sn compound layer 13 containing Au slightly between the alloy layer and the Cu land.
May be formed.

According to this embodiment, since the structure of the solder pad is Cu land / Au plating (1.5 μm thickness), the heat history (adhesion / curing of the chip, inner lead bonding, sealing) in the package assembling process. Stop
Even if a small amount of Cu precipitates on the Au surface due to baking, the Au plating film completely dissolves in the solder at the time of solder ball reflow, so that good solder wettability can be ensured over the entire Au plating area, and sufficient It is possible to obtain the initial solder joint strength. At the same time, C
In order to solve the problem that the brittle layer of the intermetallic compound grows at the u / solder joint interface and the strength is reduced, an Au—Cu—Sn alloy layer is formed at the Cu / solder interface at the final stage of package production. At the same time as the growth of the Cu ₃ Sn compound is slowed down, the hardness and brittleness of the Cu ₃ Sn compound are improved because Au is supplied from the Au—Cu—Sn layer to that layer, so that solder bonding This makes it possible to reduce high-temperature deterioration of the part.

Further, in this embodiment, the structure of the solder joint portion is such that the periphery of the joint interface between Cu and solder is fixed by the polyimide film 4 so that stress is not concentrated on the interface. The distance between the stress concentration point determined by the shape of the polyimide film and the solder ball and the bonding interface is the same as the thickness of the polyimide film, 30 to 100 μm, and 150 ° C. to 1000 h which guarantees the high temperature reliability of the semiconductor package.
Since the thickness of the compound that grows at 20 mm is 20 μm or less, the crack starting point is always the solder portion. The effect of this structure also has the effect that cracks do not occur at the bonding interface from the beginning in the temperature cycle test. In this embodiment, the reliability of the solder joint is greatly improved by improving the characteristics of the compound to be formed and by employing a structure in which stress concentration does not occur at the joint where the compound grows in shape.

In the inner lead bonding, since Au has a thickness of 1.5 μm, the deposition of Cu on the Au surface during the chip bonding / curing step is minimized, and the bonding property is impaired. On the contrary, the lead is softened due to the elimination of the hard Ni plating of the base, and the damage under the Al pad can be reduced, and at the same time, the lead is easily deformed with low stress, so that a new surface is easily formed. Thus, the effect that the joining strength is improved can be obtained.

Further, since the tape substrate is a single-sided wiring, and the plating process is performed only by one Au plating step, the manufacturing cost is reduced, and the cost of package members can be reduced.
At the same time, the assembly yield, particularly the yield of the inner lead bonding described above, can be improved, so that the package cost can be significantly reduced by both effects.

Regarding the temperature cycle life of the inner lead portion of the package after assembly, when there is hard Ni plating, cracks occur in the Ni plating portion of the bent portion of the lead, which is the starting point of crack propagation due to fatigue. However, in the example, the initial plating was not generated in the bent portion of the lead due to the elimination of Ni plating, and the temperature cycle life of the inner lead portion can be greatly extended.

By the various effects described above, it is possible to provide a chip size BGA type semiconductor package which is low in cost and excellent in reliability.

FIG. 2 shows another embodiment of the sectional structure of the chip size package according to the present invention. In this structure, the electrode pads 21 of the LSI chip 20 are arranged around. In the figure, a tape substrate composed of an organic film 22, Cu wiring 26, Au-plated pad 23, Au-plated inner lead 24 and plating resist 25 is connected to LSI chip 2 via organic elastic body 27.
0 is adhered to the circuit forming surface. A of lead and pad
The thickness of the u plating is set to 2 μm, which is sufficient to prevent pad damage by inner lead bonding. Inner leads protruding from two or four sides of the tape substrate are bonded to Al electrode pads one point at a time by ultrasonic thermocompression bonding. The bonding portion, the lead, and the electrode pad are covered and protected by a sealing resin 29. The solder ball bump 28 is formed by mounting a solder ball coated with flux on an Au-plated pad, heating the solder ball to about 240 ° C., reflowing the solder ball, and joining the pad to the pad. After forming the solder ball bumps, finally, aging treatment at 125 ° C.-48 h is performed to stabilize the device characteristics of the package, and at the same time, to form an Au—Cu—Sn alloy layer at the solder joint, and to achieve high reliability of the joint. It is trying to make it.

FIG. 3 shows a sectional view of a tape substrate which is an assembly part of the package of FIG. 2 and a plan view seen from the pad side. In the drawing, a tape-shaped organic film 30 has an opening 31 for reel winding and an opening 32 for forming an inner lead, and a cutting opening 3 for facilitating cutting after assembly.
33 are provided. Cu land 3 in which a Cu foil is attached to a tape and patterned by etching
4, a plating resist 39 is formed on the Cu wiring 35 and the Cu core lead 36 where Au plating is unnecessary.
The Au platings 33 and 37 are formed by the Cu core lead surface and Cu plating.
It is applied to two places of the pad formation surface on the land, and is formed to a thickness of about 2 μm by electroplating. Two places of Au
Plating is performed under the same conditions in one process. The tape frame to be cut and removed and the organic film 22 are connected by a thin hanging portion, and a plurality of connected tape substrates are handled while being wound on a reel.

According to the present embodiment, the N
By eliminating the i-plating, the same effect as in FIG. 1 can be obtained. In addition, since the solder ball bumps are arranged at the center of the chip as compared with FIG. 1, there is an advantage that thermal stress applied to the solder bumps when mounted on the mounting board is reduced, and the mounting reliability is excellent. In addition, since a large number of tape substrates can be handled in a connected tape state, there is an advantage that mass productivity in package assembly is excellent and that the cost of the package can be reduced.

FIG. 4 shows an embodiment of a sectional structure of a fan-out tape BGA package according to the present invention. The figure also shows a plan view from the solder ball side. In the figure, an Al pad 41 for bonding is formed on a peripheral portion of an LSI chip 40. The tape substrate is made of polyimide film 42 and patterned Cu
It is composed of a wiring, a solder pad 43 formed by Au plating on a Cu land, an inner lead 44 plated with Au on a Cu core lead, and a plating resist 45. A
The thickness of the u plating is 1.0 μm. The tape substrate is bonded to a reinforcing plate 47 via a low elastic organic elastic body 46. Inner lead bonding is performed by aligning the Au-plated Cu lead with the Au bump 50 formed on the Al pad, pressing the lead against the Au bump with a single-point TAB bonding tool that applies ultrasonic vibration and a load, and heats. While doing ultrasonic bonding. The ultrasonic frequency used at this time is 120
Ultrasonic output conditions in which the vibration amplitude was 0.8 μm at kHz were adopted, and the load was 50 g, the ultrasonic transmission time was 20 ms, and the heating temperature was 200 ° C. After bonding the inner lead of the tape substrate to which the reinforcing plate is bonded and the Al pad,
The resin is poured from the chip surface and hardened so that the sealing resin 49 protects the circuit surface, pads and lead portions of the chip. At this time, a resin whose viscosity and thixotropy are adjusted so that the resin does not leak from the gap between the chip and the reinforcing plate is used.
The curing condition of the resin was 150 ° C. for 4 hours. afterwards,
A solder ball 48 of Sn-Pb eutectic composition coated with flux is mounted on the Au-plated solder pad 23, and
Heat to 0 ° C. to melt the solder balls and join them to the pads. Finally, the package is completed by performing aging treatment at 125 ° C.-48 h together with product inspection.

According to this embodiment, in the fan-out tape BGA package corresponding to the increase in the number of pins, the base N
The tape substrate cost can be reduced by adopting a tape substrate directly plated with Au on Cu without omitting i-plating, and the inner lead bonding is eliminated by eliminating the hard underlying Ni plating and facilitating lead deformation. Strength can be improved, and the elimination of the underlying Ni plating at the solder ball joint can prevent the formation of the AuSn compound and thus prevent high temperature deterioration. In addition, the growth of the brittle intermetallic compound Cu ₃ Sn growing at the Cu / solder joint interface is slowed down by the Au—Cu—Sn alloy layer grown by the aging treatment, and is formed in advance even when the Cu ₃ Sn grows slightly. Since a small amount of Au diffuses into Cu ₃ Sn from the ternary alloy layer and improves the mechanical properties of the compound, high-temperature reliability is high, and as a result, the solder bump bonding portion Even if the diameter is as small as 0.25 mm,
It is possible to maintain a bonding strength of 200 g or more per bump, and to assure a temperature cycle life of -55 to 125 ° C./1000 cycles or more when mounted on a motherboard. For the above reasons,
It is possible to easily provide a semiconductor package which is low in cost and has a high temperature or excellent temperature cycle life.

FIG. 5 shows a tape BGA of the present invention for a microcomputer or a gate array LSI chip which generates a large amount of heat.
1 shows an embodiment of a cross-sectional structure of a package. In the figure,
The LSI chip 51 is bonded to a heat sink (also a reinforcing plate) 54 with an adhesive 53 having excellent thermal conductivity. The heat sink is made of a material having high thermal conductivity, a Cu or Al-based metal material, a composite material of them and W, or a ceramic material of AlN or SiC. The tape substrate is
Organic film 55, Cu wirings 56, 57 on both surfaces, Cu plating through hole 58 connecting between the wirings on both surfaces, Au-plated solder pad 59, Au-plated inner lead 60, plating resists 61, 62 And is adhered to a heat sink via an elastomer 63 which is an organic elastic body. The Au plating thickness of the lead and the pad is 2.0 μm. In the inner lead bonding, single point bonding is performed by ultrasonic thermocompression bonding on an Au bump 64 formed on the Al pad 52 by plating or ball bonding. The solder ball bump 65 may be formed by reflowing the solder ball or by repeatedly performing a method of printing and reflowing the solder paste. A concentrated layer is formed.

According to this embodiment, since the LSI chip is directly bonded to the heat sink with an adhesive having good heat conductivity, the heat dissipation characteristics are excellent. It can be operated. The reliability of the joint of the solder ball bumps can be greatly improved as in the case of FIG. 4 by preventing the formation of the AuSn compound having a low interface strength and diffusing Au into the Cu-Sn compound. Also, in the inner lead bonding portion, there is no problem in pad damage due to the effect of the Au bump, and the chip / tape substrate can be adhered / removed.
There is a concern that organic contamination of the lead surface during the curing process may cause a decrease in bonding properties. However, since the Au plating is thick, scrubbing should be performed immediately before bonding to mechanically scrape the surface layer. This makes it possible to improve the bonding property by adding a scrub.

From the above, it is possible to assemble an LSI chip that generates a large amount of heat and has a large number of electrode terminals into a small package with high connection reliability at both the inner lead joint and the solder bump joint. .

FIG. 6 shows an embodiment of the present invention having a tape BGA package structure of a type in which chip substrates are connected by wire bonding. In the figure, the tape substrate is composed of polyimide films 74 and 75, Cu wiring 76, a solder pad plated with Au on Cu land 77, an inner bonding pad 78 plated with Au, and a plating resist 79. Au plating of each pad of the substrate is applied directly on the Cu pattern and the thickness is minimum 1.0μ.
m. The LSI chip 70 is fixed to a tab 74 made of a polyimide film with an adhesive. The polyimide film in the area corresponding to the electrode pad 71 of the LSI chip has been removed, and the tab 74 is made smaller than the chip by the electrode pad area. Au wire 7 between the electrode pad of the LSI chip and the inner bonding pad of the tape substrate
2 are electrically connected by ball bonding. On the chip mounting surface side of the tape substrate, a resin is molded and solidified for the purpose of protecting the wire bond portion and the chip and for the purpose of maintaining the flatness of the tape substrate. Solder balls 80 are joined and mounted on the solder pads of the tape substrate by reflow.
An Au-Cu-Sn alloy is formed at the bonding interface by the aging process. FIG. 7 shows a wire bonding method when assembling the package of FIG. Also, LS
The I chip 70 is attached to a tab 74 of a polyimide film of a tape substrate with an adhesive, and is temporarily cured at 100 ° C. for 60 minutes. The tape substrate on which the chip is mounted is placed on a heat stage 83 in which the thickness under the electrode pad of the chip is increased by the thickness of the film, and the back surface of the chip and the back surface around the inner bonding pad of the substrate are passed through a suction port 85 provided in the heat stage. In the evacuation direction 86, it is vacuum-adsorbed and fixed on the heat stage. Since the chip and the polyimide film are fixed independently, the chip does not move during wire bonding even if the adhesion between the chip and the tab of the tape is weak. Further, the chip and the tab do not peel off. The entire stage is heated by the heater 84 built in the heat stage, the electrode pads 71 on the chip are heated by heat conduction through the chip, and the bonding pads on the substrate are heated by heat conduction through the polyimide film. Since the chip has good heat conduction and the polyimide film is thin,
It can be heated to a temperature of 230 ° C. in a short time within minutes. Therefore, wire bonding can be completed within two minutes after the temperature of the tape substrate exceeds 150 ° C.

FIG. 8 is a plan view of a tape substrate on which the LSI chip of FIG. 7 is mounted. To make it easier to see, the plating resist is removed and the polyimide film under the chip is drawn through. In the figure, the polyimide film of the tape substrate is divided into a region 75 for mounting solder bumps and a tab 74 for bonding the LSI chip 70, and both are connected by a square tab suspension 87. There is no polyimide film under the electrode pad 71 of the chip. The Cu land 77 for the solder bump and the inner bonding pad 78 are connected by a Cu wiring 76. Cu
The polyimide film on the back surface of the land is removed to form an Au-plated solder pad, and the surface of the inner bonding pad is also plated with Au of the same specification.

According to the present embodiment, in the tape BGA package of the wire bonding mounting type, the plating process of the tape substrate can be performed by one Au plating process, so that the equipment cost can be reduced and the production tact can be shortened to reduce the substrate cost. Can be achieved. In addition, in the wire bonding, the chip is directly fixed on the heat stage without the intervention of the polyimide film, so that stable ball bonding can be performed without curing the adhesive of the chip. It becomes possible to lower the heat treatment temperature of the previous tape substrate to 100 ° C or less,
As a result, there is an effect that deposition of a base plating material on the Au surface before the bonding step is prevented, and bonding defects in assembling the package can be significantly reduced.
In addition, the elimination of Ni plating prevents the formation of a brittle AuSn / NiSn compound interface when left at high temperatures, thereby preventing high-temperature deterioration. Furthermore, the thermal expansion difference at the solder / pad joint interface is Ni
/ 10 × 10 ^-6 / ° C of solder to 7 × 10 ^{-6 of} Cu / solder
/ ° C, the crack generation period at the outer periphery of the solder joint at the time of the temperature cycle test is prolonged, and the fatigue life is extended.

As described above, in the tape BGA package having the wire bonding mounting structure, mounting and assembling with a high yield on a substrate without the base Ni plating can be achieved by several effects as described above. It is possible to provide a semiconductor package with high reliability.

FIG. 9 shows a sectional structure of a BGA semiconductor package having a wire bonding structure using an organic printed circuit board according to an embodiment of the present invention. In the figure, a BGA organic substrate has an organic insulating plate 92, a Cu wiring 93, and a thickness of 1.0.
μm Au-plated bonding pad 94
And a Cu-plated through hole 96, a Cu land 95 plated with Au for mounting a solder ball and having the same specifications as the bonding pad, and plating resists 98 and 99. The LSI chip 90 is bonded to the BGA substrate with an adhesive 101, and the Al pad 91 of the chip and the bonding pad 94 of the substrate are connected by ball bonding of Au wire 100. The adhesive is a low-temperature curable resin, and the curing condition is 150 ° C. for 60 minutes. The solder ball joint is subjected to an aging treatment after mounting the solder ball, and the Au-Cu-
An Sn alloy layer 97 is formed. On the Cu side, a CuSn-based alloy or compound layer containing a small amount of Au may be formed. The bonding portion has a structure in which the height of the plating resist is formed thicker than the thickness of the compound grown under the heat treatment condition of 150 ° C. to 1000 h, and the periphery of the grown compound or alloy layer is reinforced with the resist. On the side where the chip is mounted, resin 103 is molded to protect the chip and the joint.

According to the present embodiment, since the Au plating is formed to a thickness of 1 μm or more, a large amount of Cu is not deposited on the Au surface by the above-mentioned baking treatment to reduce the bonding property. Formed a brittle compound of Cu ₃ Sn by forming an alloy layer containing Au at the interface of Cu / solder without forming a brittle interface of AuSn and NiSn at the joint interface by removing the conventional Ni plating Therefore, there is an advantage that the problem of strength reduction due to high temperature storage is eliminated. Also, as in the case of FIG.
By omitting Ni, whose thermal expansion coefficient is considerably smaller than that of solder, it is possible to suppress the occurrence of thermal fatigue cracks generated in the solder due to the difference in thermal expansion between the pad and the solder. There is also an advantage that the temperature cycle life can be greatly improved to a longer time side.

FIG. 16 shows an embodiment of a partial sectional structure of a solder ball joint of a chip-size tape BGA package according to the present invention. In the figure, an LSI chip 111
A tape substrate is adhered to the circuit forming surface of FIG. The tape substrate has a thickness of 30 to 10
It is composed of a 0 μm polyimide film 112 and a Cu conductor which is patterned and Au-plated to a thickness of about 1 μm on the surface. In the figure, a Cu land 113 which is a part of the Cu conductor is shown. Au plated C
The opening of the polyimide film on the u-land becomes a solder ball mounting pad. However, at the solder joints, when the solder balls are reflowed and mounted, the entire Au plating film is dissolved in the molten solder. It becomes a joined structure. The cross-sectional structure diagram of the solder joint shown in the figure depicts a state after the aging process at 120 ° C. for 48 hours after the package assembly is completed. By this aging treatment, Au once dissolved and diffused in the solder is again aggregated at the bonding interface, and a stable Au-Cu-Sn alloy layer 117 is formed at the interface.

According to this embodiment, the structure of the solder pad is Cu land / Au plating (1.0 μm thickness), so that the heat history (adhesion / curing of the chip, inner lead bonding, sealing) in the package assembling process. Stop
Even if a small amount of Cu precipitates on the Au surface due to baking, the Au plating film completely dissolves in the solder at the time of solder ball reflow, so that good solder wettability can be secured over the entire Au plating area, and sufficient initial soldering can be achieved. It is possible to obtain a joint strength. At the same time, the problem that the brittle layer of the intermetallic compound grows on the Cu / solder joint interface due to the high temperature storage and the strength is reduced is solved by using the Au-Cu-Sn alloy layer on the Cu / solder interface at the final stage of package production. At the same time slows the growth of the Cu ₃ Sn compound, and at the same time improves the hardness and brittleness of the Cu ₃ Sn compound because Au is supplied from the Au—Cu—Sn layer to that layer. Therefore, it is possible to reduce high-temperature deterioration of the solder joint.

Further, since the tape substrate is a single-sided wiring, and the plating process is performed only by one Au plating step, the manufacturing cost is reduced, and the cost of package members can be reduced.

FIG. 17 shows an embodiment of a sectional structure of a chip-size tape BGA package according to the present invention. The figure also shows an enlarged cross-sectional structure of the solder ball bonding portion and the inner lead bonding portion. In the figure, a tape substrate is attached to a circuit forming surface of an LSI chip 121 via an organic elastic body 123. The thickness of the tape substrate is 2
5-100 μm polyimide film 124 and patterned Cu conductor 125, Cu land 126 serving as Ni / Au plated solder pad, Ni / Au plated inner lead 127, plating resist 128
Consists of The Al pad on the chip is arranged at the center of the chip, and the inner lead of the tape substrate is formed corresponding to the position of the Al pad. Inner lead 1
Reference numeral 27 denotes a Cu core lead 131 on which a Ni plating 132 having a thickness of 0.2 μm and an Au plating 133 having a thickness of 1.5 μm are applied. The inner lead and the Al pad are directly press-bonded by a thermosonic bonding method, and the Al pad and the Cu core lead are metallically joined via an Au plating layer. The solder pad is located on the bottom surface of the open polyimide film.
The structure is subjected to i / Au plating. Although the bonding surface of the inner lead and the solder pad surface are in a positional relationship of the front and back of the Cu foil, the plating is performed in the same process, so that both have approximately the same Au plating thickness. However, at the solder joint portion, when the solder ball is reflowed and mounted, the entire Au plating film is dissolved in the molten solder, so the bonding structure immediately after mounting the solder ball is on the Cu land / Ni plating surface. A structure in which the solder is directly joined is obtained.
The enlarged cross-sectional structural view of the solder joint according to the present invention illustrates a state after performing aging treatment at 150 ° C. for 48 hours after package assembly is completed. By this aging treatment, the Au once dissolved and diffused in the solder is again aggregated at the bonding interface, and at the same time, the diffusion and disappearance of the Ni film are promoted and the C
Three alloy layers 134, 135, and 136 of u-Sn / Cu-Sn-Au / Sn-Ni-Au are formed.

According to this embodiment, the structure of the solder pad is changed to Cu land / Ni plating (0.2 μm) / Au plating (1.
(5 μm thickness), it is possible to prevent the deposition of Ni and Cu on the Au surface due to the thermal history (adhesion and curing of the chip, inner lead bonding, sealing and baking) in the package assembling process. Therefore, good solder wettability can be secured, and sufficient initial solder joint strength can be obtained. At the same time, the problem that the brittle layer of the intermetallic compound grows at the Cu / Ni / solder joint interface due to the high temperature storage and the strength is reduced is solved by adding Cu to the Cu / solder interface at the final stage of package production.
-Sn / Cu-Sn-Au / Sn-Ni-Au formation of brittle AuSn ₄ compounds by forming an alloy layer prevents at the same time in a layer of another brittle Cu ₃ Sn in Au-
The supply of a small amount of Au from the Cu-Sn layer is promoted, and Cu ₃ Sn
It is possible to improve the hardness and brittleness of the compound and reduce the high-temperature deterioration of the solder joint.

In the inner lead bonding, the deposition of Cu on the 1.5 μm thick Au plating surface in the step of bonding and curing the chip can be prevented by applying a thin Ni plating on the base, Therefore, the bonding property is not impaired. In addition, the lead is softened by thinning the underlying hard Ni plating, and the damage under the Al pad can be reduced.
The lead is easily deformed with low stress, so that a new surface is easily formed, and the bonding strength can be improved.

Further, the tape substrate is one-sided and the plating process is performed only by one Au plating process, so that the manufacturing cost is reduced and the cost of package members can be reduced.
At the same time, the assembly yield, particularly the yield of the inner lead bonding described above, can be improved, so that the package cost can be significantly reduced by both effects.

By the various effects as described above, it is possible to provide a chip size BGA type semiconductor package which is low in cost and excellent in reliability.

[0055]

As described above in detail, according to the present invention, in the tape BGA package, the inner lead bonding property of the substrate is not impaired, that is, the chip strength under the pad is prevented and the bonding strength of 50% or more of the lead strength is prevented. When a sufficient thickness of Au plating was applied to the leads and the solder pads of the tape substrate, the Ni layer at the solder ball joint was eliminated and an Au-Cu-Sn alloy layer was formed at the interface. As a result, it is possible to prevent the formation of an interface between compounds fragile at the bonding interface or the formation of a layer of the compound. It is possible to provide a low-cost semiconductor package that does not cause high-temperature deterioration of the semiconductor package.

Further, in a BGA package assembled by a wire bonding method using an organic printed circuit board, a wire capable of reducing a difference in thermal expansion between a pad and solder, and preventing a decrease in wire bonding property and a high temperature deterioration of a solder joint. An object of the present invention is to provide a low cost and highly reliable BGA type semiconductor package having a wire bonding structure in which a bonding pad and a solder pad provide the same plating specifications.

Further, in a BGA package using a tape substrate or an organic printed circuit board, even when the solder ball bump size of the external connection terminal is reduced, the high temperature deterioration of the solder joint is prevented and the temperature cycle life is extended. At the same time, a low-cost and highly reliable BGA semiconductor package can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional structure of a chip-size tape BGA package according to the present invention.

FIG. 2 is another cross-sectional structure of a chip-size tape BGA package according to the present invention.

FIG. 3 is a cross-sectional view and a plan view of a tape substrate which is a package component of FIG. 2;

FIG. 4 is a cross-sectional structure of a fan-out tape BGA package according to the present invention.

FIG. 5 is a cross-sectional structure of a tape BGA package for an LSI chip generating a large amount of heat according to the present invention.

FIG. 6 is a cross-sectional structure of a tape BGA package of a wire bonding type according to the present invention.

FIG. 7 is a wire bonding method for assembling the package of FIG. 6;

FIG. 8 is a plan view of the tape substrate of FIG. 7;

FIG. 9 is a sectional view of a BGA package of a wire bonding type using an organic printed circuit board according to the present invention.

FIG. 10 is an experimental result showing the relationship between the shear strength of a solder joint after standing at a high temperature and the thickness of Au plating when there is a base Ni plating.

FIG. 11 shows an X-ray diffraction measurement result of a fracture surface of a solder joint.

FIG. 12 shows experimental data on the relationship between the shear strength of the solder joint after high-temperature storage and the Au plating thickness in the case of Ni-less.

FIG. 13 is an experimental result showing a relationship between a high-temperature leaving temperature and a solder joint strength after leaving at a high temperature in the presence and absence of a base Ni.

FIG. 14 shows the results of determination of the plating specifications of the BGA substrate and the quality of wire bonding or inner lead bonding and the strength reliability of the solder joint.

FIG. 15 shows the results of determining whether or not the plating specifications of the BGA substrate and the strength reliability of the solder joint are good or bad.

FIG. 16 shows an embodiment of a partial sectional structure of a solder ball joint of a chip-size tape BGA package according to the present invention.

FIG. 17 shows an embodiment of a sectional structure of a chip-size tape BGA package according to the present invention.

[Explanation of symbols]

1, 20, 40, 51, 70, 90, 111, 121 ...
LSI chip, 2,41,52,91,122 ... Al pad, 3,27,46,63,115,123 ... organic elastic body, 4,42,112,124 ... polyimide film,
5, 26, 35, 56, 57, 76, 93 ... Cu wiring,
6, 43, 59 ... solder pad, 7, 24, 44, 6
0,127: Inner lead, 9,48,80,10
2,116,129: solder ball, 10, 29, 49, 13
0: sealing resin, 11, 36, 131: Cu core lead, 1
2,82 ... Au plating film, 13,134 ... Cu-Sn compound layer, 14,117,135 ... Cu-Sn-Au alloy layer, 21,71 ... electrode pad, 22, 30, 55 ... organic film, 23 ... Pad, 25, 39, 45, 61, 6
2,79,98,99,128 ... Plating resist, 2
8, 65: solder ball bump, 31: reel winding opening, 32: inner lead forming opening, 33, 3
7, 114, 133 ... Au plating, 34, 77, 95,
113, 126: Cu land, 38: Tape substrate, 47
... Reinforcement plates, 50,64 ... Au pub, 53,101 ... Adhesive, 54 ... Heat sink, 58 ... Cu plating through hole, 72,88,100 ... Au wire, 73 ... Au ball, 74,75 ... Tab, 78 ... Inner bonding pad, 81,103 ... Mold resin, 83 ... Heat stage, 84 ... Heater, 85 ... Suction port, 86 ... Exhaust direction, 87 ... Tab hanging, 92 ... Organic insulating plate, 94 ... Bonding pad, 96 ... Through Hall, 97 ... Au-Cu
-Sn alloy layer, 125 ... Cu conductor part, 132 ... Ni plating, 136 ... Sn-Ni-Au alloy layer, 333 ... Cutting opening.

Continued on the front page (72) Inventor Kazuya Takahashi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Masahiro Koizumi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Research Laboratories (72) Inventor Toshiaki Morita 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Research Laboratories (72) Ryosuke Kimoto Kamizuhoncho, Kodaira, Tokyo 5-22-1, Hitachi Microcomputer System Co., Ltd. (72) Inventor Yukiharu Akiyama 5-2-1, Kamisumihonmachi, Kodaira-shi, Tokyo Semiconductor Company, Ltd. 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo In-house Semiconductor Division, Hitachi, Ltd. (72) Inventor Masanori Shibamoto 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo In-house, Semiconductor Division of Hitachi, Ltd. (72 Inventor Tomoaki Shimoishi 5-chome, Josuihoncho, Kodaira-shi, Tokyo Issue date Tatsucho LSI Engineering Co., Ltd. in

Claims (10)

[Claims] 1. A semiconductor device comprising: a lead connected to a semiconductor chip; and a solder bump bonded to the lead, wherein at a bonding interface between the lead and the solder bump,
Cu in the lead portion and solder in the solder bump,
A semiconductor package which is bonded at least via a Cu-Sn-Au alloy layer. 2. The semiconductor package according to claim 1, wherein a surface of said lead portion is plated with Au having a thickness of 0.5 μm or more. 3. The semiconductor package according to claim 1, wherein said Cu and said Cu—Sn—Au in said lead portion.
A Cu-Sn alloy layer is interposed between the semiconductor package and the alloy layer. 4. The semiconductor package according to claim 1, further comprising an organic resin film attached around said bonding interface. 5. The semiconductor package according to claim 1, wherein said solder bump is located at a central portion of said semiconductor chip. 6. The semiconductor package according to claim 1, wherein said solder bump is a solder ball bump. 7. The semiconductor package according to claim 1, wherein a surface of said Cu in said half-lead portion is plated with Ni of 0.3 μm or less, and Au is plated on said Ni plated. Semiconductor package. 8. A semiconductor device comprising: a substrate on which a semiconductor chip is mounted; a pad portion located on a surface of the substrate and electrically connected to the semiconductor chip; and a solder bump joined to the pad portion. At the bonding interface between the bad part and the solder bump,
Cu in the pad portion and solder in the solder bump,
A semiconductor package which is bonded at least via a Cu-Sn-Au alloy layer. 9. A first step of plating a surface of said pad portion of a lead portion connected to a semiconductor element and having a pad portion made of Cu with Au, and forming a solder bump on said surface plated with Au. A second step, and after the second step, at least Cu-S is formed on the bonding interface between the solder bump and the pad portion by an aging process.
a third step of forming an n-Au alloy layer. 10. The method of manufacturing a semiconductor package according to claim 7, wherein said Au plating has a thickness of 0.5 μm or more.