JPH10293581A - Musical sound frequency modulating device and method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To variously change the start of frequency modulation by providing a means for generating the initial phase information of the periodic change of modulation information and a means for starting the generation of the periodically changing modulation information form a phase complied with the generated initial phase information. SOLUTION: A processing program for generating a musical sound signal, timber data concerning a waveform and envelope and the waveform data themselves, etc., and stored in ROM 20, a read-out address is controlled by a ROM address control circuit 31 and reading out of the processing program or the timber data and reading of the waveform data are changed over to each other. The processing program read out of the ROM 20 is sent to the CPU of a key assigner circuit and various kinds of processings are executed. The initial phase information of the periodic change of modulation information is generated and the generation of the periodically changing modulation information is started from the phase complied with the generated initial phase information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument frequency modulation apparatus and method for performing frequency modulation by changing the generation speed of waveform data.

[0002]

2. Description of the Related Art Heretofore, as such a musical tone frequency modulation device for an electronic musical instrument, the present applicant has filed an application that modulates the frequency by changing the generation speed of waveform data (Japanese Patent Application No. Hei.
-22883). In this method, a plurality of pieces of modulation information for changing the reading speed of waveform data are stored in advance, and the reading speed of musical tone waveform data is changed based on the modulation information. According to this, it is possible to store a plurality of pieces of modulation information according to a change in tone color, tone length, and the like, or a change in one musical effect, with one modulation device, and it is possible to freely change the modulation content quite widely. The modulation content can be changed according to the timbre, the tone length, etc. In addition, all musical effects by frequency modulation can be realized with one modulation device, and the optimum modulation content for each musical tone can be easily obtained. Obtainable.

[0003]

SUMMARY OF THE INVENTION The present invention further improves this tone frequency modulating device, and variously modifies the start state of frequency modulation to realize various tone frequency modulating devices and methods for electronic musical instruments. It is intended to provide.

[0004]

According to the present invention, in order to achieve the above object, the present invention generates initial phase information of a periodic change in modulation information, and generates a periodic phase from a phase corresponding to the generated initial phase information. The generation of modulation information that changes to
Accordingly, the initial phase of the periodic change of the frequency modulation, that is, the start phase of the frequency modulation is changed in accordance with the generated initial phase information, and the start of the frequency modulation can be changed in various ways.

[0005] Here, the waveform data means musical sound waveform data representing a waveform of a sound in the natural world such as a musical instrument sound such as a piano, a violin, a drum or the like, a human voice, or a real-time sine synthesis.
Sine wave, triangle wave, used for M sound source, PD sound source, etc.
All waveform data which are elements of musical tones, such as basic waveform data representing basic waveforms such as a square wave and a sawtooth wave, are included.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION

1. FIG. 3 shows an overall circuit diagram of the present invention. Each key of the keyboard 1 and each switch of the timbre switch 2 are scanned by the key assigner circuit 30 and have a pitch corresponding to the operation key. Is assigned to an empty channel of the 16-channel tone generation system.
The contents of the channel assignment are stored in the assignment memory circuit 32. The keyboard 1 instructs the emission of musical tones, and may be replaced with a stringed instrument, a wind instrument, a percussion instrument, an organ-type instrument, or the like.

The key pressing pressure of each key of the keyboard 1 is
The pressure is detected by a pressure sensor provided for each key, and is converted into digital after-touch data indicating the key press pressure by an AD converter, and is sent to a CPU 300 described later.
Further, the key pressing speed of each key of the keyboard 1 is detected by a detection circuit as selection initial touch data indicating a shift time of the on-timing of a plurality of step switches provided for each key, and is sent to a CPU 300 described later.

The ROM 20 stores a processing program for generating a tone signal, tone color data relating to a waveform and an envelope, the waveform data RD itself, and the like. Reading of the program or tone data and reading of the waveform data RD are switched. R
The processing program read from the OM 20 is sent to a CPU 300 (to be described later) of the key assigner circuit 30 to execute various types of processing, and the timbre data related to the waveform and the envelope read from the ROM 20 is also stored in the empty The waveform data RD itself written in an area corresponding to the channel and further read from the ROM 20 is sent to the waveform data decompression interpolation circuit 50. In the assignment memory circuit 32, the frequency number speed data F corresponding to the operation key of the keyboard 1 is stored.
S is also written in the area corresponding to the empty channel.

The frequency number speed data FS is
The frequency number accumulator 40 sequentially accumulates the data for each channel, and stores the data in the ROM 20 through the ROM address control circuit 31.
Is provided as read address data, and waveform data RD
Is read out at a speed corresponding to the frequency number speed data FS, that is, at a speed corresponding to the pitch, and is input to the waveform data expansion interpolation circuit 50. Read waveform data RD
Are stored in the ROM 20, and these selections are made by bank data read from the assignment memory circuit 32.

In the waveform data decompression interpolation circuit 50, the differential data read from the ROM 20 in a data compressed state is decompressed, and an interpolation point between sample point points of each waveform data RD is obtained. The signal is sent to the multiplication circuit 70. This interpolation is performed by the frequency number accumulator 4
This is performed using a part of the frequency number accumulated value FA starting from 0.

The data relating to the envelope from the assignment memory circuit 32 is stored in the envelope generator 6.
0 to generate an envelope waveform, which is sent to the multiplying circuit 70. The multiplication circuit 70 multiplies each sample value of the expanded interpolation waveform data IP by each sample value EA of the envelope waveform, shifts the data by the shift circuit 80, and accumulates the data for each sequence by the sequence accumulation circuit 90. And the sound system 11 via the DA converter 100.
Sound is output from 0.

The envelope generator 60 sends the current phase value PH of the envelope waveform to the assignment memory circuit 32, and acts to output envelope data for the next new phase. Further, the frequency number accumulator 40 is output from the envelope generator 60.
, An on-event signal is sent at the key-on timing, and accumulation of the frequency number speed data FS is started.

Further, a data length signal D816 is sent from the envelope generator 60 to the waveform data decompression interpolation circuit 50, and selection is made whether interpolation of the waveform data RD is performed or not. The data length signal D816 is the waveform data R
D indicates whether the data consists of two 8-bit sample values or 10-bit sample values and 6-bit difference data, and a 10-bit sample value and 6-bit difference data are read out. At this time, interpolation of the waveform data RD is performed.

The shift circuit 80 shifts down the multiplied tone data in accordance with the magnitude of the envelope power data EA12 to 15 which are the upper bits of the envelope accumulated value EA, and falls when the decay and release are attenuated. This is to make the sound more exponential and closer to natural sound.

In the DA converter 100, four tone generation systems are formed in a time-division manner. In the sequence accumulating circuit 90, any one of the tone accumulating circuits 90 is provided in accordance with the sequence data GR from the assignment memory circuit 32. Is determined whether or not the musical sound data is to be sent to the generation system.

The series accumulating circuit 90 is also supplied with a waveform folded signal FDU from the frequency number accumulator 40. The waveform folded signal FDU generates the first half of one waveform of the waveform data. After that, when the second half-waveform is generated, the level becomes high level, whereby the tone accumulation data 90 is set to a value obtained by inverting the tone data by plus or minus. Further, a DA gate signal is also given to the series accumulation circuit 90 from the key assigner circuit 30.
Output control of tone data to the -A converter 100 is performed.

The system clock generator 10 supplies various circuits 30, 40, 50, 60, 90 of FIG. 1 with various clock signals CK 1, CK 1,
CK2, CK3, CK4, etc., and their divided, logical sum, logical product, etc. are given.
Timing control of each circuit is performed.

2. ROM 20 FIG. 6 shows the stored contents of the ROM 20.
20 is divided into 16 bank areas “0” to “15”, and each bank area has addresses “0000 н (н is a symbol indicating a hexadecimal value)” to “FFFF н”. Bank "0" from "0000н" to "0FFF"
“н” is a use area of the CPU RAM 301, the assignment memory 320, the modulation operation RAM 331, and the like for the CPU 300, and “1000 н” to “1FFF н” are use areas of the MMU latch 310 described later, and “2000”.
н ”to“ FFFFн ”store processing programs for generating musical sound signals. "0" of bank "1"
The timbre coefficient data for selecting and determining the contents of the waveform and the envelope are 128 000 」to 3FFF」.
Tones are stored.

From "4000" in bank "1" to "FFFF" in bank "15", one selected tone color is read out for each bank. (A) (B) The two tone waveform data RD are the same. It is stored in the address. The musical sound waveform data RD includes musical sound waveform data representing the waveform of a sound in the natural world, such as the sound of a musical instrument such as a piano, violin, or drum, or the sound of a human voice, or real-time sine synthesis, FM sound source, PD
In addition to basic waveform data representing basic waveforms such as sine, triangular, rectangular, and sawtooth waveforms used for sound sources, noise sound waveforms, etc., and waveforms obtained by combining these, multiple specific frequency bands corresponding to specific formants Any kind of waveform data which may be a plurality of types of waveforms obtained by synthesizing each frequency component corresponding to a spectrum group, or a PCM waveform utilizing a loop top, a loop end, etc. May be. The storage area of the timbre data is shifted from the storage area of the processing program by the MMU address data described later.

FIG. 7 is a diagram showing the “0000” of the bank “0”.
н ”to“ 0FFFн ”, showing the detailed contents of the area.
“0н” to “07FFн” are used areas for the CPU RAM 301, “0800н” to “08FFн” are used areas for the assignment memory 320, and “0900н” to
“09FFн” is a use area for the modulation calculation RAM 331, and “0A00н” to “0EFFн” are not used.
“0F00н” to “0FFFн” are used areas for interfaces between circuits. Of these, "0F00
н ”to“ 0F0Fн ”represent an input buffer 307 and an output latch 306 in the keyboard 1 described later.
Etc. are used areas for interfaces such as “0F10
н ”to“ 0F1Fн ”are the tone switches 2 to be described later.
Area used for the interface of the input buffer 305, the output latch 304, etc.
“F20 н” to “0F2F н” are used areas for the MMU latch 310 also described later,
“0F3Fн” is also a use area for the timer 302 described later, and “0F40н” to “0FFFн” are not used.

FIGS. 8 and 11 show the contents of the above-described tone color coefficient data. One tone color is composed of four data of key scaling 0, 1, 2, and 3 and one modulation coefficient. ing. Key scaling 0, 1, 2, 3
Divides the keyboard 1 into four ranges, and changes the harmonics and noise components, and changes the envelope waveform according to this range. Is stored in order to change. The modulation coefficient is data for subtly changing the tone frequency during emission of one tone to realize a tone that is more natural.

The timbre coefficient data of the waveforms 0 to 3 of the key scalings 0 to 3 include those for the tone waveform and those for the envelope. The tone color coefficient data for the tone waveform includes bank data and key data. It comprises number bias data (KEY NO bias), cent bias data (CENT bias), data length signal data D816, sequence data GR, initial frequency number data, loop top data, and loop end data.

With respect to the tone color coefficient data for the envelope, two envelopes (A) and (B) are selected for one tone color assigned to one channel. Each of the two envelope data (A) and (B) exists for each of four phases PH0, PH1, PH2, and PH3 of, for example, attack, decay, sustain, and release. The envelope data for each phase further includes envelope level data EL, envelope addition / subtraction signal data EDU, thin out data TH, and envelope speed data ES.

The tone color coefficient data for the modulation coefficient includes modulation speed data MSPD and modulation depth data MDE.
P, phase speed data PSPD, key scale selection signal data KS, key touch selection signal data KT, initial after selection signal data I / A, return signal data RET, start trigger selection signal data TRG,
It consists of initial phase angle data (initial MSACC).

The bank data is used to select and designate one of the fifteen types of tone waveform data RD, and for each tone assigned to one channel,
(A) and (B) Two waveforms are selected.

The key number bias data is input to the keyboard 1 in order to realize the pitch specified by the keyboard 1 with respect to the reference foot range (pitch) of the tone color data.
Bias data that is adjusted for the designated pitch. For example, when the tone color coefficient data is based on 4 feet and the tone waveform data RD is based on 8 feet, if the key number bias data is "12 (0001100 в (в is a symbol indicating that it is a binary number))", 1 By increasing the octave, the foot range of the musical tone waveform data RD can be matched with the foot range of the timbre coefficient data.

When the tone color coefficient data is based on 16 feet, the key number bias data is set to "-12 (1
110100）), and the foot range of the musical tone waveform data RD can be made to match the foot range of the timbre coefficient data by one octave. This "1
The value of "2" corresponds to the pitch number of one octave, and if the foot range difference is one octave or less, the key number bias data is also "12" or less.

If the foot range difference is equal to or less than the integer value of one pitch difference, the cent bias data indicates a decimal value equal to or smaller than the integer value.
The data can be shifted in units of 100/64 = approximately 1.56 cents, which is divided into 64 equal parts by the data of bits.
The values of the key number bias data and the cent bias data are determined on the same basis as the key number data and the cent data of FIG. 21 described later.

The data length signal D816 indicates whether the waveform data RD consists of two 8-bit sample values or a 10-bit sample value and 6-bit difference data, as described above. As described above, the data GR0, GR1 also indicate to which of the four tone generation systems the tone data ST after the multiplication is assigned.

The initial frequency number data is shown in FIG.
As shown in FIG. 7, the frequency number speed data FS is sequentially accumulated, and the frequency number accumulated value at the start at the time of reading out the waveform data RD is shown. The loop end data indicates the accumulation of the frequency number speed data FS. The loop number data indicates the frequency number accumulated value FA at a point where the accumulation direction of the frequency number speed data FS is turned from the addition direction to the addition direction. , FIG.
By changing the frequency number accumulated value FA between the loop top and the loop end as shown in FIG.
Half waveform data can be read out in a continuous waveform state.

The waveform return signal FDU shown in FIG. 18 is the most significant bit data of the accumulated frequency number FA. The generation of the first half wavelength of one wavelength of the waveform data is completed, and the generation of the second half wavelength is completed. The signal FDU is set to a high level, and based on this signal FDU, switching of the addition / subtraction operation of the frequency number accumulated value FA and switching of the plus / minus of the sample value (amplitude value) of the waveform data (tone data) are performed. Will be

The envelope level data EL in the envelope data indicates the accumulated value of the envelope at the final point of each of the phases PHO to PHO3 of the ack, decay, sustain, and release of the envelope waveform. It indicates whether the envelope accumulated value EA of PHO-3 is to be added or subtracted. The envelope speed data ES of the envelope data is stored in each phase PHO to
3 is data indicating the acceleration / deceleration of the envelope accumulated value EA. The larger this value is, the larger the slope of the envelope waveform becomes. The envelope speed data ES and the envelope level data EL are determined according to a key pressing speed of a key of the keyboard 1 or key touch data corresponding to a key pressing pressure.

The thin-out data TH in the envelope
Is data indicating the thinning rate of the latch for taking in the envelope accumulated value EA into the accumulation system of the envelope accumulated value EA of each phase PHO-3, and the latch for taking in the original envelope accumulated value EA is a repetition line. This is performed once in a time slot for all channels. When this data is "11", there is no thinning out. When it is "10", it is taken once every four times, when it is "01", it is taken once every 16 times, and when it is "00", it is taken once every 64 times.

0 and 1 indicate a low state of a binary logic level, h
It shows the high state. With this thin out (take-in latch thinning), even with the same envelope speed data, the envelope speed can be increased by 1 ×, 4 ×, or 16 times.
Can be changed by a factor of 64 or 64. This thin-out data TH may also be changed in accordance with the key pressing speed of a key of the keyboard 1 or key touch data corresponding to the key pressing pressure.

Modulation speed data MS of modulation coefficient data
The PD is data according to the frequency modulation cycle as shown in FIG. 1A, and the modulation depth data MDEP is data according to the frequency modulation amplitude as shown in FIG. The phase speed data PSPD is data for determining the phase times of the four phases 0 to 3 of the frequency modulation for one musical tone. As shown in FIG. 1 (2), the larger the value, the shorter the phase time Become.

The key scale selection signal data KS is used to select whether the frequency modulation content is changed (“1”) or not (“0”) according to the key scale content. Modulation speed data MSPD and modulation depth data M for frequency modulation according to the pitch
DPE, phase speed data PSPD can be changed.

The key touch selection signal data KT is for selecting whether to change the frequency modulation content (“1”) or not (“0”) according to the key touch content. Modulation speed data MSPD, modulation depth data MDP of frequency modulation according to speed (initial touch) and strength (after touch)
E, phase speed data PSPD can be changed.

Initial after-selection signal data I / A
Selects whether to use the initial touch data (key pressing speed) IKT or the after touch data (key pressing pressure) AKT as the key touch data KTD when changing the content of the frequency modulation according to the key touch content. Is what you do. Thus, of the phases 0, 1, 2, and 3 shown in FIGS. 1 and 2, the first phase can use the initial touch data IKT, and the later phases can use the after touch data AKT.

After the final phase 3 ends, the return signal data RET returns to the beginning of the phase 2 and repeats the phase (2) and the phase (3) (“1”), or continues the phase 3 as it is. ("0"). FIG. 1 (3) shows a state in which the return up to the phase (2) is repeatedly performed.

The start trigger selection signal data TRG is
A trigger signal for starting frequency modulation is selected. The trigger signal includes a key-on event signal ON EVNT and a key-on summing signal ON SUMM as shown in FIG. When the start trigger selection signal data TRG = 0, the key-on event signal is selected,
Even when there are a large number of simultaneously operated keys, frequency modulation starts at the on timing of each key. Further, if the key-on summing signal is selected by the start trigger selection signal data TRG = 1 and there is a key that is already depressed, frequency modulation does not start even if another key is turned on repeatedly.

Initial phase angle data (initial MS
ACC) indicates the phase angle of the modulation waveform at the start of frequency modulation, as shown in FIG.
000в ”with a phase angle of ± 0 degrees,“ 01 0000 000
0в ”, phase angle +90 degrees,“ 10 0000 0000 ”
в ”phase angle ± 180 degrees,“ 11 0000 0000 ”
в ”results in a phase angle of −90 degrees. Of course, it is also possible to take an intermediate value between these values.

As described above, since the ROM 20 stores the processing program for generating and emitting a musical tone and the musical tone data representing the content of the musical tone, only one memory for storing the program and the data is required. The circuit configuration can be simplified accordingly.

The storage contents of the addresses "74 H" to "7 F H" are different between FIG. 8 and FIG. This is shown in FIGS.
FIG. 10 shows an example in which the content of the frequency modulation is corrected based on the key scale data KSD and the key touch data KTD by the operation processing data, and FIGS. 11 to 13 show the scale table (KS) (ROM) 231 and the touch panel. This is because an example in which the contents of the frequency modulation are corrected based on the key scale data KSD and the key touch data KTD by the data read from the table (KT) (ROM) 235 is shown.

Such an arithmetic processing or table 23
The reading from 1, 235 is realized by directly multiplying the key scale data KSD and the key touch data KTD by the modulation speed data MSPD, the modulation depth data MDEP and the phase speed data PSPD, thereby realizing a musical tone closer to a natural sound. To do that. Of course, the key scale data KSD and the key touch data KTD may be directly multiplied as they are.

The above-mentioned addresses "74 н" to "7F н" in FIG.
The slope data SLOPE and the bias data BIAS stored at the addresses are coefficient data of the above-described arithmetic processing. Such coefficient data is obtained by using the modulation speed data MSPD and the modulation depth data MDEP for each of the key scale data KSD and the key touch data KTD.
And phase speed data PSPD. The coefficient data has different values for different timbres, but may be the same. The most significant bit of the slope data SLOPE indicates plus or minus of the data. The expression for this calculation process is the key scale data KSD
Is f (S) and key touch data KTD is j (T), g (S) = SLOPE (KS) × f (S) + BIAS
(KS) k (T) = SLOPE (KT) × j (T) + BIAS
(KT).

FIG. 9 is a graph showing these equations. Modulation speed data MSPD increases as input key scale data f (S) and input key touch data j (T) increase, but modulation depth data MDEP and phase speed data PSPD decrease conversely. In addition, by this calculation processing, the range of possible values of the converted output key scale data g (S) and output key touch data k (T) is determined by the input key scale data f (S) and the input key touch data j ( It becomes narrower than the range of possible values of T).

These arithmetic expressions are represented by modulation speed data M
The key scale data KSD and the key touch data KTD are the same for each of the SPD, the modulation depth data MDEP, and the phase speed data PSPD, but may be different. Also, the arithmetic expressions may not be linear functions but may be more complicated expressions, all the arithmetic expressions may be the same, or may be different expressions.

The above-mentioned addresses "74 н" to "7F" in FIG.
Table number data TBL stored at address “н”
NO. Indicates the number of the table in reading out the tables 231 and 235 described above. Table 23
As shown in FIG. 12, reference numerals 1 and 235 each include 64 table groups. These table groups correspond to each of the above-mentioned 64 timbres.
BL NO. Specifies this. Of course, these tables may be common to each tone.

The modulation speed data MSPD includes input key scale data f (S) and input key touch data j.
The larger the (T) is, the larger the modulation depth data M
The DEP and the phase speed data PSPD decrease conversely. In these tables 231 and 235, the key scale data KSD and the key touch data KTD are the same for the modulation speed data MSPD, the modulation depth data MDEP, and the phase speed data PSPD, but may be different. The data contents of the tables 231 and 235 are not limited to those in FIG. 12, and the data contents of each table may be the same.

[0050] 3. Correction Circuit 200a (200b, 200c) FIGS. 10 and 13 show the key scale data KS described above.
Correction circuit 200a (200b, 200b) for correcting the content of frequency modulation based on D and key touch data KT.
FIG.

The correction circuits 200a, 200b, 200
c is incorporated in three places in the modulation operation circuit 33 that performs the modulation operation processing shown in FIGS. Then, the modulation speed data MSPD and the modulation depth data M
The DEP and the phase speed data PSPD are corrected according to the key scale data and the key touch data.

In FIG. 10, the modulation speed data MS
PD is converted by a multiplier 210 into converted key scale data g.
(S) is multiplied, and correction according to the key scale data KSD is performed. Next, in the multiplier 213, the converted key touch data k (T) is multiplied, corrected according to the key touch data KT, and output.

In FIG. 10, the input key scale data KSD and key touch data KTD are selected key scale data SKS, selected initial touch data SIKT, and selected after touch data SAKT. Is added. This indicates that one value is selected from the key scale data KSD and the key touch data KTD of a plurality of keys that are simultaneously pressed.

Specifically, the selected key scale data SK
S is the average of the lowest key number and the highest key number among the pitches (key numbers) of currently assigned musical tones. In addition, the selection key touch data S
KT is the maximum value among the musical sounds currently being played. Of course, other values such as bass priority, treble priority, back-push priority, and first-push priority may be used. These selection processes are executed by the CPU 300. It should be noted that the key scale data KSD and the key touch data K
The content of the frequency modulation may be modified based on the TD.

The selected key scale data SKS is input to the function generator 211 via the selector 212. The function generator 211 has the slope data S described above.
LOPE (KS) and bias data BIAS (KS) are also given, and the above-mentioned g (S) = SLOP (KS) ×
The arithmetic processing of f (S) + BIAS (KS) is executed,
The converted key scale data g (S) is input to the multiplier 210. The function generator 211 can be configured by a multiplier, an adder, and a selector used when an overflow or underflow occurs, but can also be configured by a microcomputer that performs arithmetic processing based on a program.

The fixed data FIX is also supplied to the function generator 211 via the selector 212, and when the fixed data FIX is selected by the selector 212, the contents of the frequency modulation are corrected in accordance with the key scale data. Is not done. The select signal of the selector 212 is the key scale selection signal data KS described above.

The above selected initial touch data SIKT
And the selected after touch data SAKT are the selector 2
At 16, one is selected, and further input to the function generator 214 via the selector 215. Function generator 21
4, the above-mentioned slope data SLOPE (KT) and bias data BIAS (KT) are also given, and the above-mentioned k (T) = SLOPE (KT) × j (T) + BIA
The arithmetic processing of S (KT) is executed, and the converted key touch data k (T) is input to the multiplier 213. Like the function generator 211, the function generator 214 can be composed of a multiplier, an adder, and a selector used when an overflow or an underflow occurs, but performs arithmetic processing based on a program. It can also be constituted by a microcomputer.

The fixed data FIX is also supplied to the function generator 214 via the selector 215. When the fixed data FIX is selected by the selector 214, the contents of the frequency modulation are corrected in accordance with the key touch data. Is not done. The select signal of the selector 215 is
This is the key touch selection signal data KT described above. Further, the select signal of the selector 238 is the above-mentioned initial after-selection signal I / A. This function generator 2
The calculation contents of 11, 214 are as shown in FIG. 9 described above.

The selection key data SKS, the selection initial touch data SIKT, the selection after touch data SAKT, the slope data SLOPE (KS),
SLOPE (KT), bias data BIAS (K
S), BIAS (KT), fixed data FIX, selection signal data KS, KT, and I / A are
The correction circuit 200a (200b, 200c).

In this case, since the correction circuit 200a corrects the modulation speed data MSPD, the slope data SLOPE (KS), SLOPE (KT) and the bias data BIAS (KS), BIAS (KT) are the modulation speed data MSPD. SLOPE for those about MSPD
(MSPD) and BIAS (MSPD), and the correction circuit 200b corrects the modulated depth data MDEP to obtain slope data SLOPE (KS) and SLOPE.
PE (KT) and bias data BIAS (KS), B
IAS (KT) is for SLOPE (MDEP), BIAS (MDEP) for modulated depth data MDEP
Further, since the correction circuit 200c corrects the phase speed data PSPD, the slope data SLOPE (KS) and SLOPE (KT) and the bias data BIAS (KS) and BIAS (KT) are used for the phase speed data PSPD. SLOPE of thing
(PSPD) and BIAS (PSPD).

FIG. 13 shows a modification circuit 200a (200b,
FIG. 12C shows another embodiment of FIG.
As shown in (1), the contents of the frequency modulation are corrected by reading from the tables 231 and 235.

The correction circuit 200a (200b, 200
00c) is the correction circuit 200a (200b, 2b, 2b) of FIG.
The function generators 211 and 214 of 00c) are replaced with a scale table (KS) 231, a touch table (KT) 235, a limiter 232, and a limiter 236.

The selected key scale data SKS or fixed data FIX from the selector 212 is supplied to the limiter 232
Is compressed from 7-bit data to 4-bit data, and the above-mentioned 6-bit table number data TBL NO. (K
S) is added to the higher order, and is input to the scale table 231 as address data. This scale table 2
The converted key scale data is input from 31 to the multiplier 210, and is multiplied by the modulation speed data MSPD, the modulation depth data MDEP or the phase data PSPD.

Further, the selected initial data SIKT or the selected after touch data S from the selector 215 are selected.
AKT or fixed data FIX is
The 4-bit data is compressed to 4-bit data, and the 6-bit table number data TBL NO. (KT) is added to the high order, and is input to the touch table 235 as address data. The conversion key touch data is input from the touch table 235 to the multiplier 213, and is multiplied by the modulation speed data MSPD, the modulation depth data MDEP, or the phase data PSPD.

The data storage contents of the scale table 231 and the touch table 235 are the same as those of the above-described 7B (2).
As shown in FIG.

The limiter 232 determines that all of the input 7-bit selection key scale data SKS that are lower than the high pitch C2 are high pitches C2, those that are higher than the high pitch C7 are high pitches C7, and that of the high pitch pitches C2 to C7 are Is "0000 (0)""0001(1)"
.. Are output as “1111 (15)”. Specifically, the key number data of the treble C2 is subtracted from the input selected key scale data SKS, and 4-bit data is output by removing the most significant bit and the lower 2 bits. In this case, all the bits whose most significant bit is “1” are “1111 (15)”.

Therefore, the limiter 232 is realized by a logic circuit that performs such a conversion process. Of course, it can also be realized by a microcomputer that performs arithmetic processing based on a program. This is the same for the limiter 236 described below. The reason why the key scale data KS below the treble C2 and above the treble C7 is ignored is that this range is not used much. Of course, the output may be performed in a form other than the 4-bit data.
2 may be omitted and the selected key scale data SKS may be directly input to the scale table 231.

The limiter 236 performs the same conversion as that of 232. Of the 7-bit selection key touch data SKT to be inputted, those having a small value and those having a large value are ignored, and the 4-bit data of the 4-bit data is ignored. It is output in the form. For example, of the key touch data KT, “16” or less and “112” or more are ignored, and data of “16” to “112” are grouped into six pieces, and “0000 (0)” “00”
01 (1) "..." 1111 (15) ". Needless to say, the same conversion as the limiter 232 may be performed, or the limiter 236 may be omitted and the selection key touch data SKT may be directly input to the touch table 235.

The other contents are the same as those of the correction circuit 20 shown in FIG.
0a (200b, 200c). The table number data TBL NO. (KS), TBL N
O. (KT) is also the correction circuit 200a, 200b, 200
It takes a different value for each c.

4. Key Assigner Circuit 30 FIG. 4 shows the key assigner circuit 30 in which the CPU 3
00 indicates that the applied master clock signal φ (CK2) is
It can operate only when it is at the high level.
When the master clock signal CK2 is at the high level “1”, the data bus line and the address bus line
Data relating to U300 flows, and when low level “0”, data irrelevant to CPU 300 flows.

4-1. ROM address control circuit 31 Although address data CA0 to CA15 for accessing the ROM 20 and various memories from the CPU 300 are 16-bit data, the lower 11 bits CA1 excluding the least significant bit are used.
11 are supplied to the selector 313. The upper 4 bits CA12 to 15 are added with 4-bit data of "0000" in the upper bits, and are input as 19-bit address data together with the lower 11 bits CA1 to 11 through the B input of the selector 312 to the ROM2 through the selector 313.
0, and the processing program is mainly read.

When the CPU 300 reads out tone color data and other data other than the processing program, the CPU 3
00, 8-bit MMU address data is output through the data bus line, and this is added to the lower 11 bits CA1 to CA11 through the MMU latch 310 through the selector 312.
OM20.

FIG. 23 shows the switching state of the address data. FIG. 23 shows that although the address data of the ROM 20 is 19 bits, the address data of the CPU 300 is 16 bits. And addition of MMU address data.

Thus, the MMU address is added,
By adding “0000”, the reading of the program and the reading of the timbre data can be easily switched.
Even if the read address data of 00 is smaller in the number of bits than the read address data of ROM 20, the entire area of ROM 20 can be read.

Therefore, the bank "0" of the ROM 20 is connected to the CP
Since the U300 can be directly accessed without using the MMU latch 310, a processing program dedicated to the CPU 300 is stored. Further, the CPU 300 accesses, for example, the address “3524 н” of the bank “1” by M
"13" is set in the MU latch 310, and the CPU 30
If "1524H" is set as the address data of 0, the combined address data becomes "13524H", and the address "3524H" of the bank "1" is accessed. In this case, the selector 312 cancels the most significant four bits “1н” of the address data “1524н” of the CPU 300.

The upper 4-bit data CA12 to CA15 are also supplied to a comparator 311. The comparator 311 is also supplied with 4-bit f (x) data. When the two data do not match, "0000" is output. And the top four
Bit address data CA12 to CA15 are selected. When both data match, a match signal is supplied from the comparator 311 to the selector 312, and the MMU
Latch 310 is selected. Therefore, when the upper four bits of the address data CA12 to CA15 do not match the f (x) data, the processing program of the CPU 300 is read, and when they match, the tone color data and the like are read.

The f (x) data may be selected and set by the CPU 300 or may be a value fixed in advance.
When this f (x) is fixed to “1 н”, the MMU of “1000 н” to “1FFFF” of the bank “0” of the RAM 20 is obtained.
When the area for the latch 310 is accessed and f (x) is fixed to “0 н”, the area of “0000 н” to “0FFF н” of the bank “0” of the RAM 20 is accessed.

The selector 313 is also supplied with bank data read by the CPU 300 from an assignment memory 320, which will be described later, and frequency frequency accumulated values FA12 to FA26 from the frequency number accumulator 40. The waveform data RD of the corresponding bank is read out.

Data selector switching in the selector 313 is performed by a clock signal CK2 from the system clock generator 10, and as shown in the lower part of FIG.
Switching between reading the processing program and reading the sample value of the waveform data RD is switched. Of these, at the timing of reading the processing program,
(X) Switching between reading of a processing program and reading of timbre data is switched based on the data. These reading processes are repeatedly performed for 16 channels.

Of the data read from the ROM 20, the waveform data RD is sent to the waveform data decompression interpolation circuit 50 as it is, and the processing program and the timbre data are divided into two pieces of 8-bit data.
It is sent to the PU 300 or sent to the assignment memory 320 via the gate buffer 323. The data select switching in the selector 314 is performed by the CPU
Least significant bit CA0 of address data CA from 300
It is performed based on.

Thus, the data is taken in from the ROM 20 following the processing speed of the CPU 300. Further, even if the number of bits of data read from the ROM 20 is larger than the number of bits of the data bus line of the CPU 300, data processing can be performed smoothly.

4-2. Modulation operation circuit 33 In the modulation operation circuit 33, the modulation coefficient data in the timbre coefficient data corresponding to the timbre designated by the timbre switch 2 is CP
The modulation coefficient RAM, the key data, and the tablet data in the modulation coefficient RAM 331 are read out by the U300 in the modulation calculation RAM 331 in a time division manner for each stream by the CPU 300.
After the modulation operation is performed in step 3, the result is written into the modulation operation RAM 331 again as modulation data described below.

Using the modulation operation data MDATA, which is the final result of the modulation data, the modulation addition operation shown in FIG. 22 is performed for each channel of each stream, and the result is temporarily stored in an assignment memory. 320 are written in an area of modulation key number data (M KEYNO) and an area of modulation cent data (M CENT).

These values in the assignment memory 320 are sent to the frequency number accumulator 40, and frequency modulation is executed independently for each stream. This “modulation operation circuit 3
"3" is a "modulation operation processor", which can perform high-speed modulation operation.
At 00, this process can be performed by a program. The modulation operation circuit 33 includes a modulation operation RAM 33
1 and a circuit group for performing a modulation operation as shown in FIGS.

FIGS. 14 and 15 show the modulation operation RAM 331.
In the RAM 331, the modulation coefficient, key data and tablet data, modulation data, key scale coefficient data, and key touch coefficient data are stored for each of the three series 0 to 3 out of the four series 0 to 3 described above. Is stored. The modulation coefficient is 4 in the modulation waveform shown in FIGS.
For each of the three phases (0) to (3), modulation depth data MDEP, modulation speed data MSPD, phase speed data PSPD, key scale selection signal data KS, key touch selection signal data KT, initial after selection signal data I / A, Return signal data RE
T, start trigger selection signal data TRG, and initial phase angle data (initial MSACC). These data have already been described in the description of the timbre coefficient data in the RAM 20.

The key data and the doublet data are selected key scale data SKS, selected initial touch data SIKT, and selected after touch data SAKT.
, A key-on summing signal ON SUMM, a key-on event signal ON EVNT, and a timbre number. Selected key scale data SKS, selected initial touch data SIKT, selected after touch data SAKT, and key-on summing signal ON SUMM
And the key-on event signal ON EVNT have already been described in the description of the timbre coefficient data in the RAM 20, and are signals as shown in FIG. The tone number is
This is data representing a tone corresponding to the switch operated by the tone switch 2 described above.

The modulation data consists of phase speed accumulated data PSACC, modulation speed accumulated data MSACC, and modulation operation data MDATA. As shown in FIG. 1 (2), the phase speed accumulated data PSACC is accumulated data of the phase speed data PSPD, and indicates the elapsed time of each phase of the modulation.
The modulation speed accumulation data MSACC is accumulation data of the modulation speed data MSPD, as shown on the left side of FIG. 1A, and indicates an elapse point in one cycle of the modulation waveform. The modulation operation data MDATA is data indicating the magnitude of the modulation degree at each time, and includes modulation waveform data MWAVE described later and modulation depth data M indicating the modulation depth.
This is obtained by multiplying DEP.

The key scale coefficient data and the key touch coefficient data are also as described in the description of the tone color coefficient data in the RAM 20. Slope data SLOPE of key scale coefficient data and key touch coefficient data of FIG.
And the bias data BIAS are coefficient data of the operation formula in FIG. 9, and table number data TBNL of key scale coefficient data and key touch coefficient data in FIG.
O. Is data indicating the number of each table in FIG.

Of the above-described series 0 to 2, the series 0 is assigned to the upper keyboard of the keyboard 1, the series 1 is assigned to the lower keyboard, and the series 2 is assigned to the foot keyboard.
Different modulation contents can be set. Of course, different timbres and different modulation contents may be set for each channel. As described above, one modulation operation circuit 33 can set various modulation contents.

4-3. CPU RAM 301 FIG. 16 shows a part of the contents of the CPU RAM 301. The key-on signal KEY ON, the key number data KEY NO, the cent data CENT, and the sequence data G for musical tones assigned to the 16 channels, respectively.
R, after touch data, and initial touch data are stored for each channel as described above. Of these channels, channels CH0 to CH7 are allocated to stream 0, channels CH8 to CH14 are allocated to stream 1, and channel CH15 is allocated to stream 2.

The key-on signal KEY ON is signal data indicating that a key on the keyboard 1 is being pressed.
It becomes "1" when the key is on and "0" when the key is off. The key number data KEY NO is data indicating a key number corresponding to the designated pitch of the keyboard 1, and the cent data is
This is data indicating a fine pitch difference below the key number, and the frequency value corresponding to each data is as shown in FIG.

As described above, the series data GR indicates to which of the four tone generation systems the tone data ST after the multiplication is assigned. The after touch data is data indicating a key pressing pressure of the keyboard 1, and the initial touch data is data indicating a key pressing speed of the keyboard 1.

4-4. Assignment Memory Circuit 32 FIG. 17 shows the storage contents of the assignment memory 320 of the assignment memory circuit 32. The assignment memory 320 has a memory area for timbre data for 16 channels. ROM in area
20 is set. In this case, among the tone data to be set, the envelope data is EG0.
~ 15 are set in each envelope group area,
Other data is set separately for each channel area of CH0 to CH15.

The data set in CH0 to CH15 include bank data (A) and (B), envelope group data (A) and (B), and modulation key number data (MKEYN).
O), modulated cent data (M CENT), key-on signal data, data length signal data D816, sequence data G
R, initial frequency number data, loop top data, and loop end data. The data other than the modulation key number data (MKEY NO), the modulation cent data (M CENT), and the envelope group data (A) (B) are as described in the storage contents of the ROM 20.

The modulation key number data and the modulation cent data are, as shown in FIG.
The key number bias data and the cent bias data corresponding to the designated tone color and the modulation data MDATA for implementing frequency modulation described later are added and corrected to the EY NO and the cent data CENT. Is used as an accumulation step value of the read address data of the waveform data RD. This processing is performed by CPU 300, and channel 0
In the series 0 of 7, the series 0 in the modulation operation RAM 331
The modulation data of the sequence 1 is also used for the sequence 1 of the channels 8 to 14, and the modulation data of the sequence 2 is similarly used for the sequence 2 of the channel 15.

Envelope group data (A) (B)
Is an envelope group area E in which envelope data corresponding to the tone color of the channel area is stored.
This data indicates addresses G0 to G15. Since the tone color assigned to one channel is composed of two musical tones, there are two (A) and (B).
Accordingly, since there are two waveform data RDs, there are two bank data (A) and (B).
The envelope data set in EG0 to EG15 is also as described in the description of the storage contents of the ROM 20 described above.

The modulation key number data and the modulation cent data are shared for (A) and (B) two musical tones.
(A) (B) 2 according to one operation key of the keyboard 1
One musical tone is synthesized and output. This (A)
(B) Since the two musical tones have different bank data or envelope group data, the two musical tones have different timbres, and the envelope control is performed separately.

The data read from the assignment memory 320 is sent to the frequency number accumulator 40 and the envelope generator 60 via an AM (assignment memory) bus, or sent to the CPU via a gate buffer 322.
300. As for the 4-bit envelope group data (A) and (B), 2-bit phase data PA from the envelope generator 60 is added to the lower order via the latch 324, and 1-bit "1" is added to the upper order. Thus, a total of 7 bits are provided to the assignment memory 320 again via the selector 321, and the envelope level data EL, the syn-out data TH, the envelope speed data ES, etc. of the corresponding envelope are read out and sent to the envelope generator 60. Sent.

Through this selector 321, read address data which is a set of clock signals CK from system clock generator 10 is also applied to assignment memory 320, and access address data from CPU 300 is also applied.

When the power is turned on, the reset circuit 303
The U300 and the output latch 304 are reset. The sampling addresses of the tone switch 2 and the keyboard 1 are temporarily set in the output latches 304 and 306, and the input buffers 305 and 307 are set.
, The sampling result is input. Only one bit of the sampling data of the output latch 304 is used as a gate signal of the DA converter 100.

5. Modulation Calculation Circuit 33 FIGS. 24 and 26 show the modulation calculation circuit 33.
FIG. 24 is a circuit section for calculating the accumulated phase speed data PSACC, and FIG. 26 is a circuit section for calculating the modulation operation data MDATA.

First, in FIG.
31, phase speed data PSPD of each phase (0) to (3) read by the CPU 300
The selector 331 selects the data PSPD of the currently executing phase, adds it to the previous phase speed accumulated data PSACC by the adder 332, and outputs the phase speed accumulated data via the OR gate group 339 and the AND gate group 336. Output as PSACC.

The upper part of FIG. 25 shows the phase speed data P
It shows SPD and phase speed accumulated data PSACC, and is a 13-bit phase speed data PSP.
D is sequentially accumulated and the phase speed accumulated data PSA
CC. This phase speed accumulated data PSAC
As shown in FIG. 1C, the most significant bit PAL of C is the in-return data indicating that the repetitive modulation of the phases (2) to (3) is being performed.

The next upper 2 bits are PA 13 and 14 which are phase data indicating the phase at that time.
Indicates the phase (0), “01” indicates the phase (1), “1”
"0" is phase (2), and "11" is phase (3). Further, the next four bits PA9 to PA12 serve as weighting data (Rate) for moving the phase.

Referring to FIG. 24, phase data PA13, PA14 of phase speed accumulated data PSACC.
Is given to the selector 331 to select the phase speed data PSPD of the currently executing phase. This selected phase speed data PSPD
Is input to the correction circuit 200c, and correction according to the values of the key scale data KS and the key touch data KT is performed.

From the adder 332, the carry-out signal C
When out is output, return signal data RET =
When it is "0", "11 ... 1" is output as phase speed accumulated data PSACC from the OR gate group 339 via the AND gate 338, and this state is maintained, and as shown in (1) of FIG. As shown, the end point of the final phase (3) is reached, and the modulation state at this point is maintained. Also, when the return signal data RET = “1”, the upper PA 14 of the phase data is always set to “1” via the AND gate 340 and the OR gate,
As shown in (2) at the bottom of FIG.
Only (2) and “11 (3)” are repeatedly selected. At this time, the OR gate is released and the phase speed accumulated data P
The returning data PAL of the most significant bit of the SACC also becomes “1”.

The key-on summing signal ON SUMM and the key-on event signal ON EVN described in FIG.
Any of T is selected by the selector 333 by the start trigger selection signal TRG and then inverted by the inverter 334 to close the AND gate group 336, thereby setting the phase speed accumulated data PSACC to “0”.
0 ... 0 ". This inverter 33
4 is used as an initial signal CLK described later.

In FIG. 26, the modulation speed data MSPD of each phase read by the CPU 300 from the modulation calculation RAM 331 is selected by the selector 351 to select the modulation speed data MSPD of the phase currently being executed at the same time. The modulation speed data MSPD of the phase to be executed is selected.

The modulation speed data MSPD of the phase currently being executed is supplied to the multiplier 354 by the complement weight data (1).
−R) is given to the adder 356, and the modulation speed data MSPD of the phase to be executed next is multiplied by the weighting data R in the multiplier 353 to obtain the adder 356.
And both data are added. This adder 356
, The interpolation processing of the modulation speed data MSPD of the phase currently being executed and the modulation speed data MSPD of the phase to be executed next is performed.

The interpolated modulation speed data MSPD from the adder 356 is input to the correction circuit 200a, where correction is performed according to the values of the key scale data KS and the key touch data KT. Then, the modified modulation speed data MSPD is added to the previous modulation speed accumulated data MSACC by an adder 362, and is added via a selector 363 to the modulation speed accumulated data MSA.
Output as CC. This modulation speed accumulated data M
Figure 2 shows the relationship between SACC and modulation speed data MSPD.
As shown in FIG.

The selector 363 determines whether the initial signal C
By using LR, initial phase angle data (initial MS
ACC). The modulation speed accumulated data MSACC is supplied to a modulation waveform creation circuit 364, and step data MWAVE of the modulation waveform data is created as shown in FIGS. 365.

Further, the modulation operation RAM 331 stores the CPU 3
00, the modulation depth data MDEP of each phase is selected by the selector 358 as the modulation depth data MDEP of the phase currently being executed.
The selector 357 selects the modulation depth data MDEP of the phase to be executed next. The modulation depth data MDEP of the phase currently being executed is multiplied by the complement weighting data (1-R) by the multiplier 360 and given to the adder 361, and the modulation depth data MDEP of the phase to be executed next is given.
The EP is multiplied by the weighting data R in the multiplier 359 and provided to the adder 361, where both data are added. By the addition in the adder 361, an interpolation process is performed between the modulation depth data MDEP of the phase currently being executed and the modulation depth data MDEP of the phase to be executed next.

The interpolated modulated depth data MDEP from the adder 361 is input to the correction circuit 200b, and correction is performed according to the values of the key scale data KS and the key touch data KT. The corrected modulation depth data MDEP is multiplied by the above-mentioned multiplier 365 with the modulation waveform data MWAVE, and the modulated waveform data MDEP having an amplitude corresponding to the magnitude of the modulation depth data MDEP is multiplied.
In accordance with the sign bit data of the most significant bit of the modulation waveform data MWAVE, the data is output as it is or converted into two's complement data by the “2” complement circuit 366 and output as modulation operation data MDATA.

The above-mentioned phase speed accumulated data PSAC
The phase data PA13 and PA14 are converted by the next phase generation circuit 352 into the return signal data PNXT.
, Next phase data PNXT indicating the phase to be executed next is created, and the selector 35
0, 357. The phase data PA13 and PA14 indicating the phase currently being executed are directly supplied to the selectors 351 and 358.

The above-described phase speed accumulated data PS
The ACC weighting data PA9 to PA12 are complemented by the multiplication coefficient control circuit 355 into complement weighting data (1-R) indicating the weight of the phase currently being executed and weighting data R indicating the weight of the phase to be executed next. Created. The complement weight data (1-R) is calculated by the multiplier 35
4, 360, and the weighting data R is supplied to the multipliers 353, 359.

6. Modulation Waveform Creation Circuit 364 FIGS. 28A to 29D show specific circuits of the modulation waveform creation circuit 364, and FIGS.
The modulation waveform generation circuits 364 of (C) and (D) generate modulation waveform data MWAVE as shown in (a), (b), (c), and (d), respectively.

The modulation waveform creation circuit 364 of FIG. 19A first uses the “2” complement circuit 371 to calculate the modulation speed accumulated data M
The lower 8 bits are converted to the complement value of “2” at the second bit of the upper 2 bits of the SACC, and the complement circuit 372 of “2” is the most significant bit and the lower 9 bits are the complement value of “2”. Thus, modulated waveform data MWAVE having a triangular waveform as shown in FIG. 28A is obtained.

The modulation waveform generating circuit 364 of FIG. 28B stores modulation waveform data MWAVE of various waveforms as shown in FIG. 28B in the modulation ROM 373, and stores the modulation speed accumulation data MSACC in a read address. It is read as data.

The modulation waveform generating circuit 364 of (C) stores the modulation waveform data MWAVE of different waveforms for each of the phases (0), (1), (2) and (3).
4, 375, 376, 377 are prepared, and these modulated RO
Modulation speed accumulation data MSACC is given as read address data to M374, 375, 376, and 377.

Further, phase speed accumulated data PSA
The CC phase data PA13 and PA14 are
Each of the bits of the 4-bit select signal decoded by the modulation ROM 37 is used as a chip enable signal CE.
4, 375, 376, and 377. Thereby, for example, as shown in FIG. 28C, different modulation waveforms can be obtained for each of the phases (0) to (3).

The modulation waveform generation circuit 364 of (D) performs interpolation between the phases of the modulation waveform with respect to the modulation waveform generation circuit 364 of (C). That is, the modulation ROMs 374, 375, 376, 377
This is the same as that of FIG.
7, each modulation waveform data MWAVE read out by the modulation speed accumulated data MSACC is supplied to the selector 37.
In step 9, the next-phase data PNXT selects the modulation waveform data MWAVE of the phase to be executed next, and the selector 380 outputs the modulation waveform data MWAVE of the phase currently being executed by the phase data PA13 and PA14. Selected.

Among these, the modulated waveform data MWAVE of the phase to be executed next is multiplied by the weighting data R in the multiplier 381, and is given to the adder 383, and the modulated waveform data MWA of the phase currently being executed.
VE is output from the multiplier 382 to the complement weighted data (1
−R) is multiplied and given to the adder 383, and both data are added. As a result, as shown in FIG. 28D, interpolation is performed between the modulation waveform of the phase currently being executed and the modulation waveform of the phase to be executed next.

The above-mentioned "2"'s complement circuits 371, 37
2, 366 can be constituted by an exclusive OR gate group and an adder.

FIG. 30A shows a specific circuit of the next phase generation circuit 352 in FIG. 26, and shows the phase data PACC of the phase speed accumulated data PSACC.
The lower data PA13 of A13 and A14 is input to the lower A side (0) of the selector 391 via the NAND gate NA1, and is input to the upper A side (1) of the selector 391 via the OR gate OR1. PA1
4 is inverted by the inverter IN1 and the NAND gate NA
1 is input to the lower A side (0) of the selector 391, and the selector 391 is connected via the OR gate OR1.
Is input to the A-side high-order (1).

As a result, on the A side of the selector 391,
The data obtained by adding +1 to the phase data PA13, 14 is input, and the phase data PA13, 14 is "1".
In the case of “1”, “11” is input as it is, and FIG.
As shown in (1) of (2), when the phase of the modulation waveform reaches the final phase “11 (3)”, the next phase is also set to “11 (3)”, as shown in FIG. 1 (2) right. Thus, only the final phase is repeatedly executed.

This is because return signal data RET =
When "0", the output of the NAND gate NA2 is always "1",
This is the case where the A side of the selector 391 is always selected, but when the return signal data RET = “1”, only when the phase data PA13 and PA14 is “11”, “10 (2 ) "Is selected. As a result, as shown in (2) of FIG. 30 (2), when the modulation phase reaches the final phase “11 (3)”, the next phase is set to “10 (2)”, and FIG. )
As shown in (2), phases (2) and (3) are repeatedly executed.

FIG. 31 shows a specific circuit of the multiplication coefficient control circuit 356.
The ACC weighting data PA9 to PA12 are output as the weighting data R with “0” added to the higher order through AND gates AN2 to AN5. Also,
The inverter IN2 is connected via AND gates AN2 to AN5.
Inverted by .about.IN5, "0" is added to the high order, and +1 is added by the adder 392, so that the complement is set to "2", which is output as the complement weighting data (1-R).

7. Example of Frequency Modulation FIGS. 2A, 2B, 2C, and 2D show examples of frequency modulation, and examples of set values of respective data for realizing this modulation waveform are shown below.

(A) Trumpet sound type modulation phase (0) Initial phase angle data: 0 Modulation speed data MSPD: Large value Modulation depth data MDEP: Large value Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Phase (2) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Phase (3) Modulation speed data MSPD: Medium value Modulation depth data MDEP: Medium value Return signal data RET: 0 (B) Auto vent type Modulation phase (0) Initial phase angle data: 300 н (-90 degrees) Modulation speed data MSPD: 0 Modulation depth data MDEP: Medium value Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 phase (2) Modulation speed Data MSPD: 0 Modulated depth data MDEP: 0 Phase (3) Modulation speed data MSPD: Medium value Modulated depth data MDEP: Medium value Return signal data RET: 0 At the start of phase (0), frequency modulation is performed. In this state, it is possible to start producing musical tones.

(C) Glide type modulation phase (0) Initial phase angle data: 300 н (-90 degrees) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP : Medium value Phase (2), Phase (3) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Return signal data RET: 0 From phase (0) to phase (1), modulation speed accumulation data MSACC is: , The initial phase angle data “300 н” remain unchanged and the modulation depth data MDE
Since only P increases, the modulation level gradually increases gradually.

(D) Strings type modulation phase (0) Initial phase angle data: 0 Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 Phase (1) Modulation speed data MSPD: 0 Modulation depth data MDEP: 0 phase (2) Modulation speed data MSPD: Slightly small value Modulation depth data MDEP: Slightly large value Phase (3) Modulation speed data MSPD: Slightly large value Modulation depth data MDEP: Slightly small value Return signal data RET: 1 However, it is possible to obtain a complicated modulation waveform in which the amplitude is switched and becomes larger or smaller.

The size of the phase speed data PSPD is inversely proportional to the length of each phase shown in FIGS. 1A, 1B, 1C, and 1D. In this manner, the frequency of one musical tone can be sequentially and variously changed based on the modulation coefficient that differs for each phase.

8. FIG. 5 shows the frequency number accumulator 40. The modulation key number data and the modulation cent data from the assignment memory circuit 32 are read out to the frequency number speed ROM 419 via the latch 404. Frequency number speed data FS, which is given as address data and indicates a frequency value corresponding to the modulation key number data M KEY NO and the modulation cent data M CENT, is read.

This frequency number speed data FS is
Adder 4 through the exclusive OR gate group 405
07, the accumulated frequency number FA is accumulated to the previous frequency number FA, the upper 8 bits FA19 to 26 are passed through the selector 413, the lower 19 bits FA0 to 18 are passed through the exclusive OR gate group 414, and the latch group 415 and the selector 41
6, is again provided to the adder 407 as the frequency number accumulated value FA.

As a result, the frequency number accumulated value FA is accumulated at a speed corresponding to the magnitude of the frequency number speed data FS, and the accumulated value FA is transmitted via the latch 418 to the 15-bit FA12 to FA15 corresponding to the upper integer part. 26 is R
The data is sent to the OM address control circuit 31, and the waveform data RD is read. Upper 3 bits FA of decimal part
The waveform folded signal FDU of 9 to 11 and the most significant bit is sent to the waveform data decompression interpolation circuit 50 and used for decompression and interpolation of the sample value of the waveform data RD.

FIG. 32 shows the contents of the frequency number accumulated value FA. The frequency number accumulated value FA is 28-bit data in total, and the most significant bit is the waveform folded signal FDU. The next 8-bit FAs 19 to 26 are compare bits, which are used for comparing whether or not a loop end and a loop top described later have been reached.
Bits FA12-18 are integer part, last 12 bits F
A0 to 11 are decimal parts. Such frequency number speed data FS is accumulated by the frequency number accumulator 40 for 16 channels from CH0 to CH15, and the frequency number accumulated value FA of each channel is stored in the latch group 415.
Is stored in the memory.

The latch group 415 is composed of 16 latches. The latch for accumulating the frequency number speed data is switched at the timing of the clock signal CK3. Reading from the latch is performed in one cycle of the clock signal CK3. The writing to the latch is performed at the last timing in the latter half of the clock signal CK3. In each latch of the latch group 415, the same read address (the same frequency number accumulated value FA12 to FA26) is set for the two tone components (A) and (B). The difference in timbre is based on the difference in the bank data (A) and (B).

The 8-bit initial frequency number from the assignment memory circuit 32 is added with 1-bit “0” in the upper part and 19-bit “00... 0” in the lower part by the selector 416 via the latch 406. Then, it is selected as 28-bit data, which is the same as the frequency number accumulated value FA. The select signal in the selector 416 is
An on-event signal output at the key-on timing from the envelope generator 60 is used. As shown in FIG. 18, the frequency number speed data FS is sequentially accumulated from the key-on timing with respect to the initial frequency number.

Further, the loop end data and the loop top data from the assignment memory circuit 32 are selected via the latch 402 by the selector 403 to select one of the loop end and the loop top data. Is also given. In the comparator 409, the top eight of the frequency number accumulated value FA
When the frequency comparison value FA is compared with the bit comparison bits FA19 to 26, and the frequency number accumulated value FA exceeds the range between the loop end and the loop top, the selector 410 outputs an overrun signal FCP. The signals are supplied to the exclusive OR gate group 414 and the selector 413, and the loop end data or the loop top data is taken in as new data instead of the higher-order compare bits FA19 to 26 of the frequency number accumulated value FA.

At this time, the exclusive OR gate group 4
At 14, the values of the integer part and the decimal part of the frequency number accumulated value FA up to that point are inverted plus or minus. This is because the reading direction of the waveform data RD is inverted at the loop end or loop top. This is to use the frequency number accumulated value FA as it is in a state where the fraction of the accumulated value FA is plus / minus inverted and to provide consistency in inversion reading of the waveform data RD.

The overrun signal FCP is also applied to an exclusive OR gate 412 to invert the waveform folding signal FDU which is the most significant bit of the frequency number accumulated value FA.
The value of the frequency number speed data FS at 5 is inverted plus or minus, and the direction of accumulation of the frequency number accumulated value FA at the adder 407 is switched. FIG. 18 shows a state of loop reproduction for each half waveform by the switching of the frequency number speed data FS.

The waveform folded signal FDU is supplied to the selector 4
03 and 410 are provided as select signals. When frequency number speed data FS is added, loop end data and A <B detection signal are selected, and when subtraction, loop top data and A> B detection signal are selected. . The waveform folding signal FDU is also input to the Cin terminal of the adder 407, and when the frequency number speed data FS is subtracted, +1 processing of the frequency number accumulated value FA is performed.
Also provided to the exclusive OR gate 408.

An output signal from the Cout terminal of the adder 407 is also given to the exclusive OR gate 408, and it is detected that the frequency number accumulated value FA has overflowed or underflowed. Is output as

Further, with respect to the bank data (A) and (B) from the assignment memory circuit 32, one of the bank data (A) and (B) is selected by the selector 401 via the latch 400, and the latch 417 is selected. Is sent to the ROM address control circuit 31 together with the integer part of the frequency number accumulated value FA to read out the waveform data RD.

As a result, although the two tone components (A) and (B) assigned to one channel have different bank data, the common frequency number accumulated value FA is used, and the timing synchronization of the tone generation process is performed. Is taken.

The select signal of the selector 401 includes
Clock signal CK3 from system clock generator 10
Is used, the tone generation process for (A) is performed in the first half of the clock signal CK3, and the tone generation process for (B) is performed in the second half. The clock signal group CK from the system clock generator 10 corresponds to the latches 400, 402, 404, 406, 415, 417, 4
18 is also provided as a latch signal to synchronize the channel cycle and timing.

The present invention is not limited to the above embodiments, but can be variously modified without departing from the spirit of the present invention. For example, key scale data KSD and key touch data K
When changing the content of the frequency modulation by the TD, the modulation speed data MSPD and the modulation depth data M
Instead of multiplying the DEP and the phase speed data PSPD by the multipliers 210 and 213, arithmetic processing such as addition, subtraction, and division may be performed, or arithmetic may be performed based on an arithmetic expression.

The modulation information is set by the tone color switch 2 and the phase speed data PSPD, the modulation speed data MSPD,
Modulation depth data MDEP, modulation waveform data MWAV
E, key scale selection signal data KS, key touch selection signal data KT, initial after selection signal data I
/ A, return signal data RET, etc., may be individually set, and the shape of the modulation waveform may be a periodic shape or linear shape as described above, or may be a random shape by a random number generator. The information may change based on the envelope level or data that changes over time, or may change based on the selected rhythm, set tempo, or set volume,
In this case, each selected or set data value is sequentially modulated
An operation such as addition, subtraction, multiplication and division may be performed on each data in M331, or each selected or set data value may be corrected by the correction circuit 200a (2
00b, 200c).

Embodiments of the present invention are as follows. [1] An electronic musical instrument including a waveform generating means for generating waveform data, and a generating speed setting means for setting a generating speed of the waveform data of the waveform generating means, a pitch specifying means for specifying a pitch of a musical tone; Modulation information storage means for storing a plurality of pieces of modulation information for changing the generation speed of waveform data of the waveform generation means; and modulation information for outputting, from the modulation information storage means, modulation information corresponding to the contents specified by the pitch specification means. An electronic device comprising: an output unit; and a generation speed control unit that changes a generation speed of the waveform data set by the generation speed setting unit based on the modulation information output by the modulation information output unit. Musical instrument frequency modulation device for musical instruments.

[2] In an electronic musical instrument equipped with a waveform generating means for generating waveform data and a generating speed setting means for setting a generating speed of the waveform data of the waveform generating means, a sound emitting operation for performing a sound emitting operation of a musical sound Means, a sound emitting operation state detecting means for detecting a state of a sound emitting operation of the sound emitting operating means, a modulation information storing means for storing a plurality of modulation information for changing a generation speed of waveform data of the waveform generating means,
Modulation information output means for outputting modulation information in accordance with the detection content of the sound emitting operation state detection means from the modulation information storage means; and the generation speed setting based on the modulation information output by the modulation information output means. And a generation speed control means for changing the generation speed of the waveform data set by the means.

[3] The tone frequency modulation device for an electronic musical instrument according to [1] or [2], wherein the waveform generating means is means for generating musical tone waveform data.

[4] The modulation information output means is means for outputting a plurality of pieces of modulation information, and the generation speed control means is set by the generation speed setting means based on the plurality of output modulation information. 3. The tone frequency modulating device for an electronic musical instrument according to claim 1, wherein the tone frequency modulating device is means for sequentially changing a generation speed of the generated waveform data.

[5] The tone frequency modulating device for an electronic musical instrument according to the item 2, wherein the sound emitting operation state detecting means is a speed of a sound emitting operation of a musical sound.

[6] The tone frequency modulating device for an electronic musical instrument according to 2, wherein the sound emitting operation state detecting means is the intensity of a sound emitting operation of a musical tone.

[7] The modulation information output means performs an arithmetic processing according to the contents specified by the pitch specifying means or an arithmetic processing according to the contents detected by the sound emitting operation state detecting means. 3. The tone frequency modulation device for an electronic musical instrument according to 1 or 2, wherein

[8] The modulation information output means converts and outputs a value corresponding to the contents specified by the pitch specifying means or a value corresponding to the contents detected by the sound emitting operation state detecting means. 3. The tone frequency modulating device for an electronic musical instrument according to claim 1, wherein

[9] The modulation information output means outputs a plurality of pieces of modulation information, weights any two of the pieces of modulation information, and shifts the weighting from one to the other as time passes. 3. The tone frequency modulation device for an electronic musical instrument according to claim 1, wherein

[10] The electronic device according to [1] or [2], wherein the modulation information output means is means for sequentially outputting a plurality of pieces of modulation information and sequentially switching each piece of modulation information as time passes. Musical instrument frequency modulation device for musical instruments.

[11] The tone frequency modulation device for an electronic musical instrument according to [1] or [2], wherein the modulation information output means is means for repeatedly outputting one piece of modulation information.

[12] The tone frequency modulation device for an electronic musical instrument according to the item [1] or [2], wherein the modulation information stored in the modulation information storage means is information indicating a modulation speed.

[13] The tone frequency modulation device for an electronic musical instrument according to [1] or [2], wherein the modulation information stored in the modulation information storage means is information indicating a modulation depth.

[14] Phase information storage means for storing phase information at the start of a periodic change in the modulation speed and modulation depth, and phase information output for outputting the phase information from the phase information storage means 1 or 2 characterized by comprising a modulation start means for starting a periodic change of a modulation speed and a modulation depth with a phase corresponding to the phase information outputted by the phase information output means. 3. The tone frequency modulation device for an electronic musical instrument according to claim 1.

[15] In contrast to the tone frequency modulating device, the frequency modulation state can be further changed in accordance with the pitch or the sound emitting operation state, so that the modulation content can be changed considerably widely, and one modulation device can be used. All musical effects by frequency modulation can be realized, and the optimum modulation content for each performance can be easily obtained.

[16] A plurality of pieces of modulation information for changing the generation speed of the waveform data are stored in advance, and among the plurality of pieces of modulation information, information corresponding to a pitch or a sound emitting operation state, for example, a key pressed state is output. The generation speed of the waveform data is changed based on the output modulation information.

The waveform data includes musical sound waveform data representing the waveform of sounds in the natural world, such as instrument sounds such as piano, violin, and drums, and human voices, real-time sine synthesis, FM
It includes all waveform data that are used as sound sources, PD sound sources, and the like, such as sine waves, triangular waves, rectangular waves, and sawtooth waves.
The pitch is a broad concept including a range indicating a plurality of pitch groups.

As a result, a single modulation device can output a plurality of pieces of modulation information according to a pitch or a sound emitting operation state, and can easily and optimally perform various modulation contents according to various performance states. realizable.

[17] In a tone frequency modulating device that changes the generation speed of waveform data based on a plurality of pieces of modulation information, each performance state is changed by changing the frequency modulation state according to a pitch or a sound emitting operation state. The most suitable modulation content is realized in a wide variety of ways with a small amount of modulation data.

[0168]

As described above in detail, in the present invention, the initial phase information of the periodic change of the modulation information is generated, and the phase of the modulation information that periodically changes from the phase corresponding to the generated initial phase information. Start generating. Therefore, the initial phase of the periodic change of the frequency modulation, that is, the start phase of the frequency modulation is changed in accordance with the generated initial phase information, and the start of the frequency modulation can be variously changed.

[Brief description of the drawings]

FIG. 1 shows the contents of a modulation waveform.

FIG. 2 shows a specific example of a modulation waveform.

FIG. 3 shows an entire circuit of the electronic musical instrument.

FIG. 4 shows a key assigner circuit 30.

FIG. 5 shows a frequency number accumulator 40.

6 shows the contents stored in a ROM 20. FIG.

FIG. 7 shows an address mapping for the CPU 300 other than the RAM 20.

FIG. 8 shows the contents of timbre coefficient data.

FIG. 9 shows calculation contents of modulation information.

FIG. 10 shows a correction circuit 200a (200b, 200c).

FIG. 11 shows the contents of timbre coefficient data.

FIG. 12 shows the storage contents of modulation information.

FIG. 13 shows a correction circuit 200a (200b, 200c).

14 shows the contents of a modulation operation RAM 331. FIG.

15 shows the contents of a modulation operation RAM 331. FIG.

16 shows the contents stored in a CPU RAM 301. FIG.

17 shows the contents stored in an assignment memory 320. FIG.

FIG. 18 shows a reading state of waveform data RD.

FIG. 19 is a time chart showing a relationship between a key-on event signal ON EVENT and a key-on summing signal ON SUMM and the start of modulation control.

FIG. 20: Initial phase angle data INITIAL M
4 shows the relationship between SACC and the phase angle at the start of modulation control.

FIG. 21 shows a specific example of key number data and cent data.

FIG. 22 shows key number data KEY NO and cent data CENT, modulation operation data MDATA, key number bias data (KEY NO bias) and cent bias data (CENT bias), modulation key number data M KEY NO and modulation cent data M CEN.
The relation of T is shown.

FIG. 23 shows address data of the CPU 300 and the ROM 20.
Shows the correspondence with the address data.

24 shows a modulation operation circuit 33. FIG.

FIG. 25 shows calculation contents of a modulation calculation circuit 33.

26 shows a modulation operation circuit 33. FIG.

FIG. 27 shows the operation contents of the modulation operation circuit 33.

FIG. 28 shows an example of a modulation waveform creation circuit 364 and a modulation waveform.

FIG. 29 shows an example of a modulation waveform creation circuit 364 and a modulation waveform.

FIG. 30 shows a next phase creation circuit 352.

FIG. 31 shows a multiplication coefficient control circuit 356.

FIG. 32 shows the contents of a frequency number accumulated value FA.

[Explanation of symbols]

200a, 200b, 200c ... correction circuit, 210, 2
13 Multiplier, 211, 214 ... Function generator, 232,
236: Limiter, 33: Modulation operation circuit, 331: Modulation operation RAM, 352: Next phase generation circuit, 35
5 Multiplication coefficient control circuit, 364 Modulation waveform creation circuit, 3
66, 371, 372... Two's complement circuit, 373, 3
74, 375, 376, 377 ... Modulation ROM.

Claims (2)

[Claims] A means for generating waveform data; a means for setting a generation speed of the generated waveform data; and a means for generating modulation information for periodically changing the generation speed of the set waveform data. Means for changing the generation speed of the set waveform data based on the generated modulation information; means for generating initial phase information of the periodic change of the modulation information; and the generated initial phase. Means for starting the generation of the periodically changing modulation information from a phase corresponding to the information. 2. Generating waveform data, setting a generation speed of the generated waveform data, generating modulation information for periodically changing the generation speed of the set waveform data, Changing the generation speed of the set waveform data based on the modulation information; generating initial phase information of a periodic change of the modulation information; and generating the initial phase information from the phase corresponding to the generated initial phase information. A tone frequency modulation method characterized by starting generation of modulation information that changes to a tone frequency.