JPH10289920A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a resin sealed LSI(large-scale integration) package thin without losing reliability, in a semiconductor device containing an LOC(lead-on chip) structure. SOLUTION: An insulation tape 3 is brought into contact with only an inner lead 2 made thin and a pass bar 6, and the inner lead 2 and a semiconductor chip 4 are bonded together, with the insulation tape 3 in between. Lastly, a bonding pad 1 provided to the semiconductor chip 4 is electrically connected to the tip part of the inner lead 2 with a bonding wire 5. Thereby the package can be made thinner by the cut-off quantity of the lower surface of the inner lead 2 and the bus bar 6, with conventional thickness of an outer lead 12, loop height of the bonding wire 5, film thickness of the insulation tape 3 and thickness of a sealing resin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a LOC (Lead On Chic) for a large scale integrated circuit.
p) Resin-sealed LSI package with structure (TSO
The present invention relates to techniques effective in conformity with P).

[0002]

2. Description of the Related Art In the recent information age, the demand for information and communication equipment has been increasing year by year. Camera-type VT, for which the demand is particularly remarkable among information and communication equipment
Portable information devices such as R, PHS (Personal Handyphone System), and notebook computers tend to be smaller and thinner due to their ease of carrying. Therefore,
Of course, LSI packages mounted inside these devices also need to be reduced in size and thickness.

On the other hand, as the large-scale integration of semiconductor elements has progressed, the chip area has been gradually increasing. In a package method of die-bonding a chip to an island of a lead frame, a package having a required size is required. It is becoming difficult to house semiconductor elements in such devices.

In order to deal with this point, LOC as disclosed in Japanese Patent Application Laid-Open No. Hei 4-291950 and the like has been proposed.
A TSOP having a structure has been proposed and put into practical use.

FIG. 14 shows a TSOP having a typical LOC structure.
15 is a plan view showing a state before resin sealing, and FIG. 15 is a cross-sectional view taken along line DD ′ of FIG. 14 after resin sealing. This TSOP is assembled as follows. First, the insulating tape 3 is bonded to the inner lead portion 2 of the lead frame 10 including the inner lead 2, the outer lead 12, and the tie bar 13. Next, a bonding pad 1 is provided at the center.
The insulating tape 3 to which the lead frame 10 is adhered is adhered to a predetermined position on the surface of the semiconductor chip 4 on which is formed.
Then, the bonding pads 1 on the semiconductor chip 4 and the inner leads 2 are electrically connected by bonding wires 5. Subsequently, the entire semiconductor chip is sealed with a sealing resin 7 by a transfer molding method, and the lead frame 1 is sealed.
Then, the tie bar 13 and the base portion 14 are cut, and the lead is formed into a desired shape to complete the manufacture of the TSOP.

In the TSOP thus formed,
Compared to a package method in which the inner leads are positioned outside the semiconductor chip and wire bonding is performed, the size in the horizontal direction can be particularly reduced, so that the size can be reduced.

[0007]

With the spread of IC cards and the like, a thin and highly reliable T having a thickness of 1 mm or less will be used in the future.
It is expected that an SOP will be required. In the TSOP having the conventional LOC structure as described above, the loop of the bonding wire is reduced (the locus of the bonding wire from the surface of the semiconductor chip is kept low), the thickness of the semiconductor chip is reduced, the frame thickness is reduced, and the insulating tape is thinned. And the thickness of the sealing resin can be reduced by any of the following methods.

However, when the thickness is reduced by the above-described method, the following problems occur in the TSOP having the conventional LOC structure. That is, when the thickness of the bonding wire is reduced by reducing the loop, the wire comes into contact with the inner lead or the bus bar due to the variation in the loop height, and the possibility of forming a defective device increases.

In order to reduce the thickness of the semiconductor chip by reducing the thickness of the semiconductor chip, it is necessary to increase the amount of polishing on the back surface of the wafer in a back grinding process before cutting chips from the semiconductor wafer. However, in the future, it is inevitable that the wafer diameter will be further increased for the purpose of improving productivity, and the larger the diameter, the greater the warpage of the wafer due to the stress of various films deposited in the semiconductor circuit manufacturing process. turn into. If polishing is performed as it is, the semiconductor chip thickness will be different between the center and the periphery of the wafer.
It is necessary to forcibly flatten the back surface of the wafer by vacuum suction or the like before polishing, but this is not preferable because it leads to breakage of the wafer. In addition, it is not preferable to perform back grinding after cutting out a semiconductor chip, since this leads to extension of a manufacturing process period.

When the thickness of the frame is reduced by reducing the thickness of the frame, the strength of the lead frame material is reduced, and the frame is likely to be broken when the outer lead is processed into a desired shape or when it is incorporated into an electronic device. And the reliability decreases.

When the thickness of the insulating tape is reduced by reducing the thickness, the capacitance between the lead frame and the semiconductor chip becomes too large, or the resistance to the external stress applied to the semiconductor chip becomes small. In the worst case, there is a problem that cracks occur in the semiconductor chip, so that the electrical characteristics and reliability also deteriorate.

When the thickness of the sealing resin is reduced by reducing the thickness of the sealing resin, it is necessary to secure a region through which the bonding wires pass on the upper surface of the semiconductor chip, so that a certain thickness of the sealing resin is required. Therefore, there is a limit to thinning. Therefore, the only choice is to reduce the thickness of the sealing resin on the lower surface (back surface) of the chip. On the other hand, the warpage of the package is caused by the difference in the contraction force (rate) of the sealing resin at the boundary of the semiconductor chip,
The difference in contraction force depends on the volume ratio of the sealing resin. Therefore,
When the thickness of the sealing resin is reduced on the lower surface of the chip, there is a problem that the package is warped because the volume of the sealing resin is smaller on the lower surface than on the upper surface of the chip.

An object of the present invention is to realize a thinner resin-sealed LSI package (TSOP) without impairing reliability in a semiconductor device having a LOC structure.

Another object of the present invention is to reduce the thickness of a resin-sealed LSI package (TSOP) in a semiconductor device having a LOC structure without deteriorating reliability.

[0015]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention has an inner lead extending from an outer lead for connecting an external terminal on a circuit forming surface of a semiconductor chip. It is bonded via an insulating tape. Further, the inner leads and the bonding pads formed on the semiconductor chip are electrically connected by bonding wires, and the entire semiconductor chip is sealed with resin.

Here, the inner lead has a thin portion thinner than the outer lead, and the thin portion is in contact with the insulating tape.

Accordingly, the thickness of the package can be reduced by an amount corresponding to the reduced thickness of the tip portion of the inner lead.

In another semiconductor device of the present invention, inner leads are adhered to a circuit forming surface of a semiconductor chip via an insulating tape. Further, the inner leads and the bonding pads formed on the semiconductor chip are electrically connected by bonding wires, and the entire semiconductor chip is sealed with resin.

Here, the lower surface of the tip of the inner lead is partially cut out to form a notch, and one surface of the insulating tape is adhered to at least the notch, and the other surface is formed of the semiconductor chip. Adhered to the top surface.

In still another semiconductor device of the present invention, inner leads are adhered to a circuit forming surface of a semiconductor chip via an insulating tape. Further, the inner leads and the bonding pads formed on the semiconductor chip are electrically connected by bonding wires, and the entire semiconductor chip is sealed with resin.

Here, the lower surface of the inner lead is partially cut away to form a concave portion, and one surface of the insulating tape is bonded to at least the inner surface of the concave portion, and the other surface is bonded to the upper surface of the semiconductor chip. I have.

Here, preferably, in a bus bar supported by any two inner leads and arranged along the tips of the other inner leads, at least the thickness of the fixing portion in contact with the insulating tape is reduced by the thickness of the inner leads. It is almost equal to the thickness of the thin part, the notch, or the recess.

Here, preferably, a bonding wire is crimped on a thin portion, a notch, or an upper surface of the concave portion of the inner lead.

More preferably, the bonding wire passes above the fixed portion of the bus bar and connects the inner lead and the bonding pad.

Here, the thin portion, the cutout portion, or the concave portion of the inner lead may be offset below the side extending from the outer lead.

Preferably, a recess is formed in at least a portion of the inner lead located above the semiconductor chip.

[0027]

In the present invention, the tip of the inner lead and the lower surface of the bus bar, which are adhered to the semiconductor chip via the protective film and the insulating tape, are cut in advance to a certain thickness.
That is, in this case, the outer lead and the insulating tape, which greatly affect the reliability, the thickness of the sealing resin and the semiconductor chip itself, and the loop height of the bonding wire are not reduced, so that the reliability is not reduced. Also, the package can be made thinner only by adding a thinning process.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment will be described. First, a schematic configuration of the semiconductor device will be described. FIG. 1 is a plan view schematically showing a state of the semiconductor device before resin sealing, and FIG. 2 is an enlarged plan view of a part of the inner lead of FIG. FIG. 3A is a cross-sectional view taken along line AA ′ in FIG. 1 after resin sealing. FIG. 3B is an enlarged cross-sectional view of the vicinity of the insulating tape in FIG.

The semiconductor device of the first embodiment shown in FIG. 1 has a semiconductor chip 4 on which a semiconductor element (here, a DRAM is exemplified) is formed, and a lead frame 10 fixed to the semiconductor chip 4. It is composed of

A plurality of memory cells (memory cell regions) each having at least one transistor and a capacitor are formed in a matrix on the semiconductor chip 4, and a plurality of memory cells corresponding to the memory cells are formed around the memory cells. A peripheral circuit (peripheral circuit region) and the like are formed. On the surface of the semiconductor chip 4, a protective film 8 for protecting these circuits from α rays is formed so as to cover the memory cell region and the peripheral region. The protective film 8 has a plurality of openings 9 exposing a part of the surface of the semiconductor chip 4.
The bonding pad 1 made of a conductive material and electrically connected to a predetermined portion of the semiconductor chip 4 is formed in the opening 9 as shown in FIG.

Lead frame 1 made of 42 alloy
0, a device hole 11 is formed in a rectangular shape at a substantially central portion. In the device hole 11, the lead frame 10 includes a plurality of inner leads 2, which are formed substantially symmetrically so as to protrude into the device hole 11 from opposite ends of the peripheral portion, respectively.
And a diver 13 provided so as to cross the boundary between the inner lead 2 and the outer lead 12, and the inner leads 2 arranged at opposite ends of a peripheral portion of the device hole 11. The bus bar 6 provided along the tip of the other inner lead 2 while connecting the inner leads 2 disposed at the outermost ends, a base portion 14 for supporting the diver 13, and a fixed distance Are formed. Note that a plurality of the lead frames 10 are formed continuously so that they can be used corresponding to the plurality of semiconductor chips 4.
FIG. 1 shows one lead frame 10 corresponding to one semiconductor chip. Also, the lead frame 10
Is usually about 0.125 mm.

Then, as shown in FIG. 3A, the lower surface of the lead frame 10 is placed on the upper surface of the semiconductor chip 4 on which the protective film 8 is formed so that the bonding pad 1 faces from the portion between the bus bars 6 facing each other. The inner lead 2 and the lower surface of the bus bar 6 are aligned to a thickness of 0.0
The protective film 8 is bonded and fixed to the protective film 8 via an insulating tape 3 of about 8 mm.

Here, the tip portion of the inner lead 2 and the bus bar 6 shown as a hatched portion in FIG.
As shown in FIG. 3 (b), a portion of the inner lead 2 which is in contact with the insulating tape 3 is notched in a rectangular shape, and the inner lead 2 has a cutout portion 17 at a tip portion thereof. 12 and other parts of the inner lead 2 are formed thinner. Since the notch 17 is used as a crimping region for a bonding wire, the cutout 17 is 0.3 to 0.3 mm.
Preferably, it has a length of about 4 mm. The thickness of the notch 17 and the bus bar 6 can be reduced to the processing limit. In this embodiment, when the lead frame 10 and the semiconductor chip 4 are bonded to each other, the thickness of the corresponding portion is set to 0.07 mm in order to prevent the frame from being bent or broken. Further, the thickness of the notch 17 and the thickness of the bus bar 6 are made equal. Accordingly, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is about 0.205 mm in the conventional semiconductor device, but is 0.150 in the semiconductor device of the present embodiment.
In order to form the cutout portion 17 by about mm, the thickness is reduced by 0.055 mm corresponding to the thickness of a portion cut off from the distal end portion of the inner lead 2. Therefore,
The thickness of the package can be reduced.

Further, by a so-called wire bonding method, the upper surface of the tip portion of the inner lead 2 and the bonding pad 1 corresponding to the inner lead 2 are made of gold (A).
u).
As the bonding wire 5, a copper (Cu) wire,
You may use the covering wire which covered the insulating resin on the surface of the metal wire.

The outer leads 12, which are connected to the inner leads 2 and are separated from each other by cutting the diver 13, are provided with a power supply terminal for supplying a power supply voltage to each circuit constituting the DRAM, a data signal input terminal, It is used as a write enable terminal, a row address strobe signal terminal, a column address strobe signal terminal, a data signal output terminal, a reference voltage terminal, an empty terminal, and the like.

The sealing resin 7 is sealed in the resin sealing area 16 shown in FIG. 1 by using a mold (not shown).
The entire surface of the semiconductor chip 4 is covered with the sealing resin 7.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. FIG. 4 is a schematic process flow chart showing a method of manufacturing a semiconductor device in the present embodiment in the order of steps.

First, memory cells and their peripheral circuits are formed on a semiconductor wafer, and a plurality of semiconductor chips 4 are formed on the semiconductor wafer (step S1).

Then, after a pre-fuse test of each semiconductor chip 4 (step S2), an α-ray protective film 8 is formed on the entire surface of each semiconductor chip 4 (step S3). Subsequently, after the semiconductor wafer is heated to more firmly adhere the protective film 8 to the semiconductor wafer (step S4), a resist is applied to the entire surface of the semiconductor wafer (step S5), and normal photolithography (step S6) and different processes are performed. A plurality of openings 9 for exposing the bonding pads 1 formed on the lower semiconductor chip 4 are formed in the protective film 8 by anisotropic etching (step S7). After the resist is removed by ashing (step S8), the thickness of the semiconductor chip 4 is adjusted by back grinding (step S8).
9) After laser repair (step S10), a full wafer test is performed (step S11).

Next, dicing is performed to cut out the semiconductor chips 4 from the semiconductor wafer (step S12). At this time, the following four steps are performed in parallel with the operation in step S12. First, a notch is formed at the tip of the inner lead 2. At this time, the lower surface of the bus bar 6 is also removed by the same thickness as the cutout portion (step S13). The formation of the notch and the removal of the lower surface of the bus bar 6 may be performed by other removal methods other than the removal, such as etching, polishing,
It is preferably performed by a method such as pressing or rolling. Next, after an adhesive is applied to both surfaces of the insulating tape 3 (step S14), the inner leads 2 and the bus bars 6 are applied.
One surface of the insulating tape 3 is adhered to the lower surface of the substrate (step S15). At this time, the insulating tape 3 has a step S13
Notch 1 at the tip of inner lead 2 formed of
7 and the bus bar 6 are adhered so that only the portions where the lower surfaces are cut off are in contact with each other. Finally, the insulating tape 3 is shaped into a predetermined shape (step S16).

Subsequently, the inner leads 2 are arranged at predetermined positions on the surface of the protective film 8 formed on each of the cut semiconductor chips 4 with the insulating tape 3 interposed therebetween, and the semiconductor chips 4 and the inner leads 2 are bonded by applying pressure. (Step S1
7) By further heating, the semiconductor chip 4 and the inner leads 2 are firmly adhered and fixed (step S18). In some cases, the heating in step S18 can be omitted. Thereafter, the bonding pad 1 in the opening 9 formed in the protective film 8 and the inner lead 2 or the bus bar 6 are formed.
Are connected by a bonding wire 5 (step S1).
9) The entire surface of the semiconductor chip 4 is sealed with the sealing resin 7 by the transfer molding method (snub S20). Next, the tie bar 13 of the lead frame 10 and the base 1
4 is cut and the leads are formed into a desired shape to complete the package (step S21).

As described above, in the first embodiment, the notch 17 is formed by previously notching the lower surface of the tip portion of the inner lead 2 in a rectangular shape. Also, the inner lead 2 is cut away so as to have the same thickness as the cutout portion 17 at the distal end portion. In this state, one surface of the insulating tape 3 is adhered to the cutout portion 17 of the inner lead 2 and a portion of the lower surface of the pass bar 6 cut off, and further formed on the other surface of the insulating tape 3 and the surface of the semiconductor chip 4. The protective film 8 is bonded to the upper surface.
That is, in this case, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is equal to the thickness of the front end portion of the inner lead 2 and the portion cut from the busper 6 to form the cutout portion 17 and the cut bus bar 6. As a result, the package thickness is reduced, and the package thickness can be reduced. Also,
Since only the predetermined portions of the inner lead 2 and the bus bar 6 are thinned, the thickness of the outer lead 12 can be maintained as in the conventional case. Therefore, it is possible to prevent the frame from being broken when the outer lead 12 is processed into a desired shape or when the outer lead 12 is incorporated into an electronic device.

Therefore, according to the first embodiment, the LO
In a semiconductor device having a C structure, a TSOP having excellent reliability and a thin package can be realized without reducing the thickness of the frame, the semiconductor chip, the sealing resin, and the insulating tape and reducing the loop of the bonding wire. .

(Second Embodiment) Next, a second embodiment will be described. First, the schematic configuration of this semiconductor device is almost the same as that of the first embodiment,
The difference is that the positional relationship between the cutout portion of the inner lead 2 and the insulating tape 3 is different. FIG. 1 shows a plan view of a semiconductor device before resin sealing according to a second embodiment of the present invention. FIG. 5A is a cross-sectional view taken along line AA ′ in FIG. 1 after resin sealing. FIG. 5B is an enlarged cross-sectional view of the vicinity of the insulating tape in FIG.

The components are the same as those of the semiconductor device according to the first embodiment, and thus the same reference numerals are used. Second
In the semiconductor device according to the second embodiment, the surface structure of the semiconductor chip 4 and the configuration of the lead frame 10 are the same as those of the first embodiment, and therefore the description is omitted. The bonding portion between the inner lead 2 and the semiconductor chip 4 which is different from the first embodiment will be described below with reference to the drawings.

The semiconductor device according to the second embodiment is
As shown in FIG. 5A, the lower surface of the lead frame 10 is aligned with the upper surface of the semiconductor chip 4 on which the protective film 8 is formed so that the bonding pad 1 faces from a portion between the bus bars 6 facing each other. The distal end portion of the lead 2 and the lower surface of the bus bar 6 are bonded and fixed to the upper surface of the protective film 8 via an insulating tape 3 having a thickness of about 0.08 mm.

Here, as shown in FIG. 5 (b), the distal end of the inner lead 2 and the bus bar 6 have their lower surfaces cut out in a rectangular shape, and the inner lead 2 has a notch 18 at its distal end. The inner lead 2 is formed thinner than other portions. In this embodiment, a part of the notch 18 formed in the inner lead 2 is adhered to the insulating tape 3 so that the notch end face 2a is separated from the insulating tape end face 3a by a predetermined distance L. The second embodiment differs from the first embodiment. Due to the clearance L between the notch end face 2a and the end face 3a of the insulating tape, even if the position of the insulating tape 3 and the inner lead 2 is slightly shifted when the insulating tape 3 is bonded to the inner lead 2, the insulating tape 3 can be used. Can be prevented from being adhered to portions other than the notch portion 18.

The thickness of the notch 18 and the bus bar 6 can be reduced to the processing limit. In this embodiment, when the lead frame 10 and the semiconductor chip 4 are bonded to each other, the thickness of the corresponding portion is set to 0.07 mm in order to prevent the frame from being bent or broken. In addition, the thickness of the cutout portion 18 of the inner lead 2 and the thickness of the bus bar 6 are equal or almost equal. Accordingly, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is about 0.205 mm in the conventional semiconductor device, but is 0.150 in the semiconductor device of the present embodiment.
In order to form the notch 18, the thickness is reduced by 0.055 mm corresponding to the thickness of a portion cut off from the distal end portion of the inner lead 2. Therefore,
The thickness of the package can be reduced.

The manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method according to the first embodiment shown in FIG.

As described above, in the second embodiment, the lower surface of the distal end portion of the inner lead 2 is cut in a rectangular shape in advance to form the notch 18.
The lower surface of the pass bar 6 is also cut away so as to have the same thickness as the cutout portion 18 at the tip of the inner lead 2.

In this state, one surface of the insulating tape 3 is adhered to the cutout portion 18 of the inner lead 2 and a portion from which the lower surface of the bus bar 6 has been cut off, and the other surface of the insulating tape 3 and the semiconductor chip 4 Is adhered to the upper surface of the protective film 8 formed on the substrate. That is, in this case, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is equal to the thickness of the tip portion of the inner lead 2 and the portion cut off from the bus bar 6 to form the cutout portion 18 and the cut bus bar 6. And the thickness of the package can be reduced.

Further, one surface of the insulating tape 3 is adhered to only a part of the notch 18 of the inner lead 2, and a space is formed in the other part of the notch 18.
Even if the insulating tape 3 and the inner lead 2 are slightly misaligned when bonded, the insulating tape 3 can be prevented from being bonded to a portion other than the cutout portion 18 of the inner lead 2. In addition, since only the predetermined portions of the inner lead 2 and the pass bar 6 are thinned, the thickness of the outer lead 12 can be maintained as in the related art. Therefore, the outer lead 1
The frame can be prevented from breaking when processing the 2 into a desired shape or when assembling the package inside the electronic device.

Therefore, according to the second embodiment, the LO
In a semiconductor device having a C structure, a TSOP having excellent reliability and a thin package can be realized without reducing the thickness of the frame, the semiconductor chip, the sealing resin, and the insulating tape and reducing the loop of the bonding wire. .

(Third Embodiment) Next, a third embodiment will be described. First, the schematic configuration of this semiconductor device is almost the same as that of the first embodiment,
The difference is that the processed shape of the inner lead 2 and the processed shape of the insulating tape 3 are different. FIG. 6 is a plan view of a semiconductor device according to a third embodiment of the present invention before resin sealing, and FIG. 7A is a view taken along line BB ′ in FIG. 6 after resin sealing. It is sectional drawing. FIG. 7B is an enlarged sectional view of the vicinity of the insulating tape in FIG. 7A.

The components are the same as those of the semiconductor device according to the first embodiment, and thus the same reference numerals are used. Third
In the semiconductor device according to the second embodiment, the surface structure of the semiconductor chip 4 is the same as that of the first embodiment, and a description thereof will be omitted. The configuration of the lead frame 10 is a configuration in which the bus bar 6 is eliminated from the lead frame 10 shown in the first embodiment, and the other parts are the same as those of the first embodiment. The bonding portion between the inner lead 2 and the semiconductor chip 4 will be described below with reference to the drawings.

The semiconductor device according to the third embodiment is
As shown in FIG. 7A, the lower surface of the lead frame 10 is placed on the upper surface of the semiconductor chip 4 on which the protective film 8 is formed so that the bonding pad 1 faces from a portion between the front ends of the inner leads 2 facing each other. The alignment is performed, and the lower surface of the tip of the inner lead 2 is bonded and fixed to the protective film 8 via an insulating tape 3 having a thickness of about 0.08 mm.

Here, as shown in FIG. 7B, the lower surface of the inner lead 2 is
Are formed. Recess 19 in inner lead 2
May be within a range in which a part or the whole of the inner lead 2 is located above the semiconductor chip 4, and is freely set in accordance with the design of the package or the circuit of the semiconductor chip 4. .

Since the upper surface of the concave portion 19 is a region where the bonding wire is crimped, it is preferable that at least the concave portion 19 has a length of about 0.3 to 0.4 mm.
The thickness of the concave portion 19 can be reduced to the processing limit. In the present embodiment, when the lead frame 10 and the semiconductor chip 4 are bonded to each other, the thickness of the corresponding portion is set to 0. 0 to prevent the frame from being bent or broken.
07 mm. Thus, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is about 0.205 mm in the conventional semiconductor device, whereas the recess 19 is formed to be about 0.150 mm in the semiconductor device of the present embodiment. Therefore, the thickness of the inner lead 2 is reduced by 0.055 mm corresponding to the thickness of the portion cut off from the distal end portion. Therefore, the package thickness can be reduced.

The manufacturing method of the semiconductor device according to the third embodiment is the same as the manufacturing method according to the first embodiment shown in FIG.

As described above, in the third embodiment, the lower surface of the distal end portion of the inner lead 2 is cut out in advance to form the concave portion 19. In this state, one surface of the insulating tape 3 and the concave portions 1 of the inner leads 2 are formed.
9, the other surface of the insulating tape 3 and the upper surface of the protective film 8 formed on the semiconductor chip 4 are bonded. That is, in this case, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is reduced by the thickness of the portion cut off from the distal end portion of the inner lead 2 to form the recess 19. The thickness can be reduced.

Further, the recess 1 in which the inner lead 2 is formed
The position of 9 may be within a range in which a part or the whole of the concave portion 19 is located above the semiconductor chip 4 in the inner leads 2. Therefore, the position where the inner lead 2 and the semiconductor chip 4 are bonded can be freely set in accordance with the design of the package or the circuit of the semiconductor chip 4 or the like. In addition, since only a predetermined portion of the inner lead 2 is thinned, the frame can be prevented from being broken when the outer lead 12 is processed into a desired shape or when a package is incorporated in an electronic device.

Therefore, according to the third embodiment, the LO
In a semiconductor device having a C structure, a TSOP having excellent reliability and a thin package can be realized without reducing the thickness of the frame, the semiconductor chip, the sealing resin, and the insulating tape and reducing the loop of the bonding wire. .

(Fourth Embodiment) Next, a fourth embodiment will be described. First, the schematic configuration of this semiconductor device is almost the same as that of the first embodiment,
The difference is that the processed shape of the inner lead 2 is different. FIG. 8 is a plan view showing a semiconductor device according to a fourth embodiment of the present invention before resin sealing, and FIG. 9A is a sectional view taken along line CC ′ in FIG. 8 after resin sealing. It is sectional drawing. FIG.
FIG. 9B is an enlarged cross-sectional view of the vicinity of the insulating tape in FIG. Note that constituent members are the same as those of the semiconductor device of the first embodiment, and thus the same reference numerals are used.
In the semiconductor device according to the fourth embodiment, the surface structure of the semiconductor chip 4 and the configuration of the lead frame 10 are the same as those of the first embodiment, and therefore the description is omitted. First
The bonding portion between the inner lead 2 and the semiconductor chip 4 which is different from the above embodiment will be described below with reference to the drawings.

The semiconductor device according to the fourth embodiment is
As shown in FIG. 9A, the lower surface of the lead frame 2 is aligned with the upper surface of the semiconductor chip 4 on which the protective film 8 is formed so that the bonding pad 1 faces from a portion between the opposing pass bars 6. The distal end portion of the lead 2 and the lower surface of the bus bar 6 are bonded and fixed to the upper surface of the protective film 8 via an insulating tape 3 having a thickness of about 0.08 mm.

Here, as shown in FIG. 9B, the tip portion of the inner lead 2 and the bus bar 6 are offset downward with respect to the lead frame 10, and the portion in contact with the insulating tape 3 is The lower surface is shaved so as to be thinner than other portions of the outer lead 12 and the inner lead 2. The thickness of the cut end portion of the inner lead 2 and the thickness of the bus bar 6 can be reduced to the processing limit. In this embodiment, when the lead frame 10 and the semiconductor chip 4 are bonded to each other, the thickness of the corresponding portion is set to 0.07 mm in order to prevent the frame from being bent or broken. The tip of the inner lead 2 and the thickness of the bus bar 6 are equal or almost equal. Accordingly, when the thickness of the lead is about 0.125 mm as in the normal case, the height from the top surface of the protective film 8 to the top surface of the inner lead 2 offset from the top surface of the conventional semiconductor device is about 0.205 mm. In comparison, in the semiconductor device of the present embodiment, 0.150 mm
In this case, the thickness is reduced by 0.055 mm, which is the thickness obtained by shaving the lower surface of the distal end portion of the inner lead 2, and the package thickness is reduced.

Further, the upper surface of the offset end portion of each inner lead 2 and the corresponding bonding pad 1 are connected by a bonding wire 5 made of gold (Au) by a so-called wire bonding method. As the bossing wire 5, copper (C
u) A wire or a coated wire in which the surface of a metal wire is coated with an insulating resin may be used.

In FIGS. 9A and 9B, all of the offset and thinned portions of the inner leads 2 are bonded to the insulating tape 3. Lead 2 length is at least 0.3
If the thickness is about 0.4 mm, it can function as a crimping area for the bonding wire.
As shown in (1), it is also possible to arrange the inner lead 2 so that only a part of the offset thinned portion is adhered to the insulating tape 3.

Next, a method of manufacturing a semiconductor device according to the fourth embodiment will be described. FIG. 11 is a schematic process flow chart showing a method of manufacturing a semiconductor device in the present embodiment in the order of steps.

First, memory cells and their peripheral circuits are formed on a semiconductor wafer, and a plurality of semiconductor chips 4 are formed on the semiconductor wafer (step S31).

Then, after a pre-fuse test of each semiconductor chip 3 (step S32), an α-ray protective film 8 is formed on the entire surface of each semiconductor chip 4 (step S33).
Subsequently, the semiconductor wafer is heated in order to more firmly adhere the protective film 8 to the semiconductor wafer (Step S34).
A resist is applied to the entire surface of the semiconductor wafer (Step S3
5), normal photolithography (step S36)
A plurality of openings 9 for exposing the bonding pads 1 of the lower semiconductor chip are formed in the protective film 8 by anisotropic etching (step S37). After the resist is removed by ashing (step S38), the thickness of the semiconductor chip is adjusted by back grinding (step S39), and a full wafer test is performed via laser repair (step S40) (step S41).

Next, dicing is performed to cut out the semiconductor chips 4 from the semiconductor wafer (step S42). At this time, the following five steps are performed in parallel with the operation of step S42. First, the inner lead 2 of the lead frame 10
Is offset downward by a press or the like (step S43). In this case, it is preferable that the offset amount be equal to the loop height of the bonding wire 5. Next, the tip of the offset inner lead 2 and the lower surface of the bus bar 6 are shaved and thinned (step S44). The removal may be performed by a removal method other than the thin processing removal, and is preferably performed by a method such as etching, polishing, pressing, or rolling. next,
After applying the adhesive on both sides of the insulating tape 3 (step S
45), the insulating tape 3 is bonded to the inner lead 2 and the bus bar 6 (Step S46). At this time, the insulating tape 3 is adhered so as to be in contact only with the tip of the inner lead 2 and the offset portion of the bus bar 6. Finally, the insulating tape 3 is shaped into a predetermined shape (Step S47).

Subsequently, the inner leads 2 are placed on the surface of the protection film 8 of each of the cut semiconductor chips 4 via the insulating tape 3.
The semiconductor chip 4 and the inner lead 2 are bonded by applying pressure (step S48), and the semiconductor chip 4 and the inner lead 2 are firmly bonded and fixed by further heating (step S49). In some cases, the heating in step S49 can be omitted. After a while
Bonding pad 1 in opening 9 formed in protective film 8
Then, the inner lead 2 or the bus bar 6 is connected with the bonding wire 5 (Step S50), and the entire surface of the semiconductor chip 4 is sealed with the sealing resin 7 by the transfer molding method (Step S51). Next, lead frame 1
Then, the tie bar 13 and the base portion 14 are cut, and the leads are formed into a desired shape to complete the package (step S52).

As described above, in the fourth embodiment, after the front end of the inner lead 2 and the bus bar 6 are offset in advance, the lower surface of the offset portion is scraped and thinned, and the inner lead is thinned. The insulating tape 3 is brought into contact only with the offset portion of the bus bar 6 and the semiconductor chip 4 and the inner lead 2 are bonded via the insulating tape 3. That is, in this case, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is reduced by the thickness of the shaved end portion of the inner lead 2 and the lower surface of the pass bar 6, thereby reducing the thickness of the package. Is achieved. In addition, since only the predetermined portions of the inner lead 2 and the bus par 6 are thinned, the thickness of the outer lead 12 can be maintained as in the related art. Therefore, the outer lead 1
The frame can be prevented from breaking when processing the 2 into a desired shape or when assembling the package inside the electronic device.

Therefore, according to the fourth embodiment, the LO
In a semiconductor device having a C structure, a TSOP having excellent reliability and a thin package can be realized without reducing the thickness of the frame, the semiconductor chip, the sealing resin, and the insulating tape and reducing the loop of the bonding wire. .

(Fifth Embodiment) Next, a fifth embodiment will be described. First, although the schematic configuration of this semiconductor device is almost the same as that of the fourth embodiment,
The difference is that the positional relationship between the thinned portion of the inner lead 2 and the insulating tape 3 is different. FIG. 8 is a plan view of a semiconductor device before resin sealing according to a sixth embodiment of the present invention.
Since it is completely the same as that of FIG. FIG. 12A is a cross-sectional view taken along line CC ′ in FIG. 8 after resin sealing. FIG. 12B is an enlarged cross-sectional view of the vicinity of the insulating tape in FIG.

The components are the same as those of the semiconductor device according to the fourth embodiment, and the same reference numerals are used. Fifth
In the semiconductor device according to the present embodiment, the surface structure of the semiconductor chip 4 and the configuration of the lead frame 10 are the same as those of the fourth embodiment, and therefore the description is omitted. The bonding portion between the inner lead 2 and the semiconductor chip 4 different from the fourth embodiment will be described below with reference to the drawings.

The semiconductor device according to the fifth embodiment is
As shown in FIG. 12A, the lead frame 10 is formed on the upper surface of the semiconductor chip 4 on which the protective film 8 is formed so that the bonding pad 1 faces from a portion between the bus bars 6 facing each other.
Of the inner lead 2 and the lower surface of the bus bar 6 are adhered and fixed to the upper surface of the protective film 8 via an insulating tape 3 having a thickness of about 0.08 mm.

Here, as shown in FIG. 12B, the tip portion of the inner lead 2 and the bus bar 6 are offset downward with respect to the lead frame 10, and the portion that contacts the insulating tape 3 is Notch 20 on lower surface
Are formed. The notch 20 and the bus bar 6
Can be reduced to the processing limit.
In this embodiment, when the lead frame 10 and the semiconductor chip 4 are bonded to each other, the thickness of the corresponding portion is set to 0.07 in order to prevent the frame from being bent or broken.
mm. Further, the thickness of the cutout portion 20 of the inner lead 2 and the thickness of the bus bar 6 are equal or almost equal.

Accordingly, when the thickness of the lead is about 0.125 mm as in the normal case, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 offset is about 0.205 mm in the conventional semiconductor device. On the other hand, in the semiconductor device of the present embodiment, the inner lead 2
Is cut off by 0.055 mm, which is the thickness, so that the package can be made thinner.

The method of manufacturing the semiconductor device according to the fifth embodiment is the same as the method of manufacturing the semiconductor device according to the fourth embodiment shown in FIG.

As described above, in the fifth embodiment, the notch 20 is formed at the tip of the offset portion after offsetting the tip of the inner lead 2 and the bus bar 6 in advance. One surface of the insulating tape 3 is adhered only to the cutout portion 20 of the inner lead 2 and the portion where the lower surface of the bus bar 6 is cut off, and the other surface of the insulating tape 3 and the protective film 8 formed on the semiconductor chip 4 are bonded. Adhere to the top surface of That is, in this case, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is the thickness obtained by shaving the lower end portion of the inner bar 2 and the lower surface of the bus bar 6 to form the cutout portion 20 and the cut-off bar 6. As a result, the package thickness can be reduced.

Further, since only the predetermined portions of the inner lead 2 and the bus bar 6 are thinned, the thickness of the outer lead 12 can be maintained as in the conventional case. Therefore, it is possible to prevent the frame from being broken when the outer lead 12 is processed into a desired shape or when the package is incorporated into the electronic device.

Therefore, according to the fifth embodiment, the LO
In a semiconductor device having a C structure, a TSOP having excellent reliability and a thin package can be realized without reducing the thickness of the frame, the semiconductor chip, the sealing resin, and the insulating tape and reducing the loop of the bonding wire. .

(Sixth Embodiment) Next, a sixth embodiment will be described. First, the schematic configuration of this semiconductor device is almost the same as that of the third embodiment,
The difference is that the processed shape of the inner lead 2 is different. The plan view of the semiconductor device before resin sealing according to the sixth embodiment of the present invention is exactly the same as that of FIG. FIG. 13A shows BB ′ in FIG. 6 after resin sealing.
It is sectional drawing in a line. Further, FIG.
It is sectional drawing which expanded the insulating tape vicinity in (a).

Note that the constituent members are the same as those of the semiconductor device of the third embodiment, and thus the same reference numerals are used. Sixth
In the semiconductor device according to the second embodiment, the surface structure of the semiconductor chip 4 and the configuration of the lead frame 10 are the same as those of the first embodiment, and therefore the description is omitted. The bonding portion between the inner lead 2 and the semiconductor chip 4 different from the fourth embodiment will be described below with reference to the drawings.

The semiconductor device according to the sixth embodiment is
As shown in FIG.
The lower surface of the lead frame 10 is aligned with the upper surface of the semiconductor chip 4 on which the protective film 8 is formed so that the bonding pad 1 faces from a portion between the front ends of the inner leads 2. Insulation tape 3 of about 08mm
Is bonded and fixed to the protective film 8.

Here, as shown in FIG. 12B, the tip of the inner lead 2 is offset downward with respect to the lead frame 10, and the lower part of the part which comes into contact with the insulating tape 3 is cut off. A recess 21 is formed by being chipped. The position of the recess 21 in the inner lead 2 only needs to be within a range in which a part or all of the recess 21 is located above the semiconductor chip 4 in the inner lead 2.
It is set freely according to the design of the package or the circuit of the semiconductor chip 4.

Since the upper surface of the concave portion 21 is a region where the bonding wire is crimped, it is preferable that at least the concave portion 21 has a length of about 0.3 to 0.4 mm.
The thickness of the recess 21 can be reduced to the processing limit. In this embodiment, when the lead frame 10 and the semiconductor chip 4 are bonded to each other, the thickness of the corresponding portion is set to 0.07 mm in order to prevent the frame from being bent or broken. Thus, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is about 0.205 mm in the conventional semiconductor device, whereas the recess 21 is formed to be about 0.150 mm in the semiconductor device of the present embodiment. Therefore, the thickness of the inner lead 2 is reduced by 0.055 mm corresponding to the thickness of the portion cut off from the distal end portion. Therefore, the package thickness can be reduced.

The manufacturing method of the semiconductor device according to the sixth embodiment is the same as the manufacturing method according to the fourth embodiment shown in FIG.

As described above, in the sixth embodiment, after the tip of the inner lead 2 is offset in advance, the recess 21 is formed on the lower surface of the tip of the offset portion.
Is formed. In this state, the concave portions 21 of the inner leads 2 are bonded to one surface of the insulating tape 3, and the other surface of the insulating tape 3 is bonded to the semiconductor chip 4. That is, in this case, the height from the upper surface of the protective film 8 to the upper surface of the inner lead 2 is reduced by the thickness of the portion cut off from the distal end portion of the inner lead 2 to form the recess 21. The thickness can be reduced.

Further, the position of the concave portion 21 formed in the inner lead 2 may be within a range where a part or the whole of the concave portion 21 is located above the semiconductor chip 4 in the inner lead 2. Therefore, the position where the inner lead 2 and the semiconductor chip 4 are bonded can be freely set in accordance with the design of the package or the circuit of the semiconductor chip 4 or the like. In addition, since only a predetermined portion of the inner lead 2 is thinned, the frame can be prevented from being broken when the outer lead 12 is processed into a desired shape or when the package is incorporated in the electronic device.

Therefore, according to the sixth embodiment, the LO
In a semiconductor device having a C structure, a TSOP having excellent reliability and a thin package can be realized without reducing the thickness of the frame, the semiconductor chip, the sealing resin, and the insulating tape and reducing the loop of the bonding wire. .

[0094]

As described above, according to the present invention,
In the semiconductor device having the LOC structure, the thickness of the tip of the inner lead is thinned in advance, regardless of the thinning of the frame, the semiconductor chip, the sealing resin, and the insulating tape and the low loop of the bonding wire. A TSOP with excellent reliability and a thin package can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a resin-sealed semiconductor device according to first and second embodiments of the present invention before resin sealing.

FIG. 2 is a view of the semiconductor device according to the first embodiment of the present invention;
It is the schematic plan view which expanded a part of inner inner lead and bus bar.

FIG. 3 is a view of the semiconductor device according to the first embodiment of the present invention;
It is a schematic sectional drawing after resin sealing in the AA 'line in a middle.

FIG. 4 is a schematic process flowchart showing a manufacturing process of the resin-encapsulated semiconductor device according to the first, second, and third embodiments of the present invention in the order of processes.

FIG. 5 shows a semiconductor device according to a second embodiment of the present invention;
It is a schematic sectional drawing after resin sealing in the AA 'line in a middle.

FIG. 6 is a schematic plan view of a resin-sealed semiconductor device according to a third or sixth embodiment of the present invention before resin sealing.

FIG. 7 is a view showing a semiconductor device according to a third embodiment of the present invention;
It is a schematic sectional drawing after resin sealing in BB 'line in a middle.

FIG. 8 is a schematic plan view of a resin-sealed semiconductor device according to a fourth or fifth embodiment of the present invention before resin sealing.

FIG. 9 is a view showing a semiconductor device according to a fourth embodiment of the present invention;
It is a schematic sectional drawing after resin sealing in CC 'line in a middle.

FIG. 10 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention after resin sealing along line CC ′ in FIG. 8;

FIG. 11 is a schematic process flowchart showing a manufacturing process of a resin-encapsulated semiconductor device according to fourth, fifth, and sixth embodiments of the present invention in the order of processes.

FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention after resin sealing along line CC ′ in FIG. 8;

FIG. 13 is a schematic cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention after resin sealing along line BB ′ in FIG. 6;

FIG. 14 is a schematic plan view of a conventional semiconductor device before resin sealing.

FIG. 15 is a schematic sectional view of a conventional semiconductor device taken along line DD ′ in FIG. 14;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bonding pad 2 Inner lead 3 Insulating tape 4 Semiconductor chip 5 Bonding wire 6 Bus bar 7 Sealing resin 8 Protective film 9 Opening 10 Lead frame 11 Device hole 12 Outer lead 13 Diver 14 Base part 15 Sprocket hole 16 Resin sealing area 17 , 18, 20 Notch 19, 21 Recess

Claims (14)

[Claims] An inner lead extending from an outer lead for connecting an external terminal is bonded to a circuit forming surface of a semiconductor chip via an insulating tape, and is formed on the inner lead and the semiconductor chip. A resin-encapsulated semiconductor device in which a bonding pad is electrically connected to a bonding wire and the entire semiconductor chip is sealed with a resin, wherein the inner lead has a thin portion thinner than the outer lead. And a semiconductor device contacting the insulating tape at the thin portion. 2. The semiconductor device according to claim 1, wherein a tip of said inner lead is offset downward from a side connected to said outer lead. 3. The inner lead comprises a plurality of inner leads, and has a bus bar supported by any two inner leads and arranged along the tip of another inner lead. The semiconductor device according to claim 1, wherein a thickness of the fixed portion in contact with the tape is equal to a thickness of the thin portion. 4. The semiconductor device according to claim 1, wherein a portion to which said bonding wire is pressed is formed on an upper surface of said thin portion. 5. The semiconductor device according to claim 3, wherein said inner lead and said bonding pad are connected by said bonding wire passing above said fixed portion of said bus bar. 6. An inner lead is adhered to a circuit forming surface of a semiconductor chip via an insulating tape, and the inner lead and a bonding pad formed on the semiconductor chip are electrically connected by a bonding wire.
A resin-sealed semiconductor device in which the entire semiconductor chip is sealed with a resin, wherein a cutout portion is formed by partially removing a lower surface of a tip portion of the inner lead, and one surface of the insulating tape. Is bonded to at least the notch, and the other surface is bonded to the upper surface of the semiconductor chip. 7. The semiconductor device according to claim 6, wherein a portion of the inner lead where the notch is formed is offset downward from a side extending from the outer lead. 8. The inner lead comprises a plurality of inner leads, and has a bus bar supported by any two inner leads and arranged along the tip of another inner lead, wherein at least the insulating portion of the bus bar is provided. 8. The semiconductor device according to claim 6, wherein a thickness of the fixing portion in contact with the tape is equal to a thickness of the notched portion of the inner lead. 9. 9. The inner lead according to claim 6, wherein a portion to which the bonding wire is crimped is formed on an upper surface of a portion where the notch portion is formed. 3. The semiconductor device according to claim 1. 10. The semiconductor device according to claim 8, wherein said inner lead and said bonding pad are connected by said bonding wire passing above said fixed portion of said bus bar. 11. The semiconductor device according to claim 1, wherein an inner lead is bonded to a circuit forming surface of the semiconductor chip via an insulating tape, and the inner lead is electrically connected to a bonding pad formed on the semiconductor chip by a bonding wire. A resin-sealed semiconductor device in which the entire chip is sealed with a resin, wherein a lower surface of the inner lead is partially cut away to form a concave portion, and one surface of the insulating tape is at least on an inner surface of the concave portion. A semiconductor device, wherein the semiconductor device is bonded and the other surface is bonded to an upper surface of the semiconductor chip. 12. The semiconductor device according to claim 11, wherein a portion of the inner lead where the recess is formed is offset downward from a side extending from the outer lead. 13. The recess according to claim 11, wherein the recess is formed in at least a portion of the inner lead located above the semiconductor chip.
3. The semiconductor device according to claim 1. 14. The semiconductor device according to claim 11, wherein a portion to which the bonding wire is pressed is formed on an upper surface of the inner lead in which the concave portion is formed.