KR100561549B1 - Pad on chip type semiconductor package - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor package, and more specifically, in a chip on pad (COP) type semiconductor package, a long loop bonding wire contacts and contacts a top surface of a semiconductor chip. And a die pad having a window corresponding to the center pads, and a bonding wire electrically connected to the center pad and the leads of the leads through the window. Disclosed is a structure of a pad-on-chip (POC) -type semiconductor package, characterized in that the die pad is down set lower than the bonding portion of the leads and the die pad is up (Up) A structure in which an insulating material is attached along the upper edge of the die pad in a set) state is provided, through which the long loop bonding wire is formed. It is possible to prevent defects such as short-circuit contact with the upper surface of the chip and also to perform the wire bonding process without using the latest wire bonding equipment that can secure the horizontal distance of the bonding wire loop. Can increase.

Pad on chip (POC), Bonding wire, Center pad, Window, Insulating material

Description

Pad on chip type semiconductor package

1 is a cross-sectional view showing a conventional lead-on-chip semiconductor package,

2 is a cross-sectional view showing a conventional chip on pad semiconductor package;

3 is a cross-sectional view illustrating a pad-on-chip semiconductor package according to an embodiment of the present invention;

4A and 4B are plan views showing examples of lead frames used in FIG. 3, respectively;

5A and 5B are plan views each showing an example of a lead frame according to another embodiment of the present invention;

6 is a cross-sectional view illustrating a pad on chip semiconductor package according to still another embodiment of the present invention.

Description of the main parts of the drawing

10, 110, 210, 310, 410: semiconductor chip

12, 112, 212, 312, 412: Center Pad

22, 122, 222, 322, 422: lead

30, 130, 230, 330, 430: adhesive tape

40, 140, 240, 440: bonding wire

50, 150, 250, 450: molding resin

100, 200, 300, 400: semiconductor package

120, 220, 320, 420: lead frame

124, 224, 324, 424: die pad

226, 326, 426: bonding unit 228, 328, 428: window

360: recognition unit 432: insulating material

A: height of bonding wire loop

B: horizontal distance of bonding wire loop

C: depth between lead and die pad

The present invention relates to a structure of a semiconductor package, and more particularly, a die pad having a window formed on an active surface provided with center pads of a semiconductor chip is bonded, and a bonding wire is attached to each center through a window of the die pad. The present invention relates to a pad on chip (POC) type semiconductor package characterized by electrically connecting pads and leads.

The structure of the semiconductor package has been developed using a variety of forms and techniques, starting with a typical semiconductor package using a lead frame having a die pad and leads, among which the lead-on chip structure has become widespread. The lead-on-chip structure is characterized by bonding leads having extended lengths over the active surface of the semiconductor chip instead of the conventional die pads. This structure enables a smaller and more reliable product than a conventional semiconductor package. .

However, such a lead-on chip structure has a result of limiting the size of the semiconductor chip to a certain limit or more applied due to the nature of the structure that the leads are bonded to the semiconductor chip. That is, the size of the semiconductor chip is limited so that the size of the semiconductor chip can not be smaller than a certain range because the leads that maintain a relatively rigid size should be arranged over the semiconductor chip compared to the trend that the semiconductor chip is light and short.

In order to overcome this drawback of the lead-on chip structure, a chip-on-pad type structure having a long loop bonding wire has been proposed as a method for reducing the size of a semiconductor chip.

1 and 2 illustrate cross-sectional views of a conventional lead-on-chip semiconductor package 100 and a chip-on-pad semiconductor package 200 having a long loop bonding wire, respectively. This will be described with reference to FIGS. 1 and 2 as follows.

As shown in FIG. 1, the conventional lead-on chip type package 100 is bonded with each lead 22 after the leads 22 are bonded through the adhesive tape 30 onto the active surface of the semiconductor chip 10. Pad 12 is connected to the bonding wire 40, it is characterized in that the molding of the molding resin (50).

The chip-on-pad semiconductor package 200 having the long loop bonding wire of FIG. 2 is designed to remove the limitation that the leads must be arranged over the active surface of the semiconductor chip 110. ) Is spaced apart from the semiconductor chip 110, and then each lead and the bonding pad 112 are electrically connected to each other by the bonding wire 140.

In this case, the bonding wire 140 may be a long loop bonding wire having a longer length than the conventional structure, and the semiconductor chip 110 may include a die formed at the center of the leads 122. Adhered on the pad 124, it is characterized in that the molding of this structure with a molding resin (150).

Such a chip-on-pad structure is characterized in that a smaller semiconductor chip can be applied than the lead-on-chip structure. For this purpose, it is necessary to satisfy the process conditions as the length of the bonding wire becomes longer.

Unlike the conventional wire bonding process, in order to form a long loop bonding wire, the horizontal distance (B) of the bonding wire loop is added to the height (A) of the bonding wire loop and the depth (C) between the die pad and the lead. Should be added.

Conventional wire bonding process is carried out by vertically pulling the ball-bonding bonding wire to a certain height (A) to wedge bonding at the bonding portion of the lead, but in the case of using a long loop bonding wire Since the distance between the center pad and the lead is large, it is necessary to secure the horizontal distance B in forming the loop of the bonding wire.

More specifically, in the chip-on-pad type structure having the long loop bonding wire, if the horizontal distance B of the bonding wire loop is not sufficiently secured, the wire may be shorted by contacting the upper edge of the semiconductor chip. It may bring a bad.

One method of preventing contact between the semiconductor chip and the bonding wire is to provide a down set to the die pad to sufficiently secure the depth C between the lead portion and the die pad. In the molding process, when molding resin such as epoxy molding compound (EMC) is supplied, it may cause inferior molding due to deterioration of fluidity and may increase the thickness of the package. have.

In addition, the wire bonding equipment applicable to the pad-on-chip (POC) type products such as the so-called "16M Conventional type" method has been used with some of the latest expensive equipment to secure the horizontal distance of the bonding wire loop. It is limited, it is not possible to utilize the existing equipment applied to the lead-on-chip type products, so-called "fourth generation (16M LOC type)", and even the latest equipment has a disadvantage that the production efficiency is reduced by the loop control.

division Maximum length of bonding wire Work time per bonding wire Number of bonding wires Unit workload Workload per day 4th generation (LOC) 1.5 mm 0.16sec / wire 52 433 9252.6 5th generation (Con'l) 3.1 mm 0.22sec / wire 53 316 6754.5

As shown in Table 1, the production efficiency is reduced by about 27% due to the decrease in wire bonding speed in the fifth generation products-for example, the daily workload of the fifth generation products based on the daily workload of the fourth generation products. Can be calculated to about 63%. -Can be seen.

In addition, in order to maintain the above production efficiency, because the process conditions applied to the equipment must be maintained within a precise range, management difficulties may occur such as an increase in the initial setting time of the equipment.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package having a pad on chip structure capable of preventing poor contact between a long loop bonding wire and a semiconductor chip.

Another object of the present invention is to utilize the existing bonding wire equipment difficult to secure the horizontal distance of the bonding wire loop.

In order to achieve the above object, the present invention is a semiconductor chip having an active surface provided with a plurality of center pads; A die pad in the form of a flat plate having windows corresponding to the center pads, the die pad being bonded onto the active surface; Leads spaced apart from the die pad and including bonding portions arranged around the die pad; Bonding wires electrically connected to the bonding portions of the respective center pads and corresponding leads through a window, the loops being formed; And a molding resin encapsulating a region including a semiconductor chip, a die pad, bonding wires, and a bonding portion of the leads, wherein the die pad is not formed higher than the bonding portion of the leads so that the bonding wire does not contact the die pad. A pad-on-chip semiconductor package is provided.

In the die pad of the pad-on-chip semiconductor package according to the present invention, at least two recognition parts may be formed to form alignment criteria of the center pads and the leads in the wire bonding process, and the recognition parts are formed by deforming the planar shape of the window. It is characterized by.

In addition, the present invention is a semiconductor chip having an active surface provided with a plurality of center pads; A die pad in the form of a flat plate having windows corresponding to the center pads, wherein an insulating material is attached along the upper edge of the flat plate, and the bottom surface of the flat plate is bonded onto the active surface; Leads spaced apart from the die pad and including bonding portions arranged around the die pad; Bonding wires electrically connected to the bonding portions of the respective center pads and corresponding leads through a window, the loops being formed; And a molding resin encapsulating a region including a semiconductor chip, a die pad, and bonding portions of the bonding wires and leads, wherein the bonding wire is not directly in contact with the die pad through an insulating material. It further provides an on-chip semiconductor package.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a pad-on-chip semiconductor package 300 according to an embodiment of the present invention, and FIGS. 4A and 4B are plan views illustrating examples of a lead frame used in FIG. 3, respectively. Referring to Figures 3 to 4b an embodiment according to the present invention will be described.

The pad on chip type semiconductor package 300 according to the present invention has a die pad 224 and leads 222 like a conventional chip on pad type semiconductor package (200 of FIG. 2). A long frame bonding wire 240 is used, and a long loop bonding wire 240 is used.

The semiconductor chip 210 is adhered to a lower surface of the die pad 224, and a window 228 is formed at the center of the die pad corresponding to the center pads 212 of the semiconductor chip 210. An adhesive tape 230 is formed along both bottom surfaces of the window 228 of the die pad, and the active surface of the semiconductor chip with the center pads 212 is adhered to the die pad through the adhesive tape, and the die pad 224 is formed. ) Is set down to be positioned below the bonding portion 226 of the leads 222 to sufficiently secure the depth C ′ between the leads and the die pad.

Finally, the bonding wire 240 is formed by the molding resin 250 to electrically connect the bonding portion of the center pad and the leads through the window 228 of the die pad to form a long loop bonding wire. The pad-on-chip (POC) semiconductor package 300 having is completed.

According to the present invention, since the bonding portions of the leads are formed at the same position as or higher than the die pads, defects such as contact with the die pads do not occur even when the bonding wires do not secure a horizontal distance (B in FIG. 2). In the conventional chip-on-pad type semiconductor package, in order to obtain the same effect as the present invention, there is a difficulty that the die pad should be set further downward by the thickness of the semiconductor chip.

In addition, according to the present invention, since the semiconductor chip can be used regardless of the size of the die pad, it can be freely configured. That is, as shown in FIG. 4A, a larger size of the die pad 224 than the semiconductor chip 210 is used, or as shown in FIG. 4B, a smaller size of the die pad 224 ′ than the semiconductor chip 210 is shown. Can be used.

In addition, as the die pad is bonded onto the active surface of the semiconductor chip, a problem may occur that it is difficult to set a criterion for the initial setting operation in the wire bonding equipment.

In the prior art, the setting operation was performed based on a specific region of the semiconductor chip. However, in the structure according to the present invention, since the die pad covers most of the semiconductor chip, it is difficult to perform the setting operation based on the semiconductor chip. .

Thus, as an example to compensate for this, as shown in FIGS. 5A and 5B, a part of the window of the die pad is formed in a specific shape to form a recognition unit that can be a reference for setting work.

In more detail, in the lead frame 320 having the die pad 324 and the leads 322 arranged around the die pad, a window is formed in a circular shape at both ends or protruded at both ends. By forming 328 and 328 ', recognition units 360 and 360' that can be used as a reference for setting work are formed.

In addition, if the depth at which the die pad is set down is too large, when the molding resin such as epoxy molding compound (EMC) is supplied in a subsequent molding process, fluidity may be degraded, resulting in incomplete molding, and the thickness of the package may increase. Difficult to apply because it can be a factor. Another embodiment of the present invention for preventing this will be described a structure in which the die pad is upset to be formed above the bonding portion of the leads.

6 is a cross-sectional view illustrating a pad on chip type semiconductor package 400 according to another exemplary embodiment of the present invention. This will be described with reference to FIG. 6.

The pad on chip type semiconductor package 400 according to the present invention uses a lead frame 420 composed of a die pad 424 and leads 422, and a long loop bonding wire 440. loop bonding wire).

The semiconductor chip 410 is bonded to the lower surface of the die pad 424, and a window 428 is formed at the center of the die pad to correspond to the center pads 412 of the semiconductor chip 410. An adhesive tape 430 is formed along both lower surfaces of the window 428 of the die pad, and the active surface of the semiconductor chip with the center pads 412 is adhered to the die pad through the adhesive tape 430. The 424 is upset to be positioned above the bonding portion 426 of the leads 422 by a predetermined depth C ″.

The bonding wire 440 is ball bonded on the center pad 412 and then raised to a constant height A ″ and guided to the bonding portion 426 of the leads 422 to be wedge bonded. .

In this case, an insulating material 432 is formed along the upper surface of the outer surface of the die pad 424 so that the bonding wire 440 does not contact the outer surface of the die pad 424. As the insulating material 432, an insulating tape used to bond the die pad 424 and the semiconductor chip 410 may be used.

Finally, the bonding wire 440 electrically connects the center pad and the bonding portion of the leads through the window 428 of the die pad to form a molding resin 450 to form a long loop bonding wire. The pad-on-chip (POC) type semiconductor package 400 having is completed.

In the structure as described above, even if the die pad is formed higher than the bonding portion of the leads, since the insulating material is interposed between the bonding wire and the die pad, no conventional contact failure occurs.

As described above, the present invention is characterized in that the bonding wire forms a loop through the window of the die pad after the die pad is adhered onto the active surface of the semiconductor chip. In the semiconductor package, a defect such as short circuiting of the long loop bonding wire to the semiconductor chip may be prevented.

In addition, in the case of applying the above structure, in the wire bonding process, without limiting to some of the latest expensive equipment applied to the so-called "5th generation (16M Conventional type)" products that can ensure the horizontal distance of the bonding wire loops, so-called Existing equipment applied to "4th generation (16M LOC type)" products can be utilized.

That is, even if the horizontal distance of the bonding wire loop is not secured, the bonding wire is shorted by contacting the semiconductor chip or the die pad by bonding the die pad over the active surface of the semiconductor chip and forming the bonding portion of the leads at a position higher than the die pad. You can prevent it. In addition, when the bonding portion of the leads is formed at a position lower than the die pad, a short circuit of the bonding wire may also be prevented by using a structure in which an insulating material is formed along the outer upper surface of the die pad.

Therefore, the process of securing the horizontal distance of the bonding wire loop by using the latest expensive equipment is not necessarily required, and thus, the existing equipment can be utilized, thereby producing a pad-on-chip semiconductor package without replacing the equipment.

The semiconductor package according to the present invention includes a semiconductor chip having center pads and a die pad having a window corresponding to the center pad, and a bonding wire electrically connects the center pad and the bonding portion of the leads through the window. This structure prevents defects such as short-circuit of the bonding wires in contact with the semiconductor chip in the conventional chip-on-pad type semiconductor package, and furthermore, the horizontal distance of the bonding wire loop without making the horizontal distance. The pad-on-chip semiconductor package can be manufactured by using existing wire bonding equipment without additionally using the latest wire bonding equipment to secure the device.

Claims (3)

A semiconductor chip having an active surface provided with a plurality of center pads; A die pad in the form of a flat plate having windows corresponding to the center pads, the die pad being bonded onto the active surface; Leads separated from the die pad and including bonding portions arranged around the die pad; Bonding wires having a loop formed on the die pad and electrically connecting bonding portions of the respective center pads and corresponding leads through the window; And A molding resin encapsulating a region including the semiconductor chip, the die pad, and bonding portions of the bonding wires and the leads; Including; The die pad is formed so as not to be higher than the bonding portion of the leads, so that the bonding wire is not in contact with the die pad pad on chip type semiconductor package. The method of claim 1, wherein the die pad is formed by at least two recognition units that can be an alignment criterion of the center pads and the leads in the wire bonding process, the recognition unit is formed by modifying the planar shape of the window Pad-on-chip semiconductor package, characterized in that. A semiconductor chip having an active surface provided with a plurality of center pads; A die pad in the form of a flat plate having windows corresponding to the center pads, wherein an insulating material is attached along the upper edge of the flat plate, and the bottom surface of the flat plate is adhered to the active surface; Leads separated from the die pad and including bonding portions arranged around the die pad; Bonding wires having a loop formed on the die pad and electrically connecting bonding portions of the respective center pads and corresponding leads through the window; And A molding resin encapsulating a region including the semiconductor chip, the die pad, and bonding portions of the bonding wires and the leads; Including; And the bonding wire is not in direct contact with the die pad through the insulating material.

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