JPH10284846A - Structure for mounting ball grid array packaging type semiconductor component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent void connection of soldering and improve reliability of the connection. SOLUTION: BGA (Ball Grid Array) component 21 comprises a grid of bump solder and are connected to the first and second pad, 33 and 34, of the multilayer wiring board 22 by the solder connection 25. The first pad 33 positioned in the outside 2 row is connected to the surface conductor pattern 29. The second pad 34 positioned inside of the pad 33 is connected to the concave viahole formed nearby through the connection 36 and connected to the inner layer conductor pattern 30. The viahole 35 is disposed at an angle of 45 deg. from the second pad 34 and disposed between the pad 33 and 34. The periphery of the connection 36 and viahole 35 is covered by the solder resist 37. As the surface of the first and second pad, 33 and 34, are flat no air is left and the cream solder is printed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball grid array package type semiconductor having an improved structure for mounting a ball grid array package type semiconductor component on a multilayer wiring board having a plurality of pads for bump connection on its surface. The present invention relates to a component mounting structure.

[0002]

A ball grid array package type semiconductor component 1 (hereinafter abbreviated as a BGA component 1) has a mounting surface (lower surface) of a package 2 as shown in FIG. ), A large number of ball-shaped solder bumps 3 are formed in a grid shape. Although not shown, a multilayer wiring board having a large number of pads on the surface corresponding to the solder bumps 3 is used for mounting such a BGA component 1. Conventionally, the outer ones of the pads are arranged on the surface. The inner conductor is connected to the conductor pattern, and the inner conductor is connected to the inner conductor pattern via a through hole.

However, in such a multilayer wiring board using through holes, the area occupied by the through holes becomes large, so that the clearance between conductors becomes small, causing a problem in insulation, and the mounting density is increased ( High-density wiring). Therefore, in recent years, for example,
As shown in Japanese Patent No. 162767, a concave via hole has been used as an inner pad for bump connection instead of a conventional through hole.

That is, as shown in FIGS. 6 and 7 (e),
The multilayer wiring board 4 connects the pads 5 located in the outer two rows as so-called solid pads as they are to the surface conductor pattern 6 (only a part is shown), and connects the pads 7 located on the inner side with a so-called concave shape having a U-shaped cross section. The via hole 8 is connected to the inner conductor pattern 9. In addition, BGA
In mounting the component 1, as shown in FIG. 6, a cream solder 10 is printed on the pads 5 and 7, the BGA component 1 is mounted, and then the cream solder 10 and the solder bumps are passed through a reflow furnace. 3 is melted and hardened to make electrical and physical connections.

In this case, the multilayer wiring board 4 is manufactured by a built-up method as shown in FIG. First, inner layer conductor patterns 9 and 12 are formed on both upper and lower surfaces of the base substrate 11 (see FIG. 7A), and photosensitive insulating resins 13 and 13 are further laminated on both surfaces thereof.
A hole 13a is formed at a position (which becomes a position) by a photo method (see FIG. 7B). Next, copper plating is performed on both surfaces, and the surface conductor pattern 6, the pads 5, 7 and the conductor pattern 14 on the back surface are formed by etching (see FIG. 7C). Then, a conductor portion on the surface is plated with nickel and gold (see FIG. 7D), and finally, a solder resist 15 is formed (see FIG. 7E).

According to this, since the concave via hole 8 is formed by the photo method, the inner diameter of the concave via hole 8 is 0.1 mm.
The diameter of the pad 7 itself can be reduced to the same extent as the pad 5. Therefore,
Even if the arrangement pitch of the pads 5 and 7 is reduced, the minimum clearance between conductors can be set to, for example, about 0.15 mm, so that sufficient insulation can be ensured.

However, in the mounting structure using the concave via hole 8 as described above, when the BGA component 1 is mounted (see FIG. 6), the solder connection portion 16 of the pad 7 is formed.
There is a problem that void B is included in the inside. When the void B is generated in the solder connection portion 16 in this manner, a problem that the strength against stress is reduced and the reliability of the connection is reduced is caused. The cause of the void B in the solder connection portion 16 is considered to be due to the following mechanism.

[0008] That is, FIG.
The metal mask 17 is brought into close contact with the multilayer wiring board 4 and the squeegee 18 is moved on the upper surface of the metal mask 17 in the direction of arrow A.
Cream solder 10 supplied on metal mask 17
Is applied onto the substrate 4 (pads 5, 7) through the through holes 17a. However, when the cream solder 10 is applied through the through holes 17a of the metal mask 17, the cream solder 10
(See FIG. 6 (a)), and the lid is covered with the cream solder 10 in a state where air (bubbles) is confined in the via hole 8. Become.

Then, as shown in FIGS. 6B, 6C and 6D, when the BGA component 1 is mounted from that state,
When the cream solder 10 and the solder bump 3 are integrated and melted and hardened to form the solder connection portion 16, the air remaining in the via hole 8 causes the solder connection portion 16 to flow through the solder connection portion 16 in a subsequent reflow process. It moves up and becomes void B.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to mount a ball grid array package type semiconductor component capable of preventing the occurrence of voids in a solder connection portion and improving connection reliability. In providing structure.

[0011]

According to a first aspect of the present invention, there is provided a ball grid array package type semiconductor component mounting structure comprising: a ball grid array package type semiconductor component; and a plurality of pads for bump connection on a surface portion. A first pad connected to a surface conductor of the multilayer wiring board, wherein the pad is mounted on the multilayer wiring board via solder printed on the pad. And a second pad connected to the inner conductor of the multi-layer wiring board, wherein the second pad is provided in a via hole formed near the second pad, and in a surface portion of the multilayer wiring board. It is characterized in that it is configured to be connected to the inner layer conductor through the connection portion and the via hole by being connected by the provided connection portion.

[0012] According to this, the second pad is connected to the inner layer conductor through the via hole separated from the second pad, so that the surface can be made flat without irregularities. The surface of the first pad connected to the surface conductor is of course made flat. Accordingly, the solder is printed on the surfaces of the first and second pads, both of which are flat, and no air remains.

As a result, according to the present invention, it is possible to obtain an excellent effect that the occurrence of voids in the solder connection portion can be prevented and the reliability of the connection can be improved. At this time, the second pad can be made as small as the first pad, and the via hole can be formed by the photo method to reduce the occupied area. Therefore, it has been confirmed that even when the mounting density is high, the clearance required for insulation between conductors can be sufficiently ensured.

In this case, the via hole can be provided at a position shifted from the second pad by an angle of 45 degrees and at a central portion between the pads. According to this, the via hole can be efficiently arranged in the region between the pads without providing an extra region for providing the via hole on the multilayer wiring board, and the via hole and the other pad can be connected to each other. The insulation distance between the electrodes can be maximized, and the insulation property is sufficiently excellent.

Further, the connection portion and the surface of the via hole may be covered with a solder resist. According to this, the conductor is not exposed on the surface portion of the multilayer wiring board except for a necessary portion such as a pad, which is effective in terms of insulation.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. First, FIGS. 1 and 2 show a state where a ball grid array package type semiconductor component 21 (hereinafter abbreviated as BGA component 21) is mounted on a multilayer wiring board 22. FIG.

As shown in FIG. 5B, the BGA component 21 has a plurality of ball-shaped solder bumps 24 (which will be referred to as solder connection portions 25) on a mounting surface (lower surface in the figure) of a rectangular package 23. ) In a grid shape (grid shape). In this case, as can be understood from FIG. 2, the solder bumps 24 are formed in four lines in the inward and outward directions on the lower surface of the package 23 in a frame-shaped region excluding a rectangular region at the center thereof. Further, the pitch at which the solder bumps 24 are formed in the vertical and horizontal directions (and, consequently, the arrangement pitch of the pads to be described later) is as narrow as 1.0 mm or less and 0.8 mm in this case.

On the other hand, the multilayer wiring board 22 is manufactured by a built-up method as described later. In this case, as shown in FIGS. 1, 3, and 5, the multilayer wiring board 22 includes a front-side insulating layer 27 and a back-side insulating layer 28 on both sides of the intermediate insulating layer 26 (up and down in the figure). And the surface conductor pattern 29 and the surface-side insulating layer 27 located on the surface of the surface-side insulating layer 27.
The inner conductor pattern 3 is located between the
0, a backside conductive pattern 31 located on the backside of the backside insulating layer 28, and a backside inner layer conductive pattern 32 located between the backside insulating layer 28 and the intermediate insulating layer 26. I have.

As shown in FIGS. 2 and 4, the surface of the multilayer wiring board 22 (surface-side insulating layer 27) on which the BGA component 21 is mounted corresponds to the solder bump 24. And a plurality of bump connection pads 33, 3
4 are provided. Outside (left side in FIGS. 1 and 5) 2
A row of pads is a first pad 33, and a row of inner two rows is a second pad.

In this case, the first and second pads 3
Reference numerals 3 and 34 denote so-called solid front pads formed integrally with the surface conductor pattern 29. In the present embodiment, the first and second pads 33 and 34 are all formed in a circular shape having a diameter of, for example, 0.3 mm, and the pitch at both the vertical and horizontal sides is, for example, 0.8 mm.
The first pad 33 is connected to the surface conductor pattern 29 extending outward.

In the vicinity of each of the second pads 34, a concave via hole 35 is provided, and each of the second pads 34 and each of the via holes 35 are formed on the surface of the multilayer wiring board 22. Are connected by a connecting portion 36 made of a narrow conductor. In this embodiment, as shown in FIGS. 2 and 4, the via hole 35 is provided at a position shifted from the second pad 34 by an angle of 45 degrees and at a central portion between the pads 33, 34. I have.

The via hole 35 is formed as described later, and as shown in FIG.
7, a circular hole 27a (FIG. 3)
(See (b)), a conductor is provided in a continuous form at the bottom, the inner peripheral surface, and the ring-shaped portion around the top opening. The bottom of the via hole 35 is connected to the inner conductor pattern 30, and the ring-shaped portion around the upper surface is connected to the second pad 34 via the connection 36.

As a result, the second pad 34 is connected to the inner conductor pattern 30 via the connection portion 36 and the via hole 35. In this embodiment,
The via hole 35 has a diameter of 100, for example.
μm, the depth dimension is, for example, 70 μm, and the diameter dimension of the ring-shaped portion around the upper surface is, for example, 250 μm. Thus, the minimum clearance between the via hole 35 and the other pads 33, 34 is 0.1 mm or more, in this case 0.14.
mm is secured.

As shown in FIGS. 1 and 4, both the front and back surfaces of the multilayer wiring board 22 are provided with necessary portions (pads 3).
Except for the portions 3 and 34), they are covered with the solder resist 37. Accordingly, the surface portions of the connection portions 36 and the via holes 35 are also covered with the solder resist 37, and at this time, the solder resist 37 is filled in the holes of the via holes 35. The first and second pads 33 and 34 include:
As described later, a paste-like cream solder 38 (FIG. 5)
Is printed, and the BGA component 21 is mounted thereon.

Here, a method for manufacturing the multilayer wiring board 22 (built-up method) will be briefly described. FIG. 3 shows steps of manufacturing the multilayer wiring board 22 in order. First,
As shown in FIG. 3A, an inner conductor pattern 30 made of copper foil and a back inner conductor pattern 32 are formed on both upper and lower surfaces of a base substrate 39 serving as the intermediate insulating layer 26. Further, as shown in (b), photosensitive insulating resins 40 and 41 serving as the front-side insulating layer 27 and the back-side insulating layer 28 are laminated on the upper and lower surfaces of the base substrate 39, and a mask (not shown) is adhered thereto. After the exposure, development is performed to cure the photosensitive insulating resins 40 and 41 to form the front-side insulating layer 27 and the back-side insulating layer 28, and to form the via hole 35 later in the front-side insulating layer 27. Hole 27 in position
a is formed.

Next, as shown in (c), the upper surface of the front-side insulating layer 27 and the lower surface of the back-side insulating layer 28 are plated with copper and etched, so that the surface of the front-side insulating layer 27 is Conductive pattern 29 and first and second pads 3
3, 34, and the conductor portion and the connection portion 3 of the via hole 35
6 and the back conductor pattern 31 is formed. Then, as a finishing step, nickel and gold plating are sequentially applied to the conductor portions on both the front and back surfaces (see FIG. 3D), and finally, a solder resist 37 is applied, exposed and developed to complete the multilayer wiring board 22. (FIG. 3
(E)).

At this time, the solder resist 37 is provided so as to expose the first and second pads 33 and 34, as shown in FIG. 4, and covers the surface of the connection portion 36 and the via hole 35. It is provided as follows. Since the solder resist 37 is to be cured after applying a liquid material, the inside of the via hole 35 is also filled with the solder resist 37. In FIG. 4, the solder resist 37 is hatched for convenience.

Now, a procedure for mounting the BGA component 21 on the multilayer wiring board 22 configured as described above will be described with reference to FIG. FIG. 5 shows a procedure for mounting the BGA component 21 on the multilayer wiring board 22.
First, as shown in FIG. 5A, a step of printing and applying a cream solder 38 on the upper surface of the multilayer wiring board 22 (first and second pads 33 and 34) is performed.

In this printing process, the pads 33, 3
Metal mask 42 in which a through hole 42a corresponding to No. 4 is formed
Is used, and a metal mask 4 is
The squeegee 43 slides in the direction of arrow A while the cream solder 38 is supplied on the metal mask 42 so that the cream solder 3
8 is filled in the through hole 42a. Thereafter, when the metal mask 42 is raised, the cream solder 38 is printed in a raised state on the upper surfaces of the pads 33 and 34 through the through holes 42a.

Thereafter, as shown in FIG. 5B, the BGA component 21 is mounted on the multilayer wiring board 22 with the pads 33 and 34 and the solder bumps 24 aligned. Then, it is passed through a reflow furnace (not shown) and heated to, for example, 183 ° C. or more, so that the heat treatment shown in FIG.
As shown in FIG.
Are melted and integrated, and then cooled,
As shown in (d), the solder hardens and the solder connection 2
Thus, the electrical and physical connection of the BGA component 21 to the multilayer wiring board 22 is made.

However, at this time, as described in the conventional example, in the case where the pad 7 and the inner layer conductor pattern 9 are connected by using the concave via hole 8, air is trapped in the concave via hole 8. In this state, the cream solder 10 is printed, and there is a possibility that the void B is generated in the solder connection portion 16. However, in the present embodiment, not only the surface of the first pad 33 is flat, but also the second pad 34 is connected to the inner conductor pattern 30 via the connection portion 36 and the via hole 35. The surface can be made flat without irregularities.

Therefore, according to the present embodiment, the cream solder 38 is printed on the flat surfaces of the first and second pads 33 and 34 without any air remaining, and the solder connection portion is formed. 25 can be prevented from generating voids. As a result, unlike the conventional mounting structure, an excellent effect that the reliability of connection can be greatly improved can be obtained.

At this time, the second pad 34 is connected to the first pad
It is needless to say that the diameter of the pad 33 can be made as small as that of the pad 33, and the via hole 35 is formed by the photo method so that the occupied area can be reduced. Wiring) Even under circumstances, the clearance required for insulation between the conductors, that is, at least 0.14 mm in this embodiment, could be secured. In this case, in particular, in the present embodiment, the via hole 35 is provided at a position shifted from the second pad 34 by an angle of 45 degrees and at the center between the pads 33, 34.
Can be efficiently arranged in the region between the pads 33 and 34, but the insulation distance between the via hole 35 and the other pads 33 and 34 can be maximized.

Further, in this embodiment, the surface portions of the connection portions 36 and the via holes 35 are
, The conductor is not exposed on the surface of the multilayer wiring board 22 except for the necessary parts such as the pads 33 and 34, so that it is more effective in terms of insulation. Benefits can be obtained.

The present invention is not limited to the above-described embodiment. For example, even in the same row, the first pad and the second pad may be provided so as to be mixed.
Further, the via hole may be provided at a position spaced inward from the formation region of the second pad. Moreover,
The dimensions and manufacturing method of each part described above are merely examples, and various modifications can be made.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, and is an enlarged vertical sectional front view showing a mounting structure of a BGA component on a substrate.

FIG. 2 is a plan view of a main part showing a mounting structure of a BGA component on a substrate.

FIG. 3 is a diagram showing a manufacturing process of the multilayer wiring board;

FIG. 4 is a plan view of a main part of the multilayer wiring board.

FIG. 5 is a diagram showing a mounting process of a BGA component.

FIG. 6 is a diagram corresponding to FIG. 5 showing a conventional example.

FIG. 7 is a diagram corresponding to FIG. 3;

[Explanation of symbols]

In the drawing, 21 is a ball grid array package type semiconductor component, 22 is a multilayer wiring board, 24 is a solder bump,
5 is a solder connection part, 27 is a front side insulating layer, 27a is a hole,
29 is a surface conductor pattern, 30 is an inner layer conductor pattern, 3
Reference numeral 3 denotes a first pad, 34 denotes a second pad, 35 denotes a via hole, 36 denotes a connection portion, 37 denotes a solder resist, and 38 denotes a cream solder (solder).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koji Numata 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Inside DENSO Corporation

Claims (3)

[Claims] 1. A structure in which a ball grid array package type semiconductor component is mounted on a multilayer wiring board having a plurality of pads for bump connection on a surface portion thereof via solder printed on the pads. The pad includes a first pad connected to a surface conductor of the multilayer wiring board, and a second pad connected to an inner layer conductor of the multilayer wiring board, and the second pad Is connected to a via hole formed in the vicinity of the second pad by a connecting portion provided on a surface portion of the multilayer wiring board, and is connected to the inner layer conductor through the connecting portion and the via hole. A mounting structure of a ball grid array package type semiconductor component, which is connected. 2. The ball grid array according to claim 1, wherein the via hole is provided at a position shifted from the second pad by an angle of 45 degrees and at a central portion between the pads. Packaging structure for packaged semiconductor components. 3. The mounting structure of a ball grid array package type semiconductor component according to claim 1, wherein a surface portion of the connection portion and the via hole is covered with a solder resist.