JPH1027467A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve versatility by properly changing the number of bits of input/output data and the number of I/O while efficiently utilizing a shift regis ter in an input/output circuit. SOLUTION: This device is provided with a function circuit block 2 and an input circuit 4. The input circuit 4 is provided with a plurality of external input terminal (I1, etc.), a shift register 10 series/parallel-converting input data in the input circuit 4 comprises a plurality of unit shift registers 22 shifting successively input data in accordance with applying of a clock signal CKW, these are connected in series through an input switching means 24. Each input switching means 24 separates an input terminal (D terminal) of the unit shift register 22 of a post stage side from an output terminal (Q terminal) of the unit shift register 22 of a preceding stage in accordance with an input terminal selection signal (gr- a, etc.), and connects it to the external input terminal (I1, etc.). An output circuit 6 is properly provided with a plurality of output terminals (O1, etc.), with interval in accordance with the number of bits of output data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device which has improved versatility by effectively changing the number of I / Os while effectively utilizing a shift register in an input / output circuit provided in an LA (Programmable Logic Array) or the like.

[0002]

2. Description of the Related Art For example, in various semiconductor memories,
In the memory array, data writing and reading are usually performed for each word line. However, if the input / output data is handled as parallel data, the number of input / output terminals becomes too large,
High integration cannot be achieved. For this reason, in the input / output circuit connected to the memory array, the input data is serial-parallel-converted by the shift register and sent into the memory array, and conversely, the output data is taken out from the output circuit after the parallel-serial conversion. ing.

On the other hand, in order to increase the speed of a semiconductor memory, a memory array may be divided into predetermined blocks, and data may be written or read in units of these blocks. In this case, the input / output circuit handles a plurality of input / output data at the same time. Therefore, the number of stages of the shift register is determined in advance according to the number of bits, and the serial / parallel conversion of the input / output data is performed by using a plurality of shift registers. Was being done.

[0004]

However, in this conventional semiconductor device, the number of stages of each shift register is fixed, and a general-purpose product needs to be able to cope with data having a somewhat different number of bits. In accordance with the number of input / output data bits, several product lineups must be prepared in advance.

Further, the number of bits of data to be handled and I / O
In some cases, the number was expected to change during the design stage or during use after commercialization. In this case, since the number of stages of the shift register can be reduced, but cannot be increased, the shift register has to be configured in accordance with the maximum number of bits assumed in advance. Therefore, in some cases, there is a useless area that is not used for the shift register. On the other hand, if a plurality of types of shift registers are prepared in accordance with the expected number of bits of data, some shift registers are not used at all, and the occupied area of the entire input / output circuit increases.
Not preferred.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has been made in consideration of the size of input / output data and I / O data while effectively utilizing a shift register in an input / output circuit provided in a functional circuit block such as a memory array. It is an object of the present invention to newly provide a semiconductor device with improved versatility by allowing the number of O to be appropriately changed.

[0007]

In order to solve the above-mentioned problems of the prior art and achieve the above object, a semiconductor device according to the present invention employs a functional circuit block in which unit cells are arranged in an array. The input circuit that receives serial data and converts the data into parallel data and outputs the data is provided with a plurality of external input terminals to which serial data can be input from the outside. The shift register in the input circuit is composed of a plurality of unit shift registers for sequentially shifting input data in response to application of a clock signal, and these are connected in series via input switching means. Each of the input switching means connects the input terminal of the unit shift register on the subsequent stage to
In accordance with the input terminal selection signal, it is disconnected from the output terminal of the preceding unit shift register and connected to any of the external input terminals determined for each connection point.

That is, when an input terminal selection signal controls which input switching means is operated in accordance with the number of bits of input data, the input switching means is multiplied by an integral multiple of the unit shift register.
The size of the shift register assigned to each input data can be expanded or reduced. This makes it possible to minimize the useless shift register and its area that are not used, and to use the shift register effectively.

On the other hand, with respect to the output circuit, a plurality of output terminals are appropriately provided at intervals according to the number of bits of the output data, and if the user selects which output terminal is used, the desired output data can be obtained. To be able to obtain. As described above, the size of the input / output data and the number of I / Os of the input / output circuit can be appropriately changed by rewriting the content of the input terminal selection signal or changing the output terminal to be selected.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention has an input circuit and an output circuit, and comprises a functional circuit block for handling digital information via these input / output circuits. The functional circuit block is not particularly limited as long as it has an array configuration. For example, it may be a memory array such as a DRAM or an SRAM, or a logic array having a predetermined function by combining logic gates. As a logic array, for example, a PLA (ProgrammedLog) for electrically programming
ic Array), or a read-only logical array that performs programming in the middle of a process using a master slice. Further, when referred to as a functional circuit block, in addition to the memory array and the logic array, a circuit in which peripheral circuits (for example, a sense amplifier or the like) are combined may be used.

Hereinafter, a case where the present invention is applied to a DRAM will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a DRAM according to the present embodiment. In the figure, reference numeral 2 denotes a DRAM memory array, 4 denotes an input circuit, and 6 denotes an output circuit.

The memory array 2 of the DRAM corresponds to the functional circuit block of the present invention, and has 256 memory cells in the column direction (vertical direction in the figure) and 1024 memory cells in the row direction (horizontal direction in the figure). They are arranged in a matrix. The memory array 2 is connected to an address decoder 8 for decoding the input address signals A0 to A9 and appropriately selecting a word line. Therefore, this DRAM can access a memory cell of 256 bits at a time in a row unit.

On the input port side of the memory array 2,
The input circuit 4 is connected, and the input circuit 4
It comprises a first shift register 10 which outputs after converting input data (serial data) into parallel data, and a register 12 which temporarily stores the parallel data from the first shift register 10 and outputs it to the memory array 2. Have been. The first shift register 10 is provided with a plurality of external input terminals so that a plurality of data can be input.
In the present invention, since the number of I / Os is made variable, the number of external input terminals is set to a maximum
O number is determined. Specifically, in the example of FIG. 1, 16 external input terminals I0 to I15 are provided. The internal configuration of the D-type flip-flops (D-type
FF) are connected in series, whereby serial-parallel conversion of 256-bit input data is possible.

On the other hand, the output circuit 6 is connected to the output port side of the memory array 2, and the output circuit 6 is provided with a latch 14 for temporarily storing output data (parallel data) from the memory array 2. And a second shift register 16 for converting the parallel data from the latch 14 into serial data. The second shift register 16 has an external output terminal O0 so that output data can be taken out as serial data in accordance with the number of bits.
ＯO15 are provided. The number of external output terminals is also determined in advance to the maximum number of I / Os, similarly to the external input terminals. The configuration of the second shift register 16 and the first shift register 10 and changes in the number of I / Os will be described later in detail.

In addition, an access control signal XCE and a read / write control signal XWE are input to this semiconductor memory, thereby generating a clock signal and the like for controlling data exchange between the memory array 2 and the latch 14 and the like. An input terminal selection signal (group signal gr) for selecting a set of terminals capable of receiving data from the clock generator 18 to be output and the external input terminals I0 to I15 of the input circuit 4.
_A to gr_e)
Are provided.

FIG. 3 shows the circuit configuration of the input / output circuit of the semiconductor memory in detail. As described above, the input circuit 4 is provided with external input terminals I0 to I15 to which input data (serial data) can be input from the outside.
First shift register 10 constituting the input circuit 4
Is composed of a total of 256 DFFs by further connecting 16 DFF rows 22 in which 16 DFFs are connected in series.

As shown in the enlarged view of FIG. 3, input connection means (selector 24) is provided at each connection point of this DFF row 22.
Is interposed. Each selector 24 has its A input terminal connected to one of the external input terminals I0 to I15. The B input terminal is connected to the output of the preceding DFF row 22, and the select B terminal receives one of the input terminal selection signals (group signals gr_a to gr_e from the pin select decoder 20 in FIG. 1). Connected as possible. Then, the output terminal of each selector 24 is
As shown in FIG. 3, it is connected to the D terminal of the first stage DFF0 constituting the second stage DFF row 22. Each of the selectors 24 connected in this manner outputs the group signals gr_a to gr_g.
In accordance with r_e, the input terminal (D terminal of DFF0) of the subsequent DFF row 22 is disconnected from the output terminal (Q terminal of DFF15) of the preceding DFF row 22, and the corresponding external input terminals I0 to I15 are disconnected. It has a function of connecting to any one (I1 in FIG. 3).

25 constituting the first shift register 10
Registers 12 are connected to the Q terminals of the six DFFs as shown in FIG. The register 12 is basically configured by connecting another DFF for temporarily storing data between the Q terminal of each DFF and the memory array 2. Further, a selector for simultaneously transferring data with the data load signal LDW at the time of writing is interposed between the two DFFs. In this case, the A terminal of each selector is connected to the output of the DFF on the register 12 side. As a result, the LD is connected to the select B terminal.
The latch loop formed when W is not input is interrupted when LDW is input.

On the other hand, in the output circuit 6, a latch 14 having a substantially similar configuration is provided. However, this latch 1
Reference numeral 4 indicates that a selector is connected to the output side of the DFF constituting the selector. Thereby, the data load signal L at the time of reading is
Data transfer is performed at the DR application timing.

A second shift register 16 is connected to the output side of the selector. That is, each D terminal of the 256 DFFs connected in series is connected to the output terminal of the selector, and the DFFs are connected to each other in series via this selector. In the present invention, a plurality of external output terminals are taken out of the second shift register 16. In the case of this embodiment,
The external output terminals O0 to O15 are provided at the same interval corresponding to the above-mentioned external input terminals I1 to I15. That is, each of the external output terminals O0 to O15 is connected to the Q of the first stage DFF0 of the 16-stage DFF row 22 similarly to the input circuit 4 side.
Removed from terminal.

The input / output circuit 4 having the configuration described above
In 6, the state of the group signals gr_a to gr_e for selectively switching the selector 24 on the input circuit 4 side is usually based on the number of bits of the input / output data and the external input terminals I0 to I15 and the external output terminals O0 to O15. (Hereinafter, both are collectively referred to as external input / output terminals).

FIG. 4 summarizes the relationship between external input / output terminals to be selected in this embodiment and their grouping. Here, I / O0 to I / O15 denote external input / output terminals I0 to I15 and O0 to O15, respectively.
Each number of x2, x4, x8, and x16 represents the number of I / O. In the figure, the number of I / Os is x1, x2, x4, x8, x
If it is different from 16, a circle is marked in the column of I / O0 to I / O15 to be selected. Then, I / Os selected only in the case of x16 are group a, I / Os selected in the case of x16 and x8 are group b, and so on. It is classified into.

As shown in FIG. 4, if the I / O selection has regularity, the maximum value of the number of bits of the input data is determined by the DF
An integer multiple of the number of DFFs constituting the F column 22 (2 in this table)
Double) to step up uniformly. For example, x16 where all the external input / output terminals I / O0 to I / O15 are selected
In the case of (1), the number of bits of the input data is one DFF row 22, that is, up to 16 bits. In the case of x8, however, the number of bits can be set up to 32 times that number. Similarly, the number of bits of input data is up to 64 bits for x4 and 1 for x2.
Up to 28 bits can be set, and external I / O terminals I0 and O
In the case of x1 where only 0 is selected, at most memory array 2
256-bit data for one row can be input / output.

FIG. 5 shows pin select signals PS0, PS1, and PS2 input to the pin select decoder 20, and
The correspondence relationship with the group signals gr_a to gr_e after the decoding is shown. Group signals gr_a to gr_
"e" is a signal for identifying which of the five groups in FIG. 4 each external input / output terminal I / O0 to I / O15 belongs to. Here, 5 of the three input signals
Two group signals gr_a to gr_e are generated. The three-input pin select decoder 20 can generate up to eight group signals.

Hereinafter, the data input / output operation of the semiconductor memory 2 will be described with reference to the timing charts of the signals shown in FIGS. First, a data input operation when the number of I / Os of the input circuit 4 is x16 will be described. The number of I / Os is set by setting the state of the pin select signal to [PS2, PS1, PS2
0] = [0, X, X] (X means 0 or 1). As a result, in the pin select decoder 20, the group signal gr_
a to gr_e are all set to “0” (low level) based on FIG. Then, I / Os belonging to all the groups in FIG. 4 are selected. That is, all the selectors 24 in FIG. 1 separate the preceding and succeeding DFF strings, and connect the input terminal (D terminal of the first-stage DFF1) of the succeeding DFF string to the corresponding I / O. As a result, 16
A state in which 16 bit input data can be input in parallel is prepared.

On the other hand, since the input signals XCE and XWE are both low active, the clock generator 18
As shown in FIG. 6, a clock signal CK synchronized every 16 clocks is output from the clock generator 18.
W and CKR are output. Of these, the clock signal CK
W is the input circuit 4 of FIG.
Is used as a synchronization signal at the time of data transmission. Therefore, for each pulse of the clock signal CKW, the input data is fetched bit by bit from all the external input terminals I0 to I15, and is sequentially transferred to the subsequent DFF.

Then, the data is sent to the last stage in each DFF column 22 and the 16-bit data is arranged in the first shift register 10, and is written to the register 12 of the next stage. It is sent by the data load signal LDW at the time, and is held in the register 12. This register 1
The data holding state in No. 2 is indicated by DWlatch in FIG.
Thereafter, although not particularly shown, the clock generator 1
After waiting for a write signal of 2 from 8 to the memory array, 16 pieces of 16-bit data are simultaneously written into the memory array 2 at the timing of the write signal.

When the input port is changed to x8, the state of the pin select signal is [PS2, PS1, PS0] =
Switch to [1,0,0]. As a result, in the pin select decoder 20, only the group signal gr_a among the group signals gr_a to gr_e, which are the output signals, becomes “1” (high level) and the other signals are maintained at low level based on FIG. . Then, based on FIG.
External input terminals I1, I3, I5, I belonging to group a
7, I9, I11, I13, and I15 are not selected. That is, the selector 24 to which these external input terminals are connected is connected to the input terminal (first stage DF) of the subsequent DFF row.
The D1 terminal of F1 is disconnected from the external input terminal and connected to the output terminal of the preceding DFF row (the Q terminal of the last DFF15). Other external input terminals I0, I2, I4, I6,
Since I8, I10, I12, and I14 remain selected, input data can be accepted in the same manner as described above. As a result, a state in which eight DFF columns, that is, eight pieces of 32-bit input data can be input in parallel is prepared.

Thereafter, as in the case of X16 described above,
The double 32-bit data is sequentially sent to the first shift register 10 by the clock signal CKW, and when eight 32-bit data are arranged in the shift register 10, the eight data are transferred to the next stage. LD in register 12
W is sent in, and is held in the register 12 until a write signal is input.

Finally, the data output operation when the number of I / Os of the output circuit 6 is x16 will be described. Sixteen 16-bit data read out in the memory array 2 are fetched into the latch 14 by the latch_ld signal from the clock generator 18 as shown in FIG. The data holding state of the latch 14 is indicated by DRlatch in FIG.

Thereafter, the held data is transferred to the second shift register 16 in the next stage by the data load signal LDR at the time of reading.
And outputs the data from the external output terminals O0 to O15 while transferring the clock signal CKR toward the subsequent stage of the second shift register 16.

In the case of this embodiment, the second shift register 16 on the output side is the first shift register 1 on the input side.
0 is opposite to the data sending direction, and the LIFO (Last-In
First-Out) data input / output format is adopted. Therefore, from the external output terminal O0, the last input 16
Reverse output data with the lower bit of the bit data at the beginning is obtained, and from the next external output terminal O1, reverse output data with the lower bit of the second to last input data at the beginning are obtained.

When the number of I / Os of the output circuit 6 is x8, the output data is the same. In this case, the user selects every other external output terminals O0 to O15 from which output data is to be taken out according to FIG. 4, and the unused external output terminals O1, O3,...

In the output circuit 6 having such a configuration,
Since the output data is also forwarded in the second shift register 16, even if the number of clocks of the clock signal CKR becomes equal to the number of bits of the output data, there is no new data loaded in the second shift register 16, When the clock signal is continuously applied, the same data as that output from the external output terminal at the subsequent stage flows. In order to prevent this, similarly to the input circuit 4, a selector 24 for appropriately separating the DFF row 22 according to the group signals gr_a to gr_e may be provided on the output circuit 6 side.

If the data input / output format is to be FIFO (First-In First-Out) instead of LIFO,
The connection between DFFs may be changed in the second shift register 16.

[0036]

As described above, according to the semiconductor device of the present invention, the input circuit increases the size of the shift register internally allocated to each input data by an integral multiple of the unit shift register. Can be expanded and contracted. Therefore, even if the number of I / Os and the data length are assumed to be plural, the unused area in the shift register divided by the number of I / Os and assigned to each input data is reduced as much as possible. Effective utilization can be achieved. In particular, the number of data bits (1
(6 bits, 32 bits,...), When the number of bits differs by an integral multiple, no useless area is generated in the shift register.

Further, since the flip-flop columns are appropriately separated from each other and data interruption can be input therefrom, the number of I / Os can be made variable. The degree of freedom of connection can be increased. Further, a data transfer cycle and a data input / output operation cycle of the semiconductor device can be changed. This allows
In addition to changing the data length and the number of I / Os on the way, it can be used in various applications such as connecting a plurality of functional circuit blocks having different bit widths with one set of input / output circuits.

Therefore, according to the present invention, it is possible to provide a highly versatile semiconductor device which can switch the size of input data and the number of I / Os and can be used in various applications.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a DRAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing the inside of an input / output circuit of the DRAM of FIG. 1;

FIG. 3 is a circuit diagram showing the input circuit of FIG.
It is an enlarged view which shows the connection part of a flop row.

FIG. 4 is an explanatory diagram showing the relationship between external input / output terminals to be selected and their grouping.

FIG. 5 is an explanatory diagram showing a correspondence between a pin select signal input to a pin select decoder and a group signal after the decoding;

FIG. 6 is a timing chart of each signal showing a data input / output operation of the DRAM of FIG. 1 when the number of I / Os is set to 16;

FIG. 7 is the same timing chart when the number of I / Os is set to 8;

[Explanation of symbols]

2 ... memory array (functional circuit block), 4 ... input circuit, 6 ... output circuit, 8 ... address decoder, 10 ... first
Shift registers, 12 ... registers, 14 ... latches, 1
6 ... second shift register (shift register), 18 ...
Clock generator, 20 ... pin select decoder,
22: DFF row (unit shift register), 24: selector (input switching means), I0 to I15: external input terminal, O0
... O15 ... External output terminal (output terminal), DFF ... D-type flip-flop, A0 -A9 ... Address signal, CKW ...
Clock signal for writing, CKR: Clock signal for reading, gr_a to gr_e: Group signal (input terminal selection signal), LDW: Data load signal for writing, LDR ...
Data load signal at the time of reading, latch_ld ... latch signal,
PS0 to PS2: pin select signal, XCE: access control signal, XWE: read / write control signal.

Claims (3)

[Claims] An input circuit includes a functional circuit block in which unit cells are arranged in an array, and converts input serial data into parallel data in the input circuit and outputs the parallel data to the functional circuit block. A plurality of external input terminals each of which is capable of inputting serial data from outside, wherein the input circuit sequentially shifts input data in response to application of a clock signal in the input circuit. A plurality of shift registers are connected in series, and at each connection point between the unit shift registers, an input terminal of a subsequent unit shift register is connected to an input terminal of a unit shift register of a preceding stage in accordance with an input terminal selection signal. Input switching means for disconnecting from the output terminal and connecting to any of the external input terminals determined for each connection point is provided for each connection point. Semiconductor device. 2. An image processing apparatus comprising: a functional circuit block configured by arranging unit cells in an array; and an output circuit, receiving parallel data from the functional circuit block, converting the parallel data into serial data, and outputting the serial data to the outside as output data. A semiconductor device comprising a shift register in an output circuit, wherein the shift register is provided with a plurality of output terminals as appropriate at intervals according to the number of bits of the output data. 3. An output circuit in addition to the functional circuit block and the input circuit, wherein the output circuit receives parallel data from the functional circuit block, converts the data into serial data, and outputs the serial data. 2. The semiconductor device according to claim 1, further comprising: a shift register that outputs the data to the outside, wherein the shift register is provided with a plurality of output terminals as appropriate at intervals according to the number of bits of the output data.