JPH10261717A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide various logic circuits even with one PLT circuit by using a plurality of pass transistor logics which have one of the source/drain channels in a transfer gate MOSFET and a gate as input side and the other channel as output side. SOLUTION: A circuit composed of MOSFETs Q3 and Q4 are connected with MOSFETs Q1 and Q2 which constitute an α cell by multistage connection, and a pass transistor logic called β cell is constituted. Namely, on the output node side of the MOSFETs Q1 and Q2, a similar logic stage composed of the MOSFETs Q3 and Q4 are connected in series, one of the source/drain channels of the MOSFET Q4 is used as an input terminal C, and the gates of the MOSFETs Q3 and Q4 are provided with a pair of complementary input terminals E and /E. Then, the other source/drain channels of the MOSFETs Q3 and Q4 is commonly connected to be a logic output node X and an output circuit is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology that is effective when used as a logic correction technology in a semiconductor integrated circuit device whose circuit function is determined by a standard cell system.

[0002]

2. Description of the Related Art There is a standard cell type semi-custom LSI (large-scale integrated circuit device). In the standard cell system, the entire chip is designed by combining standard cells designed in advance. Unlike the gate array, the standard cell method combines various cells whose interiors are freely designed. Therefore, like the full custom LSI, it is necessary to manufacture all the masks for each chip. Therefore, the development cost is higher than that of the gate array, but the same function can be realized on a small chip, so that the manufacturing cost is reduced. Regarding such a standard cell system, Nikkei McGraw-Hill 1
“Nikkei Electronics” No. 166, September 9, 985
Page to page 192.

[0003]

In the above standard cell system, dummy cells are provided for correcting the logic of the standard cells. The dummy cell is used when a logic block in which several tens of commonly used cells are interconnected is mounted as a dummy block, and the logic needs to be corrected. However, since the logic failure itself cannot be predicted, there is a problem in that when the dummy cell mounted on the corner is intended to correct it, it is often impossible to correct the logic to match it. For this reason,
It is conceivable to provide a dummy cell with some margin,
By doing so, waste in the dummy cell part increases,
There is a contradiction that the high integration of the standard cell method cannot be utilized.

An object of the present invention is to provide a semiconductor integrated circuit device based on a standard cell system having dummy cells capable of efficiently modifying the logic with a small circuit scale. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a signal processing circuit for performing a desired digital signal processing is realized by using a plurality of types of standard cells in which specific logic functions are designed in advance, and designing the layout and wiring for connecting the standard cells. In a standard cell type semiconductor integrated circuit device, dummy cells used for logic correction are appropriately provided between the standard cells, and one of the source-drain paths in the transfer gate MOSFET and the gate are input as such dummy cells, A plurality of pass transistor logics having the other of the source-drain paths as the output side are used.

[0006]

FIG. 1 shows a pass transistor logic (PT) constituting a dummy cell mounted on a standard cell type semiconductor integrated circuit device according to the present invention.
L) A circuit diagram of one embodiment is shown. Each circuit element in the figure is formed on one semiconductor substrate together with another circuit element including a standard cell (not shown) by a known semiconductor integrated circuit manufacturing technique.

The pass transistor logic shown in FIG. 1 is called an α cell, and connects two N-channel MOSFETs Q1 and Q2 in parallel to each other,
One of the source-drain paths of ETQ1 and Q2 is set as input terminals A and B, the gates of the MOSFETs Q1 and Q2 are set as input terminals C, and complementary signals C and / C are supplied. The complementary signals C and / C supplied to the gates of the MOSFETs Q1 and Q2 are complementary signals in which C has a high level as a significant level and / C has a low level as a significant level. The other of the source-drain paths of the MOSFETs Q1 and Q2 is commonly connected to be a logical output node X.

Although not particularly limited, when the logic is formed using the transfer gate MOSFET as described above, the source-drain path of the MOSFETs Q1 and Q2 is determined by the threshold voltage between the gate and the source of the MOSFET Q1 or Q2. In the other logic output node X, the level on the high level side drops. Therefore, an output circuit having a pull-up function is provided in the output unit.

The output circuit is a MOSFE shown by way of example.
It consists of TQ10 to Q14. P-channel type MOSFE
TQ10 and N-channel MOSFET Q11 are CM
The output node X is connected to an input terminal IN, and an output signal is formed from an output terminal OUT of the OS inverter circuit. The following pull-up circuit is provided at the input portion of the output CMOS inverter circuit including the MOSFETs Q10 and Q11. The signal at the input terminal IN is input to a driving CMOS inverter circuit composed of a P-channel MOSFET Q12 and an N-channel MOSFET Q13.
Drive OSFET Q14. This pull-up MOSF
ETQ14 is composed of a P-channel type MOSFET,
It is provided between the input terminal IN (output node X) and the power supply voltage (high level side).

The operation of the output circuit is as follows.
When the logical output node X is at a low level, the output inverter circuits (Q10, Q11) correspondingly generate a high-level output signal. At this time, the driving CM
Since the OS inverter circuits (Q12, Q13) also generate high-level drive signals, the pull-up P-channel MOSFET Q14 is turned off. On the other hand, when the logic output node X is at the high level, the high level is set to the N-channel MOSFET as described above.
Is lowered by the threshold voltage between the gate and the source. The output inverter circuit (Q10, Q1
1) correspondingly forms a low-level output signal. At this time, the driving CMOS inverter circuit (Q1
2, Q13) form a low-level drive signal, so that the pull-up P-channel MOSFET Q14
Is turned on, and the level of the input terminal IN is pulled up to the power supply voltage (high level side). This allows
In the two CMOS inverter circuits, the P-channel MOSFETs Q10 and Q12 are turned off, and the signal input to the next-stage circuit is set to the CMOS level while minimizing the leakage current there.

The logic which can be realized by the α cell is as follows. When the input terminal A and the input terminal C are used and the input terminal B is fixed at a low level (logic 0), the logic becomes NAND (Nand) logic. That is, only when the input terminal A is at the high level, the input terminal C is at the high level, and the MOSFET Q1 is in the ON state, the logical output node X is at the high level. In other combinations, that is, the input terminal C is at the high level and the MOSFET Q1 is turned on. In this state, if the input terminal A is at a low level, a low level is output. If the input terminal C is at a low level, the MOSFET Q1 is turned off, and the high level of the input terminal / C turns on the MOSFET Q2 irrespective of the input terminal A. The fixed low level of the input terminal B is output. Since the inverted signal is output from the output circuit, the logical output node X is inverted, so that the NAND logic becomes as described above.

When the input terminal A is fixed to a high level (logic 1) using the input terminals B and C, the logic becomes NOR (Nor). That is, when the input terminal B is at a low level and the input terminal C is at a low level, the MOSFET Q1 is turned off, and when the input terminal / C is at a high level, the MOSFET Q1 is turned off.
2 is only in the ON state, the logic output node X is at the low level, and other combinations, that is, the input terminal C
Is high level and the MOSFET Q1 is on, the fixed high level of the input terminal A is output irrespective of the input terminal B, and the MOSFE is determined by the high level of the input terminal / C.
If the input terminal B is at a high level when TQ2 is on, a high level is output. Since the inverted signal is output from the output circuit, the logic output node X is inverted, so that the above NOR logic is obtained.

When the inverted signal / A of the input terminal A is supplied to the input terminal B, an exclusive OR circuit is formed. That is, when the two input signals A, / A, C, and / C match, in other words, when the input signal A is at a high level and the input signal C is at a high level, the input signal A is turned on by the ON state of the MOSFET Q1. When the high level is output to the logical output node X, the input signal A is low and the input signal C is low, the high level of the input signal / A is output to the logical output node X by the ON state of the MOSFET Q2, and the input signal A When C and C do not match, the input signal C is at a high level.
This is because the low level of the input signal A is output according to the ON state of the SFET Q1, and the low level of the input signal / A is output according to the ON state of the MOSFET Q2 if the input signal A is at the high level because the input signal C is at the low level. Since the inverted signal is output from the output circuit, the logical output node X is inverted, so that an exclusive OR circuit as described above is obtained.

In addition, if the input signals C and / C are set to a fixed level, it goes without saying that an inverter circuit for inverting the input signal A or B is formed. As described above, four types of logic can be adopted by the α cell. In other words, in the pass transistor logic, since a large number of logics can be determined by setting signals or potential levels supplied to the input terminals A, B and C and / C as described above, a logic having a wide application range with a small number of element primes is used. Can be used for correction.

FIG. 2 shows a standard according to the present invention.
A circuit diagram of another embodiment of a pass transistor logic (PTL) constituting a dummy cell mounted on a cell type semiconductor integrated circuit device is shown. The pass transistor logic shown in FIG. 1 is called a β cell, and MOSFETs Q1 and Q2 constituting the α cell are:
A circuit comprising MOSFETs Q3 and Q4 is connected in multiple stages. That is, a similar logic stage composed of MOSFETs Q3 and Q4 is connected in series to the output nodes of the MOSFETs Q1 and Q2, and one of the source-drain paths of the MOSFET Q4 is used as the input terminal C.
And Q4 have a pair of complementary input terminals E and / E. The MOSFETs Q3 and Q3
The other of the four source-drain paths is commonly connected to form a logical output node X, and an output circuit similar to the above is provided.

FIG. 3 is a circuit diagram of a logic circuit which can be realized by the β cell shown in FIG. Since the β cell is configured by a combination of the two-stage configuration of the α cell, the above three types of logic by the MOSFETs Q1 and Q2 and the three types of logic by the MOSFETs Q3 and Q4 are combined, One obtains a logic circuit in which a NAND gate circuit NAND is arranged at the output of the exclusive OR circuit EX as shown in FIG.
(C) to obtain a logic circuit in which a NOR gate circuit NOR is arranged at the output of the exclusive OR circuit EX, and (2) a two-input AND gate circuit AND as shown in FIG.
(D) in which a logic circuit in which a NOR gate NOR is arranged at the output of a three-input AND gate circuit is obtained.
As shown in the figure, an AND gate circuit, an OR gate circuit OR
And a logic circuit in which NOR gates NOR are arranged in multiple stages to achieve a logic circuit.

FIG. 4 shows a standard according to the present invention.
A circuit diagram of still another embodiment of a pass transistor logic (PTL) constituting a dummy cell mounted on a cell type semiconductor integrated circuit device is shown. The pass transistor logic shown in the figure is called a γ cell, and two MOSFETs Q1, Q2 and Q5, Q6 constituting the α cell are provided with the same MOSFET as the β cell.
The circuit composed of TQ3 and Q4 is connected in multiple stages.
In other words, similar logic stages comprising MOSFETs Q3 and Q4 are connected in series to the output nodes of the MOSFETs Q1 and Q2 and Q5 and Q6. In other words, three logic parts of α cells are combined and arranged in multiple stages symmetrically with respect to the signal transmission path direction. In this configuration, a more complicated logic circuit can be realized, including a logic circuit realized by the α cells and β cells.

FIG. 5 is a schematic block diagram showing one embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 1A shows an example of a polycell type, and FIG. 1B shows an example of a building block type. Each circuit block in the figure is drawn according to a geometrical arrangement formed on an actual semiconductor substrate.

In the polycell type shown in FIG. 1A, cells having the same cell height and different cell widths in each standard cell are arranged in combination, and the standard cells are connected to each other by wiring. To obtain a digital signal processing circuit. In this case, the standard cell is constituted by a CMOS logic circuit having a circuit scale of about SSI or MSI, and signal terminals are provided only above and below it. Therefore, a wiring channel is provided in the height direction of the cell, and a wiring for connecting the standard cells is formed here.

The standard cells constitute an internal logic circuit, and input / output buffer cells constituting an input buffer and an output buffer as a semiconductor integrated circuit device are not usually provided with a logical function, and the logic modification thereof is performed. Are omitted in FIG. The input / output buffer (not shown) is generally higher than the standard cell, and is formed to have a larger size. In analog circuits and digital circuits, standard cells for memory circuits are
The cell type also has a different height from the logic standard cell and is prepared as a large standard cell.

In this embodiment, after the basic logic design is completed in the standard cell constituting the above-described logic circuit, the logic is corrected in advance based on the result of the subsequent circuit analysis and the like. Dummy cells are appropriately arranged. In the figure, a narrow hatched portion adjacent to the standard cell is a dummy cell. The dummy cell is configured by mounting a plurality of α cells, β cells, or γ cells configured by the pass transistor logic.

The connection of the input / output terminals to the dummy cell (PTL) is determined so that it can be connected by the uppermost wiring layer. For this reason, it can be used not only for making final logical corrections and changes, but also for making circuit changes based on the results of circuit analysis on a developed product. In other words, in order to perform logic debugging by verifying the circuit operation, the above-described connection to the PTL is performed using the uppermost wiring layer, and thus the logic modification to the logic output signal formed by the standard cell is performed. FIB (focused ion beam) wiring layer for PTL
It can be changed by technology.

In other words, by cutting the uppermost wiring layer and connecting the wiring to each other in the PTL prepared as a dummy cell by the FIB technique, the logical correction is performed on the standard cell, and the logical correction is performed. Confirmation can be performed. FIB like this
By incorporating logic debugging by technology, development and design of the standard cell type semiconductor integrated circuit device can be shortened. In the final product, the semiconductor integrated circuit device can be completed only by changing the wiring design of the uppermost layer, in other words, only by changing the wiring mask of the uppermost layer.

By combining the above-described dummy cell using PTL and the above-mentioned FIB technique, it is possible to obtain a semiconductor integrated circuit device of a standard cell type having a dummy cell capable of efficiently modifying the logic with a small circuit scale. it can.

In the building block type (or general cell type) shown in FIG. 2B, the height and width of the cell may differ from the source. Signal input terminals are provided on four sides of each cell. The standard cell of the building block type has a circuit size larger than that of the standard cell of the poly cell type described above, includes circuits up to about LSI, and includes, for example, a microprocessor as a standard cell.

In such a building block type semiconductor integrated circuit device as well, after the basic logic design is completed in a standard cell constituting the above logic circuit, the result of subsequent circuit analysis and the like is obtained. Dummy cells are appropriately arranged in advance in order to perform the logic correction based on. In the figure, a narrow hatched portion adjacent to each standard cell is a dummy cell. This dummy cell is composed of the α formed by the pass transistor logic.
A plurality of cells, β cells or γ cells are mounted.

In general-purpose circuit blocks such as the above-described circuit blocks such as a microprocessor or a memory,
There is little need to make that logical modification. Therefore, the dummy cell may be omitted for such a general-purpose circuit block. In other words, the part that performs the special operation as the custom LSI is realized by a logic circuit that constitutes the peripheral circuits of the microprocessor and the memory. The logic circuit is a standard cell having a small circuit scale, and each of the logic cells has its own unique function. This is because it is common to perform logical processing. Therefore, the logic modification or change is often performed by the logic change in the peripheral logic circuit portion. Therefore, a dummy cell is arranged adjacent to the standard cell corresponding to the SSI or MSI similarly to the above poly cell type. In practice, however, it can be handled.

Such a building block type semiconductor integrated circuit device also includes a dummy cell using the above-described PTL and a dummy cell capable of efficiently modifying the logic with a small circuit scale by combining the above-mentioned FIB technology. A semiconductor integrated circuit device using the standard cell method can be obtained.

The standard cell is constituted by a CMOS circuit. When a CMOS circuit is used as a standard cell as described above, existing circuit design resources can be effectively used. In other words, in the standard cell system, even when designing and manufacturing a full custom LSI, a circuit is designed by combining previously designed cells, and the cells can be used as is by an unspecified number of users. This is because they have been developed and standardized, and have a wealth of experience as standard cells.

The functions and effects obtained from the above embodiment are as follows. (1) A signal processing circuit for performing a desired digital signal processing by using a plurality of types of standard cells in which specific logic functions are designed in advance, and by designing the layout and wiring for connecting the standard cells. In a standard cell type semiconductor integrated circuit device to be realized, dummy cells used for logic correction are appropriately provided between the standard cells,
The transfer gate MOSFE is used as such a dummy cell.
By using a plurality of pass-transistor logics (PTLs) having one of the source-drain paths and the gate as an input and the other of the source-drain paths as an output at T, a single PTL circuit can realize various logic circuits. Since it can be realized, there is obtained an effect that a logical modification with a small circuit scale and a wide application range can be efficiently performed.

(2) A plurality of N-channel MOSFETs in which basic unit logics constituting the pass transistor logic are connected in series and in a multistage configuration, and the N-channel MOSFET is connected to an output portion of a circuit network including the N-channel MOSFETs. P-channel type MOSFET that compensates for level drop due to threshold voltage between gate and source of MOSFET
T, a first CMOS inverter circuit having an output terminal coupled to the gate of the P-channel type MOSFET and having the input of the signal of the output unit supplied thereto, and an output terminal of the first CMOS inverter circuit having the signal of the signal unit supplied thereto. By providing an output circuit composed of a second CMOS inverter circuit for transmitting an output signal from the CMOS, signal processing at the CMOS level is performed, so that the effect of reducing power consumption can be obtained.

(3) By forming a wiring layer for connecting to the MOSFET constituting the pass transistor logic of the dummy cell with the uppermost wiring layer, it is possible to verify the logic correction by the FIB technique in the development process, and to obtain a final product. Thus, a semiconductor integrated circuit device in which the above-described logic correction is performed can be obtained only by changing the wiring mask of the uppermost layer, and the effect of shortening the time for designing and manufacturing can be obtained.

(4) By using a CMOS circuit as the standard cell, it is possible to effectively use a wide variety of circuits as standard cells.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, only the CMOS inverter circuit may be arranged at the output part of the pass transistor logic. in this case,
Due to the above-mentioned level drop in the input high level of the CMOS inverter circuit, the P-channel type MOSF
ET is turned on weekly, and the current consumption of the CMOS inverter circuit increases. However, the number of places where the dummy cells are used is not so large, so there is no problem as a whole.

Then, the P-channel MOSFET
This is because the above current can be suppressed to a minimum if the size is reduced. The dummy cells appropriately provided between the standard cells are not always used, and the C cells provided in unused dummy cells are not always used.
If the wiring of the input terminal is connected to the MOS inverter circuit so that a low level is input, it is possible to prevent the above-described current from flowing there. The present invention can be widely used for a standard cell type semiconductor integrated circuit device.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a signal processing circuit for performing a desired digital signal processing is realized by using a plurality of types of standard cells in which specific logic functions are designed in advance, and designing the layout and wiring for connecting the standard cells. In a standard cell type semiconductor integrated circuit device, dummy cells used for logic correction are appropriately provided between the standard cells, and one of the source-drain paths in the transfer gate MOSFET and the gate are input as such dummy cells, A pass transistor logic (PT) having the other of the source-drain paths as the output side
By using a plurality of L), various logic circuits can be realized even with one PTL circuit, so that a small circuit scale can be used more efficiently and a wide range of logic correction is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a pass transistor logic constituting a dummy cell mounted on a standard cell type semiconductor integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the pass transistor logic constituting the dummy cell mounted on the standard cell type semiconductor integrated circuit device according to the present invention.

FIG. 3 is a circuit diagram for explaining a logic circuit that can be realized by the β cell shown in FIG. 2;

FIG. 4 is a circuit diagram showing still another embodiment of the pass transistor logic constituting the dummy cell mounted on the standard cell type semiconductor integrated circuit device according to the present invention.

FIG. 5 is a schematic block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.

[Explanation of symbols]

Q1 to Q14: MOSFET, EX: Exclusive OR circuit, AND: AND gate circuit, OR: OR gate circuit, NAND: NAND gate circuit, NOR: NOR gate circuit.

Claims (4)

[Claims] 1. A signal processing circuit for performing desired digital signal processing by using a plurality of types of standard cells in which specific logic functions are designed in advance, and arranging the standard cells and designing wiring for connecting the standard cells. In a standard cell type semiconductor integrated circuit device, a dummy cell used for correcting the logic of the standard cell is appropriately provided between the standard cells, and a pair of the dummy cells are arranged in parallel. One of the source-drain paths in the transfer gate MOSFET is used as the eleventh and second inputs, the gate is used as the third input to supply a complementary signal, and the other of the source-drain paths is commonly connected to obtain an output signal. It consists of a plurality of pass transistor logics including the basic unit logic The semiconductor integrated circuit device. 2. The pass transistor logic according to claim 1, wherein said basic unit logic is connected in series in a multistage configuration.
Channel MOSFET and such an N-channel M
A P-channel MOSFET, which is provided at an output of an OSFET circuit network and compensates for a level drop caused by a threshold voltage between the gate and the source of the N-channel MOSFET.
T, a first CMOS inverter circuit having an output terminal coupled to the gate of the P-channel type MOSFET and having the input of the signal of the output unit supplied thereto, and an output terminal of the first CMOS inverter circuit having the signal of the signal unit supplied thereto. 2. The semiconductor integrated circuit device according to claim 1, further comprising an output circuit including a second CMOS inverter circuit for transmitting an output signal from the second integrated circuit. 3. The semiconductor integrated circuit according to claim 1, wherein a wiring layer for connecting the dummy cell to a MOSFET constituting a pass transistor logic is formed by an uppermost wiring layer. Circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein said standard cell is constituted by a CMOS integrated circuit.