JPH11260923A - Semiconductor integrated circuit and its layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save a power by cutting leakage currents running in a non-used cell for correction before correction at the time of preliminarily arranging cells for correction so that circuit change can be easily attained in layout correction only after a wiring level in the layout of a semiconductor integrated circuit. SOLUTION: In an inverter cell for correction equipped with a P-type transistor 1 and an N-type transistor 2, power supply to sources 1a and 2a of the P type and N-type transistors 1 and 2 is operated only from a power line 15 before correction (when unused). Therefore, one part of the leak path of currents from the power line 15 through the source and drain of the P-type transistor 1 and the drain and source of the N-type transistor 2 to a ground line 16 is interrupted so that leakage currents running to the unused cell for correction can be completely cut, and the unnecessary power consumption of the semiconductor integrated circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a layout method thereof, and more particularly to an improvement of a circuit provided with an unused circuit (repair cell) which is originally unnecessary for a logic circuit for layout correction.

[0002]

2. Description of the Related Art In recent years, with the development of semiconductor process technology, the scale of circuits that can be mounted on a single semiconductor chip has been increasingly increased, and a multi-layer wiring technology of four or five wiring layers has been used. It is becoming.

In such a large-scale semiconductor integrated circuit, because of its large scale, it takes a very long time to verify the circuit operation at the time of design, and it is necessary to completely eliminate design errors before starting a manufacturing process. It has become very difficult.

In such a situation, a conventional semiconductor integrated circuit employs a configuration in which unused circuits which are not originally required for a logic circuit are previously included in a layout. By adopting such a configuration in advance, even if the logic circuit is changed, it is more likely that only the correction after the wiring level can be dealt with at the layout correction stage, and the correction after the correction in a short period of time. You can get chips. Recently, some automatic layout and wiring layout tools have a function of automatically arranging correction cells at the time of automatic layout and wiring using standard cells.

In such a repair cell, the input terminal is fixed to a power supply line or a ground line so that a leak current does not flow, the output terminal is opened, and the power supply is
For example, in the case of a CMOS circuit, the source of the P-type transistor is fixed to the power supply line, and the source of the N-type transistor is fixed to the ground line. When repairing, only the input and output are reconnected.

FIG. 7 is a diagram showing a layout of a correction inverter cell after a wiring level in a conventional semiconductor integrated circuit. In the figure, 51 is a gate electrode as an input terminal, 52 is a diffusion region of a P-type transistor, 53 is a diffusion region of an N-type transistor, 54 is an output wiring, 55 is a power supply line, and 56 is a ground line. Power supply to the P-type transistor is performed from a power supply line 55, and power supply to the N-type transistor is performed from a ground line 56. The drains of the two transistors are connected by the output wiring 54.

[0007]

However, in the above-described conventional semiconductor integrated circuit, in the inverter cell,
There is a path from the power supply line 55 to the ground line 56 through the P-type transistor and the N-type transistor, and there is a problem that a weak leak current flows through this path.

[0008] Current semiconductor integrated circuits tend to have higher and higher operating frequencies, and circuits of several hundred MHz have appeared.
In order to increase the operating speed of the transistor in response to this, it is necessary to provide such a characteristic that the operating current flowing through the transistor in the manufacturing process increases.
In a conventional semiconductor integrated circuit, when such characteristics are given, there arises a problem that the current value of the leak current also increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an unused repairing cell or repairing transistor so that logic can be corrected only by repairing after a wiring level. In the semiconductor integrated circuit provided with the above, the leakage current flowing through the repair cell or the repair transistor is completely cut to reduce the overall power consumption.

[0010]

In order to solve the above problems, the present invention employs a configuration in which a path from a power supply line to a ground line via a repair cell or a repair transistor is cut off.

Specifically, the semiconductor integrated circuit according to the first aspect of the present invention is a semiconductor integrated circuit including a plurality of correction transistors used for performing a circuit correction by a change after a wiring level. Is characterized in that the power supply node is unifiedly connected to only one of the power supply line and the ground line.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A semiconductor integrated circuit having a cell for correction used for performing circuit correction by a change after a wiring level,
The correction cell includes a P-type transistor and an N-type transistor, and the P-type transistor and the N-type transistor have the same potential applied to a power supply node.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the potential is a power supply potential or a ground potential.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A semiconductor integrated circuit having a cell for correction used for performing circuit correction by a change after a wiring level,
The correction cell includes a P-type transistor and an N-type transistor, and an output node of the P-type transistor and an output node of the N-type transistor are not connected.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit of the fourth aspect, a power supply node of the P-type transistor is connected to a power supply line, and a power supply node of the N-type transistor is connected to a ground line. Is connected to the terminal.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
A semiconductor integrated circuit having a correction transistor used for performing circuit correction by a change after a wiring level, wherein a part of a path from a power supply line to a ground line via the correction transistor is partially lost due to lack of wiring. It is characterized by being blocked.

According to a seventh aspect of the present invention, there is provided a layout method for a semiconductor integrated circuit, which is used for performing a circuit correction by a change after a wiring level, and has a repair cell including a P-type transistor and an N-type transistor. A method of laying out a semiconductor integrated circuit, wherein in the repair cell, a power supply node of the P-type transistor and a predetermined relay point are connected by a first wiring element, and a power supply node of the N-type transistor is connected to a ground line. Are connected by a second wiring element, and the relay point and the ground line are connected by a third wiring element.

According to an eighth aspect of the present invention, in the layout method of the semiconductor integrated circuit according to the seventh aspect, the third wiring element is cut when the circuit is corrected, and the relay point and the power supply line are connected to the fourth wiring element. The connection is characterized by:

According to a ninth aspect of the present invention, there is provided a layout method for a semiconductor integrated circuit, which is used for performing a circuit correction by a change after a wiring level, and has a correction cell including a P-type transistor and an N-type transistor. A method of laying out a semiconductor integrated circuit, wherein in the repair cell, a power supply node of the P-type transistor and a power supply line are connected by a first wiring element, and a power supply node of the N-type transistor is connected to a predetermined relay point. Are connected by a second wiring element, and the relay point and the power supply line are connected by a third wiring element.

According to a tenth aspect of the present invention, in the layout method of the semiconductor integrated circuit according to the ninth aspect, when the circuit is modified, the third wiring element is cut, and the relay point and the ground line are connected to the fourth wiring element. The connection is characterized by:

According to an eleventh aspect of the present invention, in the semiconductor integrated circuit layout method according to the seventh or ninth aspect, the first wiring element and the second wiring element are included in a first wiring layer, The third wiring element is included in a second wiring layer above the first wiring layer.

According to a twelfth aspect of the present invention, in the layout method of the semiconductor integrated circuit according to the eighth or tenth aspect, the first wiring element and the second wiring element are the first wiring element.
The third wiring element and the fourth wiring element are included in a wiring layer, and the third wiring element and the fourth wiring element are included in a second wiring layer above the first wiring layer.

The layout method of a semiconductor integrated circuit according to the present invention is used for correcting a circuit by a change after a wiring level, and has a repair cell composed of a P-type transistor and an N-type transistor. A method of laying out a semiconductor integrated circuit, wherein in the repair cell, a power supply node of the P-type transistor and a power supply line are connected by a first wiring element, and a power supply node of the N-type transistor is connected to a ground line. A second wiring element, an output node of the P-type transistor and a first relay point are connected by a third wiring element, and an output node of the N-type transistor and a second relay point are connected by a fourth wiring element The third wiring element and the fourth wiring element are not connected.

The invention according to claim 14 is the invention according to claim 13.
In the layout method of a semiconductor integrated circuit described above, the first relay point and the second relay point are connected by a fifth wiring element at the time of circuit correction.

According to a fifteenth aspect of the present invention, the thirteenth aspect is provided.
In the layout method of a semiconductor integrated circuit described in the above, the output node of the P-type transistor, the first relay point, the second relay point, and the output node of the N-type transistor are arranged on the same straight line in this order. Is characterized in that:

[0026] According to a sixteenth aspect of the present invention, there is provided the above-mentioned fourteenth aspect.
In the layout method for a semiconductor integrated circuit described above, the third wiring element, the fourth wiring element, and the fifth wiring element are integrated by circuit modification.

According to the present invention, the leak path from the power supply line to the ground line via the repair transistor or the repair cell in the unused repair transistor or repair cell is provided. Are cut off, the weak leakage current flowing through them is completely cut, and unnecessary power consumption of the semiconductor integrated circuit is effectively reduced.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a layout diagram of a repair inverter cell portion in a semiconductor integrated circuit according to a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a P-type transistor (correction transistor), and 2 denotes an N-type transistor (correction transistor). Both transistors 1 and 2 constitute a correction cell. Reference numeral 12 denotes a diffusion region of the P-type transistor 1, reference numeral 13 denotes a diffusion region of the N-type transistor 2, and reference numeral 15 denotes a power supply line disposed in a first metal wiring layer.
Reference numeral 6 denotes a ground line arranged in the first wiring layer.

A power supply node (source) 1a of the P-type transistor 1 is connected to a predetermined relay point 5 by a first wiring element 4 of a first metal wiring layer. The power supply node 2a of the N-type transistor 2 is connected to a ground line 16 by a second wiring element 6 of the first wiring layer. The ground line 16 is connected to the relay point 5 by a third wiring element 7 of a second metal wiring layer above the first wiring layer.
Further, the drains (output nodes) 1b and 2b of the P-type and N-type transistors 1 and 2 are connected by an output wiring 14 arranged in a first wiring layer. In addition, the common gate electrode 11 of the P-type and N-type transistors 1 and 2 is connected to the power supply line 15 via the wiring element 8 of the first wiring layer and the wiring element 9 of the second wiring layer. This gate electrode 11 may be connected to ground line 16 instead of power supply line 15.

In the drawings, the symbol □ indicates a contact for connecting the electrodes of the P-type and N-type transistors to the wiring of the first wiring layer, and the hatched part in the symbol □ indicates the first wiring. This is a contact for connecting the wiring in the layer and the wiring in the second wiring layer.

In the present embodiment, as shown in FIG.
The power supply to the P-type transistor 1 is performed from the ground line 16 in the same manner as the power supply to the N-type transistor 2. As a result, a wiring connecting the power supply line 15 to the power supply node 1a of the P-type transistor 1 is lost, and the missing portion causes the power supply line 15 in the repair inverter cell to be grounded via both transistors 1, 2. Since a part of the path leading to the line 16 is cut off, the leakage current flowing through this path is cut.

FIG. 2 shows a layout result after the layout of the repair cell is corrected when the circuit is corrected after the wiring level using the repair cell of FIG.

That is, as can be seen by comparing with the layout before correction shown in FIG. 1, the third wiring element 7 is cut, and then the relay point 5 and the power supply line 15 are connected to the second wiring layer. The power is supplied to the P-type transistor 1 from the power supply line 15 by being connected by the fourth wiring element 10. Further, the wiring element 9 is cut, and thereafter, using the wiring element 17 of the second wiring layer, the wiring element 8 is connected to a predetermined signal terminal, and a predetermined signal is input to the gate electrode 8. As described above, the intended circuit operation as an inverter can be performed by using only the addition of the wiring elements 10 and 17 of the second wiring layer.

(Modification of First Embodiment) FIG. 3 shows a modification of the first embodiment. In this modification, the power supply to the P-type and N-type transistors 1 and 2 is
It is intended to be performed from.

That is, the power supply node (source) 1a of the P-type transistor 1 is connected to the power supply line 15 by the first wiring element 20 in the first wiring layer. The power supply node 2 a of the N-type transistor 2 is connected to a predetermined relay point 22 by a second wiring element 21. Further, the relay point 2
2 is connected to the power supply line 15 by the third wiring element 23 of the second wiring layer.

Therefore, in this modification, the ground line 16
, The wiring connected to the power supply node 2a of the N-type transistor 2 is missing.
Since a part of the path leading to the ground line 16 through 2 is cut off, the leakage current flowing through this path is cut.

FIG. 4 shows a layout result after the layout of the repair cell is corrected in the case where the circuit is repaired after the wiring level using the repair cell of FIG.

That is, as can be seen by comparing with the layout before correction shown in FIG.
Thereafter, the relay point 22 and the ground line 16 are connected by the fourth wiring element 24 of the second wiring layer, and the ground line 16
Power is supplied to the type transistor 2. Since the change of the wiring for the gate electrode 8 is the same as that of the first embodiment, the description is omitted.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described. In the present embodiment, the path of the leak current between the P-type transistor 1 and the N-type transistor 2 is cut off.

FIG. 5 is a layout diagram of a correction inverter cell portion in a semiconductor integrated circuit according to a second embodiment of the present invention. In FIG. 1, a power supply node (source) 1a of the P-type transistor 1 is connected to a power supply line 15 by a first wiring element 50 in a first wiring layer. The power supply node 2a of the N-type transistor 2 is connected to the first
It is connected to the ground line 16 by the second wiring element 51 of the wiring layer. The drain (output node) 1b of the P-type transistor 1 is connected to a first relay point 53 by a third wiring element 52 of a first wiring layer, and the drain 2b of the N-type transistor 2 is connected to a first wiring layer. Is connected to the second relay point 55 by the fourth wiring element 54. The third wiring element 52 and the fourth wiring element 54 are not connected to each other. The drain 1b of the P-type transistor 1, the first relay point 53, the second relay point 55, and the drain 2b of the N-type transistor 2 are arranged on the same straight line in this order. Other configurations are the same as those in FIG. 1 of the first embodiment, and therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted.

As can be seen from FIG. 5, power supply to P-type transistor 1 is performed from power supply line 15 and power supply to N-type transistor 2 is performed from ground line 16. However, since the drains of the P-type and N-type transistors 1 and 2 are not connected to each other, there is no path from the power supply line 15 to the ground line 16 via both transistors 1 and 2 as a whole cell, and the leakage current is completely cut off. Have been.

FIG. 6 shows a layout result after the layout of the repair cell is corrected when the circuit is repaired after the wiring level using the repair cell of FIG. As can be seen by comparing with the layout before the modification in FIG. 5, the third wiring element 52 and the fourth wiring element 54
These are connected using the fifth wiring element 56 of the wiring layer,
One wiring element is integrated. Accordingly, with respect to the connection between the drains of the transistors 1 and 2, it is possible to perform the circuit operation as an inverter only by adding the wiring of the first wiring layer.

In the above description, an inverter cell is used as a repairing cell. However, the present invention is not limited to this, and it is needless to say that various cells such as an AND cell and an OR cell may be used. It is.

[0046]

As described above, according to the first to sixteenth aspects of the present invention, in a semiconductor integrated circuit including an unused repair transistor or repair cell and a layout method thereof, an unused repair transistor or repair cell is used. It is possible to completely cut a weak leak current flowing through the repair transistor or the repair cell, and to reduce power consumption of the entire semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a repair inverter cell of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a layout diagram after correction of the correction inverter cell shown in FIG. 1 after a wiring level;

FIG. 3 is a layout diagram of a correction inverter cell of a semiconductor integrated circuit according to a modification of the first embodiment of the present invention.

FIG. 4 is a layout diagram after correction of the correction inverter cell shown in FIG. 3 after a wiring level;

FIG. 5 is a layout diagram of a correction inverter cell of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is a layout diagram after correction of the correction inverter cell shown in FIG. 5 after the wiring level.

FIG. 7 is a layout diagram of a conventional inverter cell for correction of a semiconductor integrated circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 P-type transistor (correction transistor) 2 N-type transistor (correction transistor) 1a, 2a Source (power supply node) 1b, 2b Drain (output node) 3 Correction cell 4, 20, 50 First wiring element 5, 22 relay point 6, 21, 51 second wiring element 7, 23, 52 third wiring element 10, 24, 54 fourth wiring element 11 gate electrode 14 output wiring 15 power supply line 16 ground line 53 first relay point 54 second Relay point 56 fourth wiring element

Claims (16)

[Claims] 1. A semiconductor integrated circuit having a plurality of correction transistors used for performing a circuit correction by a change after a wiring level, wherein the plurality of correction transistors have a power supply node connected to a power supply line and a ground. A semiconductor integrated circuit, which is unifiedly connected to only one of the lines. 2. A semiconductor integrated circuit having a repair cell used for performing a circuit repair by a change after a wiring level, wherein the repair cell includes a P-type transistor and an N-type transistor, A semiconductor integrated circuit, wherein the P-type transistor and the N-type transistor have the same potential applied to a power supply node. 3. The semiconductor integrated circuit according to claim 2, wherein said potential is a power supply potential or a ground potential. 4. A semiconductor integrated circuit provided with a repair cell used for performing a circuit repair by a change after a wiring level, wherein the repair cell includes a P-type transistor and an N-type transistor, A semiconductor integrated circuit, wherein an output node of the P-type transistor and an output node of the N-type transistor are not connected. 5. The semiconductor integrated circuit according to claim 4, wherein a power supply node of said P-type transistor is connected to a power supply line, and a power supply node of said N-type transistor is connected to a ground line. circuit. 6. A semiconductor integrated circuit having a correction transistor used for correcting a circuit by a change after a wiring level, wherein a part of a path from a power supply line to a ground line via the correction transistor is provided. A semiconductor integrated circuit characterized by being interrupted by a lack of wiring. 7. A layout method for a semiconductor integrated circuit having a repair cell including a P-type transistor and an N-type transistor, which is used for performing a circuit repair by a change after a wiring level. In the cell, a power supply node of the P-type transistor and a predetermined relay point are connected by a first wiring element; a power supply node of the N-type transistor and a ground line are connected by a second wiring element; And a ground line connected by a third wiring element. 8. The layout method of a semiconductor integrated circuit according to claim 7, wherein the third wiring element is cut off at the time of circuit correction, and the relay point and the power supply line are connected by a fourth wiring element. 9. A layout method for a semiconductor integrated circuit having a repair cell including a P-type transistor and an N-type transistor, which is used for performing a circuit repair by a change after a wiring level. In the cell, a power supply node of the P-type transistor and a power supply line are connected by a first wiring element; a power supply node of the N-type transistor and a predetermined relay point are connected by a second wiring element; And a power supply line connected by a third wiring element. 10. The layout method for a semiconductor integrated circuit according to claim 9, wherein the third wiring element is cut off at the time of circuit correction, and the relay point and a ground line are connected by a fourth wiring element. 11. The method according to claim 11, wherein the first wiring element and the second wiring element are included in a first wiring layer, and the third wiring element is included in a second wiring layer above the first wiring layer. 10. The layout method for a semiconductor integrated circuit according to claim 7, wherein: 12. The first wiring element and the second wiring element are included in a first wiring layer, and the third wiring element and the fourth wiring element are second wirings higher than the first wiring layer. 11. The layout method for a semiconductor integrated circuit according to claim 8, wherein the layout method is included in a layer. 13. A layout method for a semiconductor integrated circuit having a repair cell including a P-type transistor and an N-type transistor, which is used for performing a circuit repair by a change after a wiring level. In the cell, a power supply node of the P-type transistor and a power supply line are connected by a first wiring element; a power supply node of the N-type transistor and a ground line are connected by a second wiring element; An output node and a first relay point are connected by a third wiring element, an output node of the N-type transistor and a second relay point are connected by a fourth wiring element, and the third wiring element and the fourth wiring element are connected to each other. Is not connected, a layout method of a semiconductor integrated circuit. 14. The layout method of a semiconductor integrated circuit according to claim 13, wherein said first relay point and said second relay point are connected by a fifth wiring element at the time of circuit correction. 15. The output node of the P-type transistor, the first relay point, the second relay point, and the output node of the N-type transistor are on the same straight line in this order. 14. The layout method for a semiconductor integrated circuit according to claim 13, wherein: 16. The layout method for a semiconductor integrated circuit according to claim 14, wherein said third wiring element, said fourth wiring element, and said fifth wiring element are integrated by circuit modification.