JPH10247850A - Frequency-divider circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit configuration area with the addition of a flip-flop by adopting the configuration that one flip-flop is not added to a frequency divider of a modulator prescaler, in order to provide a frequency division number of 1/(k+1) to the modular prescaler. SOLUTION: This circuit is provided with a modular prescaler 11, having a frequency division function operated at a fundamental frequency division number 1/k in the 1st mode and at a fundamental frequency division number 1/(k-1) in the 2nd mode, a swallow counter 2 whose count is Nx and a program counter 3 whose count is Np. The frequency division number in the 2nd mode is selected smaller than a fundamental frequency division number in the 1st mode, so as to simplify the circuit configuration of the modular prescaler 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider suitable for use in, for example, a frequency synthesizer of a mobile communication device.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional frequency dividing circuit. This frequency dividing circuit is used in, for example, a frequency synthesizer in mobile communication, and has a frequency dividing function operating at a frequency dividing number 1 / (k + 1) and a basic frequency dividing number of 1.
/ K, a modulo prescaler 1 having a frequency dividing function, a swallow counter 2 having a count of Nx, and a program counter 3 having a count of Np, and initially operating at a frequency of 1 / (k + 1). When the swallow counter 2 counts Nx pulse outputs of the modulus prescaler 1, the swallow counter 2 outputs an output M. The output M is inverted by the inverter circuit 4 and input to the AND circuit 5. , The gate of the AND circuit 5 is closed. The output M is supplied to the modulus prescaler 1 to operate the modulus prescaler 1 at the basic frequency division number 1 / k until the program counter counts Np-Nx pulse outputs of the modulus prescaler 1. Then, the swallow counter 2 and the program counter 3 are reset and the same operation is repeated.

The overall dividing ratio N of this dividing circuit is k (Np
+ Nx), the value Nx is set as the lower bit in the swallow counter 2, and the value Np is set as the upper bit in the program counter 3, and the overall frequency division ratio N is determined. Then, while making Np variable, from 0 to (k
By selecting the value up to -1) as the value Nx, the whole frequency division number 1 / N can be changed with a continuous integer value, and operated as a variable frequency dividing circuit.

In such a frequency dividing circuit, CMOS or the like can be used as a logic circuit element. In the modulus prescaler 1, the basic frequency division number 1 / k and the frequency division number 1 / k are used.
In order to obtain (k + 1), one more flip-flop is added to the frequency divider having the basic frequency division number 1 / k. FIG. 5 is a logic circuit diagram showing a configuration of the frequency divider of such a modulus prescaler 1, in which one flip-flop 8 is added in addition to the flip-flops 6 and 7.

[0005]

Since the conventional frequency dividing circuit is constructed as described above, in the modulus prescaler 1, the frequency dividing number 1 / (k) is larger than the basic frequency dividing number 1 / k.
One flip-flop is added to the divider of the modulus prescaler 1 to obtain +1). For this reason, there is a problem that a circuit configuration area is required for the addition of the flip-flop.

SUMMARY OF THE INVENTION An object of the present invention is to provide a frequency dividing circuit that can reduce the circuit scale and fix the circuit current consumption by fixing the frequency dividing number.

[0007]

In order to achieve the above object, the present invention provides a modulus prescaler having a frequency dividing function which operates in a first mode and a second mode, a swallow counter having a count number of Nx, and a count number. Comprises a Np program counter, and when the swallow counter counts Nx pulse outputs of the modulus prescaler operating in the first mode, the program counter outputs Np-Nx pulse outputs of the modulus prescaler. After the modulus prescaler operates in the second mode until counting, in a frequency divider circuit that repeats the operation of resetting the swallow counter and the program counter, the frequency division number of the modulus prescaler in the first mode is Modulus prescaler provided Basic division number 1 / k of the frequency divider, the frequency division number of the second mode of the modulus prescaler, wherein the the basic divisor smaller than 1 / (k-1).

In the frequency dividing circuit of the present invention, the frequency dividing number in the first mode of the modulus prescaler is determined by the basic frequency dividing number 1 / k of the frequency divider provided in the modulus prescaler and the frequency dividing number in the second mode. A frequency division number 1 smaller than the basic frequency division number of the frequency divider
/ (K-1) to simplify the circuit configuration of the modulus prescaler, reduce the circuit scale as a frequency dividing circuit, and further suppress current consumption.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a frequency divider according to the present invention will be described below. FIG. 1 is a block diagram showing an example of a frequency dividing circuit according to the present invention. In FIG. 1,
The same elements as those of the frequency dividing circuit shown in FIG. The frequency dividing circuit has a frequency dividing function that operates at a basic mode of 1 / k, which is a first mode, and a frequency dividing function that operates at a frequency of 1 / (k-1), which is a second mode. And a swallow counter 2 whose count number is Nx, and a program counter 3 whose count number is Np. The modulus prescaler 11 includes a frequency divider having a frequency dividing function of the first mode and the second mode. FIG. 2 is a logic circuit diagram showing a configuration of the frequency divider. The frequency divider includes a flip-flop 12, a flip-flop 13, an AND circuit 15, and a NOR circuit 1.
Four.

In this frequency dividing circuit, first, the basic frequency dividing number 1 /
k, the swallow counter 2 outputs the pulse output of the modulus prescaler 11 operating in the first mode
After counting x, the swallow counter 2 outputs an output M. When the output M is inverted by the inverter circuit 4 and input to the AND circuit 5, the gate of the AND circuit 5 is closed. The output M of the swallow counter 2 is supplied to the modulus prescaler 11 and the program counter 3 outputs the pulse output of the modulus prescaler 11 to Np.
-Modulus prescaler 11 until count Nx
Are operated in the second mode with the frequency division number 1 / (k-1).
When the program counter 3 counts Np-Nx pulse outputs of the modulus prescaler 11, the swallow counter 2 and the program counter 3 are reset, and thereafter the same operation is repeated.

The overall dividing value N of this dividing circuit is k · (N
p−Nx), the value Nx is set as the lower bit in the swallow counter 2, the value Np is set as the upper bit in the program counter 3, and the entire frequency division value 1
/ N is determined. However, since Nx is subtracted from k · Np, it is not easy to change the frequency division number 1 / N of the entire frequency dividing circuit by a continuous integer value and operate as a variable frequency dividing circuit. There is no problem when the frequency division value 1 / N is fixed and used.

The circuit configuration of the frequency divider provided in the modulus prescaler 11 shown in FIG. 2 has one less flip-flop than the circuit configuration of the frequency divider provided in the conventional modulus prescaler 1 shown in FIG. In addition, the NOR circuit has been changed to an AND circuit.

When these logic circuits are constituted by CMOS, the operation speed is slow and a high-speed operation is required. Therefore, bipolar CMOS is often used. FIG. 3 is a diagram illustrating a NOR circuit constituting the frequency divider, a composite circuit of an AND circuit and a NOR circuit,
FIG. 4 is a circuit diagram showing an internal configuration when a flip-flop is configured by bipolar CMOS. When the frequency divider of the modulus prescaler 11 is constituted by such a bipolar CMOS, one flip-flop is reduced, which is advantageous in terms of a circuit configuration area and further suppresses current consumption. Further, while the frequency divider provided in the conventional modulus prescaler 1 uses two NOR circuits, the modulus prescaler 11 of the present embodiment is used.
Is provided with one composite circuit of an AND circuit and a NOR circuit. A comparison between (a) and (b) of FIG. 3 shows that a conventional NOR circuit using two NOR circuits is used. Obviously, the frequency divider is disadvantageous in terms of the circuit configuration area.

As described above, in the frequency dividing circuit of the present embodiment, first, the modulus prescaler 11 operates in the first mode of the basic frequency division number 1 / k, and outputs the pulse output of the modulus prescaler 11 to the swallow counter. 2 is Nx
After counting, the modulus prescaler 11 counts the number of divisions 1 / (k) until the program counter 3 counts Np−Nx pulse outputs of the modulus prescaler 11.
-1) It operates in the second mode. When the program counter 3 counts Np-Nx pulse outputs of the modulus prescaler 11, the swallow counter 2 and the program counter 3 are reset, and the program counter 3 counts Np pulse outputs of the modulus prescaler 11 once. Is obtained. The overall frequency division value is k · (Np−Nx), but the frequency division number of the second mode of the modulus prescaler 11 is 1 / (k−1) which is smaller than the basic frequency division number 1 / k. , The frequency divider provided in the modulus prescaler 11 includes one flip-flop for realizing the second mode as in the prior art.
There is no need to add one. Therefore, the circuit configuration including the circuit configuration area of the flip-flop is simplified as compared with the conventional frequency divider, the circuit configuration area is reduced, and power consumption can be suppressed.

[0015]

As described above, in the frequency dividing circuit of the present invention, the circuit configuration of the modulus prescaler can be simplified, so that the space required for the entire circuit configuration of the frequency dividing circuit can be reduced and the power consumption of the circuit can be reduced. There is an effect that can be done. In particular, when the circuit configuration for realizing the frequency dividing function of the first mode and the second mode of the modulus prescaler is constituted by a flip-flop, an AND operation circuit and a NOR operation circuit are constituted by bipolar circuit elements, Since the circuit configuration of the modulus prescaler can be simplified, including reducing the number of circuits by one, the space required for the circuit configuration of the entire frequency dividing circuit can be reduced, and the circuit power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a frequency dividing circuit according to the present invention.

FIG. 2 is a logic circuit diagram showing a circuit configuration of a frequency divider provided in a modulus prescaler in one example of the frequency dividing circuit of the present invention.

FIG. 3 is a circuit showing an internal configuration when a frequency divider provided in a modulus prescaler in an example of a frequency dividing circuit according to the present invention is configured by a NOR circuit, a composite circuit of an AND circuit and a NOR circuit, and a flip-flop is configured by a bipolar CMOS; FIG.

FIG. 4 is a block diagram showing a conventional frequency dividing circuit.

FIG. 5 is a logic circuit diagram showing a circuit configuration of a frequency divider provided in a modulus prescaler in a conventional frequency dividing circuit.

[Explanation of symbols]

2 ... Swallow counter, 3 ... Program counter,
11: modulus prescaler, 12: first flip-flop, 13: second flip-flop, 14
... NOR operation circuit, and 15 AND operation circuit.

Claims (5)

[Claims] 1. A modulus prescaler having a frequency dividing function that operates in a first mode and a second mode, a swallow counter having a count of Nx, and a count of Np
When the swallow counter counts Nx pulse outputs of the modulus prescaler operating in the first mode, the program counter counts Np-Nx pulse outputs of the modulus prescaler. A frequency dividing circuit that repeats an operation of resetting the swallow counter and the program counter after the modulus prescaler operates in the second mode until the modulus prescaler operates in the second mode. And 1 / k of the basic frequency divider of the frequency divider provided by the modulus prescaler.
Is smaller than the basic division number by 1 / (k
A frequency dividing circuit according to (1). 2. The frequency dividing circuit according to claim 1, wherein the entire frequency dividing ratio is not variable but fixed. 3. The count number Nx of the swallow counter
3. The frequency dividing circuit according to claim 2, wherein the whole frequency dividing ratio is fixed by setting the count number Np of said program counter to a fixed value. 4. The frequency divider of the modulus prescaler includes a first flip-flop, a second flip-flop that takes in a non-inverted output of the first flip-flop as data, and a non-inverted signal of the first flip-flop. A logical product circuit for performing a logical product operation of the inverted output and the output of the swallow counter; and a logical sum negative operation result of the logical product of the output of the logical product circuit and the non-inverted output of the second flip-flop, Is output to the first flip-flop as data. The modulus prescaler is configured to output a basic divisor “1” of the frequency divider when the output of the swallow counter is a logical value “0”. / 4 "in the first mode, and when the output of the swallow counter is a logical value" 1 ", it is smaller than the basic frequency division number" 1/4 ". 4. The frequency dividing circuit according to claim 1, further comprising a frequency dividing function that operates in the second mode with a frequency division number of “１ ／”. 5. 5. The first flip-flop, the second flip-flop,
5. The frequency dividing circuit according to claim 4, wherein said flip-flop, said AND operation circuit, and said NOR operation circuit are constituted by bipolar circuit elements.