JPH10242265A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten the main face of a semiconductor substrate which is large in roughness and fineness of the polishing place. SOLUTION: A pad oxide film 2 is made on the main face of the semiconductor substrate 1 consisting of silicon, and then a polishing stop film 3 consisting of material lower in polishing speed than the film 2 is made on the pad oxide film 2, and then a groove 4 is made by photolithography etching, and further a film 8 (CVD oxide film) as an insulating film for element isolation is made thick to fill up the groove 4 on the main face of the semiconductor substrate 1. Next, an etching mask 12 is made, using a mask which has an inverted exposure pattern which becomes reverse to the exposure pattern of a mask for photolithography at formation of an active region 10. Next, the swell 9 of the CVD oxide film 8 at the aperture part 11 of the etching mask 12 is etched by specified thickness to lessen the remaining projection 13, and then chemicomechanical polishing processing is performed to flatten the main face of the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly, to a method for manufacturing a semiconductor integrated circuit device using a CMP (Chemic
Al Mechanical Polishing), for example, by embedding an insulating film (insulating film for element isolation) such as a CVD (vapor phase chemical growth) oxide film in a trench formed on the surface of a semiconductor substrate. The present invention relates to a technique which is effective when applied to a technique for forming an isolation structure.

[0002]

2. Description of the Related Art As one of techniques for flattening the surface of a semiconductor substrate in manufacturing a semiconductor integrated circuit device, a CMP technique is known.

[0003] The CMP technique is described in, for example, "Electronic Materials", May 1996, p. The document summarizes, "In the manufacture of semiconductor devices, the minimum processing dimension is 0.35 μm for next-generation devices, and eventually 0.25 μm, and in these cases, there is a step on the device surface. Since a stepper cannot provide sufficient resolution, global flattening is required to eliminate surface irregularities and steps. "

[0004] Further, in the document, isolation is formed as an application to an insulating film, a metal lower layer insulating film is formed, a metal interlayer insulating film is formed, and as a metal film, a plug is formed, a wiring is formed, and a wiring and a plug are simultaneously formed. Are listed.

[0005]

Conventionally, flattening by CMP has a problem that when the step pattern on the surface (main surface) of the semiconductor substrate is uneven, the polishing rate is different and flattening is deteriorated (dishing effect). There is.

In order to avoid this problem, a method in which a resist is applied to the surface of a semiconductor substrate, the whole surface is etched back by a dry etching technique, a portion of the CVD oxide film on the protruding portion is preliminarily cut, and then a CMP process is performed (Japanese Patent Laid-Open No. -1481
No. 55, JP-A-6-61342) and a method in which a dummy pattern is formed simultaneously with a device pattern in advance so that unevenness of the device pattern does not occur (US Pat. No. 5,292,689).
No.) is known.

However, in the former case, the resist film thickness tends to be non-uniform depending on the pattern density and the area, and there is a problem in the uniformity of in-plane flatness after dry etching.

In the latter case, the parasitic capacitance increases and the parasitic MOS increases.
FET (Metal Oxide Semiconductor Field-Effect-Tra
There are problems such as adverse effects such as nsistor), complexity in layout design, and restrictions.

An object of the present invention is to achieve a planarization of a semiconductor substrate surface in a chemical mechanical polishing process in the manufacture of a semiconductor integrated circuit device.

[0010] Another object of the present invention is to planarize the surface of a semiconductor substrate in a semiconductor substrate in which the density of polished portions is large.

Another object of the present invention is to provide a technique for performing flattening by chemical mechanical polishing after correcting the density of polished portions in flattening by applying chemical mechanical polishing to isolation technology. It is in.

[0012] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) A method of manufacturing a semiconductor integrated circuit device in which a film formed on a main surface of a semiconductor substrate is chemically and mechanically polished to flatten the main surface of the semiconductor substrate, wherein a film is selectively formed on the film. After forming the etching mask, the raised portion of the film is etched by a predetermined thickness using the etching mask, the etching mask is removed, and the film is polished.

As an example, after a pad oxide film is formed on the main surface of a semiconductor substrate (silicon substrate), a polishing stop film (Si) made of a material whose polishing rate is lower than the polishing rate of the film is formed on the pad oxide film. ₃ N ₄ film) is formed, then the groove by photolithography and etching (trench)
Is formed on the main surface of the semiconductor substrate, and a film (CVD oxide film) as an insulating film for element isolation (isolation) is formed thickly so as to fill the trench.

The pattern of the etching mask is an exposure pattern obtained by inverting the exposure pattern of the photolithographic mask when forming the groove.

Next, the protruding portion of the CVD oxide film at the opening of the etching mask is etched (for example, wet-etched) to reduce the remaining protruding portion.
After the density of the polished portion is eliminated and uniformized, the main surface of the semiconductor substrate is planarized by performing a chemical mechanical polishing process.

When the opening of the etching mask is small, the etchant used in the wet etching may contain a surfactant which acts so that the etching liquid easily enters the opening.

The pattern of the opening of the etching mask may be different from the corresponding pattern of the groove forming mask.

(2) In the configuration of the means (1), the etching is performed by anisotropic dry etching and subsequent wet etching, and then the semiconductor substrate is planarized by chemical mechanical polishing.

According to the above-mentioned means (1), the CVD oxide film (insulating insulating film for element isolation) which deviates from the trench is raised, but the raised portion is mostly etched by the etching using the etching mask. Since a predetermined thickness is removed while leaving the portion, the difference in the density of the raised portion in each region of the semiconductor substrate main surface is reduced, and uniform polishing over the entire semiconductor substrate main surface is possible in the subsequent chemical mechanical polishing process. Therefore, the flatness of the main surface of the semiconductor substrate is improved.

In chemical mechanical polishing, since the polishing stop film serves as a stopper, the polishing end height is constant over the entire main surface of the semiconductor substrate, and the main surface of the semiconductor substrate can be flattened.

Further, since the etching is performed by wet etching, isotropic etching can be performed with an etching solution that has entered the opening of the etching mask, and the residual swelling portion is reduced in volume. Therefore, the planarization effect by the chemical mechanical polishing process is higher.

When wet etching is performed using an etching solution containing a surfactant, the etching solution can enter the opening even if the opening of the etching mask is small. The flattening of the main surface of the semiconductor substrate by the processing is ensured.

Further, since the pattern of the etching mask is a pattern obtained by inverting the exposure pattern of the photolithographic mask at the time of forming the groove, the formation of the etching mask is facilitated.

According to the means (2), after the raised portion of the insulating film for element isolation is reduced to some extent by the first anisotropic dry etching, the entire raised portion is wet-etched with a high isotropic etching effect. Is etched again, the remaining area of the raised portion is reduced, and the flattening accuracy in the subsequent chemical mechanical polishing is further improved.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIGS. 1 to 14 relate to a method of manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention.

In the first embodiment, the surface (main surface) of the semiconductor substrate is flattened by applying a chemical mechanical polishing process (CMP process) to the isolation technique, and then surrounded by an insulating film for element isolation. MO in one active area (active area)
An example of forming an SFET will be described.

As shown in the flow chart of FIG. 2, the semiconductor substrate main surface is planarized by preparing a semiconductor substrate (Step 101), forming a pad oxide film (Step 102), forming a polishing stop film (Step 103), and forming a trench. Formation (Step 104), buried insulating film formation (Step 1)
05), etching mask formation (step 106), etching (step 107), CMP processing (step 1)
08), and the removal of the polishing stop film (step 109).

First, as shown in FIG. 3, after preparing a semiconductor substrate (silicon substrate) 1 made of, for example, p-type single crystal silicon (step 101), pads are formed on the main surface (upper surface) of the semiconductor substrate 1. An oxide film 2 and a polishing stop film 3 are sequentially formed (Step 102 and Step 10).
3).

The pad oxide film 2 is, for example, 10 to 5
It is a silicon oxide film (SiO ₂ film) having a thickness of about 0 nm.
Further, the polishing stop film 3 is, for example, 100 to 15
It is a silicon nitride film (Si ₃ N ₄ film) of about 0 nm.

[0033] varies depending slurry used in the CMP process by a slurry that is commonly used, the the Si ₃ N ₄ film is slow 2-3 times polishing rate compared to the SiO ₂ film, a SiO ₂ film When CMP processing is performed,
The Si ₃ N ₄ film sufficiently functions as a polishing stop film, contributes to making the polishing height of the entire region of the semiconductor substrate 1 constant, and enables the main surface of the semiconductor substrate 1 to be flattened.

Next, as shown in FIG. 4, a trench (trench) 4 is formed by ordinary photolithography and etching (step 104). The region surrounded by the groove 4 becomes an independent semiconductor region 5. In FIG. 4, a dense region 6 in which the semiconductor regions 5 are gathered is shown on the left side, and a sparse region 7 in which a single semiconductor region 5 is located is schematically shown on the right side.

Next, as shown in FIG. 5, an insulating film 8 made of, for example, a CVD oxide film (SiO ₂ film) is formed over the entire main surface of the semiconductor substrate 1 (step 105). The insulating film 8 on the semiconductor region 5 surrounded by the trench 4 becomes a raised portion 9.

As shown in FIG. 1, the area of the raised portion 9 increases in the dense area 6 and decreases in the sparse area 7.

The insulating film 8 is removed by a predetermined thickness by a CMP process as described later, so that only the trench 4 is filled with the element isolating insulating film.

As a result, the semiconductor region 5 surrounded by the trench 4 can be used as the active region 10.

The insulating film for element isolation is a field insulating film for partitioning each element such as logic and memory, and an insulating film for insulating each cell such as memory.

In a memory or the like, since the active regions 10 are densely arranged (dense region 6), the region of the raised portion 9 by the insulating film 8 for forming the insulating film for element isolation is increased, and the region is polished by the CMP process. The area increases, and the polishing rate decreases.

On the other hand, in the portion where the active regions 10 are scattered in the field insulating film, the region of the raised portion 9 of the insulating film 8 is reduced (sparse region 7), and the polishing area is reduced. Be faster.

Therefore, one semiconductor substrate 1 is
In this case, uniform polishing cannot be performed on the entire surface due to unevenness in the polishing allowance, and the flatness deteriorates. Therefore, in the first embodiment, the polishing area of each polishing portion is reduced, and the polishing locations are dispersed regardless of the density of the active regions 10 to achieve uniform polishing, and the polishing of the semiconductor substrate 1 is planarized. To do.

Then, as shown in FIGS. 6 and 1, an etching mask 12 having an opening 11 in a portion corresponding to the semiconductor region 5 (active region 10) is formed (step 106). The etching mask 12 is formed by selectively exposing and developing a photoresist film formed over the entire main surface of the semiconductor substrate 1. The exposure of the photoresist film is performed using a mask having an exposure pattern obtained by inverting the exposure pattern of the photolithography mask used when forming the grooves 4.

Next, the insulating film 8 is etched to a predetermined thickness using the etching mask 12 (step 1).
07). The etching is performed by, for example, wet etching that enables isotropic etching. As a result, most of the raised portion 9 is removed by etching,
The edge portion of the portion 9 slightly rises and remains as the remaining portion 13.

When the opening 11 is small,
A surfactant is added to the etchant to make it easier for the etchant to enter the opening 11.

In the dense region 6, since the etching extends to the adjacent raised portion, the boundary between the adjacent raised portions is also removed. Become. As a result, even if the insulating film has a raised portion on the main surface of the semiconductor substrate 1, the portion to be subjected to the CMP process is the raised remaining portion 13. It is made uniform (see FIG. 7).

Next, as shown in FIG. 7, after the etching mask 12 is removed, the main surface of the semiconductor substrate 1 is subjected to chemical mechanical polishing (CMP), and as shown in FIG. 1 is flattened. Note that the two-dot chain line in FIG. 1 is the final polishing height A by the CMP process.

In the CMP process, as shown in FIG. 7, in the main surface of the semiconductor substrate 1, the active region 10 rises irrespective of whether the active region 10 is the dense region 6 or the sparse region 7. Since the polishing is uniform over the entire main surface of the semiconductor substrate 1 as compared with the conventional case where the portion 9 is directly polished, the averaged polishing over the entire main surface of the semiconductor substrate 1 is possible, and the polishing is flattened. Can be achieved.

Since the polishing rate of the polishing stop film 3 is about three times lower than that of the insulating film 8 made of a CVD oxide film, the polishing stop
If the polishing is carried out so as to leave, the polishing stop film 3 acts as a polishing stopper, so that the main surface of the semiconductor substrate 1 is reliably flattened.

The CVD oxide film remaining in the trench 4 becomes an insulating film 15 for element isolation, and the semiconductor region 5 surrounded by the insulating film 15 for element isolation can be used as an active region 10 for forming an element or the like.

Next, as shown in FIG. 9, the polishing stop film 3 on the pad oxide film 2 is removed by etching.

Next, a state in which a MOSFET is formed in the active region 10 of the semiconductor substrate 1 after the planarization has been completed will be described with reference to FIGS.

Pad oxide film 2 on the main surface of semiconductor substrate 1
Is removed by etching with a hydrogen fluoride solution or the like, as shown in FIG. 10, an insulating film 20 is formed on the main surface of the semiconductor substrate 1 to a predetermined thickness.
An electrode forming film 21 is formed thereon. For example, the insulating film 20 is a thermal oxide film (SiO 2) for forming a gate insulating film.
₂ ), and the electrode forming film 21 is a polysilicon film for forming a gate electrode.

Next, the electrode forming film 21 and the insulating film 20 are formed by a usual photolithography technique and etching technique.
Is selectively etched to form a gate insulating film (gate oxide film) 22 and a gate electrode 23 as shown in FIG.

Next, as shown in FIG. 12, an insulating film 25 is selectively formed on the main surface of the semiconductor substrate 1.
5 from the pair of openings 26 to the surface layer of the active region 10
Is implanted and annealed to form a pair of n-type semiconductor regions 3 serving as source and drain regions.
0, 31 are formed.

Next, as shown in FIG. 13, wirings 32 and 33 are selectively formed on the main surface of the semiconductor substrate 1. The wirings 32 and 33 are electrically connected to the semiconductor regions 30 and 31, respectively.

Next, as shown in FIG.
The insulating film 35 is selectively formed on the main surface of the
Cover 2,33. Thereby, MOSFET Q is formed.

According to the method of manufacturing the semiconductor integrated circuit device of the first embodiment, the following effects can be obtained.

(1) The insulating film (CVD oxide film) on the active region rises high, and the insulating film on the trench surrounding the active region is low. Therefore, a semiconductor substrate region (dense region) in which active regions are densely arranged has a large polishing area (polishing amount) in the CMP process, and a semiconductor substrate region (sparse region) in which the active regions are sparsely arranged is subjected to polishing in the CMP process. The area (polishing amount) is small. In the first embodiment, the protruding portion of the insulating film is removed except for the peripheral portion thereof using an etching mask having an opening in a portion corresponding to the active region. Since the boundary portion is also removed and only the peripheral portion of the dense region has a raised residual portion, the distribution of the bulged residual portion to be polished is uniform and the polished area is significantly reduced, so that the main surface of the semiconductor substrate is flattened. Becomes possible.

(2) According to the method of manufacturing the semiconductor integrated circuit device of the first embodiment, the polishing stop film having a lower polishing rate than the SiO ₂ film is formed on the pad oxide film on the surface of each active region. Since the polishing stop film acts as a polishing stopper during the chemical mechanical polishing process, the polishing end height over the entire semiconductor substrate main surface is constant, and the semiconductor substrate main surface is flattened. Can be achieved.

(3) According to the first embodiment, since the etching for selectively removing the insulating film is performed by wet etching, the etching solution entering the opening of the etching mask performs isotropic etching. In addition, the residual swell can be reduced in area. Therefore,
The planarization effect by the chemical mechanical polishing process is higher.

(4) According to the first embodiment, when wet etching is performed using an etching solution containing a surfactant in the above-described etching, the etching solution enters the opening even if the opening of the etching mask is small. Therefore, the etching can be performed efficiently, and the main surface of the semiconductor substrate can be reliably flattened by the chemical mechanical polishing process.

(5) According to the first embodiment, since the exposure pattern of the etching mask used in the etching is an inverted pattern of the exposure pattern of the photolithography mask at the time of forming the groove, the layout processing of the etching mask is not performed. It will be easier.

(6) According to the method of manufacturing a semiconductor integrated circuit device of the first embodiment, the flattening of the main surface of the semiconductor substrate is improved when the insulating film for element isolation is formed, so that a fine pattern can be processed. Therefore, a highly integrated semiconductor integrated circuit device can be manufactured with a high yield.

(Embodiment 2) FIG. 15 is a partial cross-sectional view showing a state where an insulating film is selectively etched in a method of manufacturing a semiconductor integrated circuit device according to Embodiment 2 of the present invention.

In the second embodiment, when the raised portion 9 of the insulating film 8 is selectively etched, the etching is performed by two etching processes. That is, the first etching is performed by anisotropic dry etching, and the raised portion 9 has a predetermined thickness.

Next, a second etching is performed by wet etching which is an isotropic etching, and the height of the flat surface 40 of the etching on the active region 10 (semiconductor region 5) and the flat surface 41 of the insulating film 8 on the groove 4 are increased. Approximate the approximation.

Thereafter, the main surface of the semiconductor substrate 1 is planarized by performing a chemical mechanical polishing process.

The method of manufacturing a semiconductor integrated circuit device according to the second embodiment has the same effects as those of the first embodiment, and also has the following effects.

That is, after the raised portion of the insulating film (insulating film for element isolation) is reduced to some extent by the first anisotropic dry etching, the entire raised portion is etched again by wet etching having a high isotropic etching effect. Therefore, the remaining area of the raised portion is reduced, and the flattening accuracy in the subsequent chemical mechanical polishing process is further improved.

(Embodiment 3) FIGS. 16 to 19 are diagrams relating to a method of manufacturing a semiconductor integrated circuit device according to Embodiment 3 of the present invention.

The third embodiment is an effective method when a groove is formed on the main surface of a semiconductor substrate, or when an alignment mark used for mask alignment at the time of exposure is formed.

FIG. 16 is a cross-sectional view in which a cross-shaped alignment mark 45 is formed on the main surface of the semiconductor substrate 1 by, for example, the groove 4. The alignment mark 45 is composed of the semiconductor region 5, and the pad oxide film 2 and the polishing stop film 3 are formed on the surface. The insulating film 8 made of a CVD oxide film provided on the main surface of the semiconductor substrate 1 has an opening 1
It has been etched by wet etching using an etching mask 12 having 1.

In the third embodiment, the alignment mark 45
The size of the opening 11 is larger than that of the above-mentioned size, and the etching is deeper than the polishing stop film 3.

Such a semiconductor substrate 1 will be described next with reference to FIG.
As shown in FIG. 7, the etching mask 12 is removed.

Next, the main surface of the semiconductor substrate 1 is planarized by chemical mechanical polishing as shown in FIG. Since the chemical mechanical polishing process is terminated when the polishing stop film 3 is interrupted, an arc surface 46 by etching remains around the polishing stop film 3.

Next, as shown in FIG. 19, the polishing stop film 3 is removed. The peripheral surface of the polishing stop film 3 is a surface perpendicular to the main surface of the semiconductor substrate 1, and since this surface intersects the arc surface 46, the intersection edge is sharp and the alignment mark 45 is sharp. To be able to observe.

According to the third embodiment, by changing the size of a part of the opening 11 of the etching mask 12,
The step of exposing the alignment mark for mask alignment becomes unnecessary.

That is, conventionally, when the chemical mechanical polishing process is performed, the main surface of the semiconductor substrate 1 is flattened and the alignment becomes difficult. Therefore, the step of revising the alignment mark after the chemical mechanical polishing process is performed. However, according to the third embodiment, this step becomes unnecessary, and the manufacturing cost of the semiconductor integrated circuit device can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

In the above embodiment, the example in which the present invention is applied to flatten the main surface of the semiconductor substrate when forming the insulating film for element isolation has been described. The same effect can be obtained by applying the same method to the formation of the wiring and the flattening of the wiring.

[0082]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) When an insulating film provided on the main surface of a semiconductor substrate for forming an insulating film for element isolation is planarized by chemical mechanical polishing, an opening corresponding to an active region is formed on the insulating film. After forming an etching mask having
Since the insulating film portion (elevated portion) raised on the active region by wet etching using this etching mask is etched to a predetermined thickness, the raised residual portion becomes only the peripheral portion of the insulating film active region.
In the region where the active region becomes dense, the adjacent raised portion is also etched away, so that the raised portion remains only in the peripheral portion in the dense region, and the difference in the density of the raised portion in each region of the semiconductor substrate main surface is reduced. In this chemical mechanical polishing process, uniform polishing can be performed over the entire main surface of the semiconductor substrate, thereby improving the flatness of the main surface of the semiconductor substrate.

(2) In chemical mechanical polishing, since the surface of the polishing stop film serves as a stop surface, the polishing end height over the entire semiconductor substrate main surface is constant, and the semiconductor substrate main surface can be flattened. .

(3) Since the etching is performed by wet etching, isotropic etching can be performed with an etching solution contained in the opening of the etching mask, and the area of the remaining swelling is reduced. Therefore, the planarization effect by the chemical mechanical polishing process is higher.

(4) Since the pattern of the etching mask is an inverted pattern of the exposure pattern of the photolithographic mask when the groove is formed, the formation of the etching mask becomes easy.

(5) Since the main surface of the semiconductor substrate can be flattened at the time of forming the element isolation insulating film, fine pattern processing can be performed thereafter, and a highly integrated semiconductor integrated circuit device can be manufactured at a high yield. Can be.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view illustrating flattening of an isolation insulating film in a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method for planarizing an isolation insulating film in a method for manufacturing a semiconductor integrated circuit device according to a first embodiment.

FIG. 3 is a partial cross-sectional view showing a semiconductor substrate having a pad oxide film and a polishing stop film formed on a surface in the method of manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 4 is a partial cross-sectional view showing a semiconductor substrate having a trench formed on a surface in the method for manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 5 is a partial cross-sectional view showing a semiconductor substrate in which an insulating film is provided on a surface of the semiconductor substrate in the method for manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 6 is a partial cross-sectional view showing a semiconductor substrate in which an insulating film is selectively etched in the method of manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 7 is a partial cross-sectional view showing the semiconductor substrate from which the etching mask has been removed in the method for manufacturing a semiconductor integrated circuit device of the first embodiment.

FIG. 8 is a partial cross-sectional view showing a semiconductor substrate having a surface flattened by a CMP process in the method of manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 9 is a partial cross-sectional view showing the semiconductor substrate from which the polishing stop film has been removed in the method of manufacturing the semiconductor integrated circuit device according to the first embodiment.

FIG. 10 is a cross-sectional view showing a state in which an insulating film and an electrode forming film are formed on the planarized semiconductor substrate in the method of manufacturing the semiconductor integrated circuit device according to the first embodiment.

FIG. 11 is a cross-sectional view showing a semiconductor substrate on which a gate insulating film and a gate electrode are formed in the method for manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 12 is a cross-sectional view showing a semiconductor substrate on which semiconductor regions to be source / drain regions are formed in the method for manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 13 is a cross-sectional view showing a semiconductor substrate on which wirings connected to source / drain regions are formed in the method for manufacturing a semiconductor integrated circuit device of the first embodiment.

FIG. 14 is a cross-sectional view showing a MOSFET portion formed in the method for manufacturing a semiconductor integrated circuit device according to the first embodiment.

FIG. 15 is a partial cross-sectional view showing a state where an insulating film is selectively etched in the method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 16 is a partial cross-sectional view showing a semiconductor substrate in which an insulating film is selectively etched in a method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 17 is a partial cross-sectional view showing a semiconductor substrate from which an etching mask has been removed in the method of manufacturing a semiconductor integrated circuit device according to the third embodiment.

FIG. 18 is a partial cross-sectional view showing a semiconductor substrate whose surface is flattened by a CMP process in the method of manufacturing a semiconductor integrated circuit device according to the third embodiment.

FIG. 19 is a partial cross-sectional view showing the semiconductor substrate from which the polishing stop film has been removed in the method of manufacturing a semiconductor integrated circuit device according to the third embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Pad oxide film, 3 ... Polishing stop film, 4 ... Groove (trench), 5 ... Semiconductor region, 6 ... Dense region, 7 ... Sparse region, 8 ... Insulating film, 9 ... Protruded portion, 1
Reference numeral 0: active region, 11: opening, 12: etching mask, 13: rising residual portion, 15: insulating film for element isolation, 20: thermal oxide film, 21: polysilicon film, 22: gate insulating film, 23: gate Electrodes, 25 ... insulating film, 26 ...
Openings, 30, 31 ... semiconductor region, 32, 33 ... wiring,
35: insulating film, 40: etched flat surface, 41: flat surface, 45: alignment mark, 46: arc surface.

Claims (9)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device, wherein a film formed on a main surface of a semiconductor substrate is chemically and mechanically polished to flatten the main surface of the semiconductor substrate, wherein the film is selectively etched on the film. After forming a mask, the raised portion of the film is etched to a predetermined thickness using the etching mask, the etching mask is removed, and then the film is polished. Production method. 2. The method according to claim 1, wherein a polishing stop film made of a material having a polishing rate lower than that of the film is selectively formed before forming the film, and the polishing stop film is removed after polishing. A method for manufacturing a semiconductor integrated circuit device according to claim 1. 3. The method according to claim 2, wherein a groove is formed on the main surface of the semiconductor substrate by photolithography and etching, and then the film or the polishing stop film and the film are formed on the main surface of the semiconductor substrate. 3. The method for manufacturing a semiconductor integrated circuit device according to 1. 4. After a pad oxide film is formed on the main surface of the semiconductor substrate, a polishing stop film made of a material having a polishing speed lower than the polishing speed of the film is formed on the pad oxide film, and then the groove is formed. 4. The method of claim 3, wherein
3. The method for manufacturing a semiconductor integrated circuit device according to 1. 5. The etching mask according to claim 3, wherein the etching mask is formed by using a mask having an exposure pattern opposite to an exposure pattern of a photolithographic mask at the time of forming the groove. Of manufacturing a semiconductor integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said film is an insulating film for element isolation. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein said etching is performed by wet etching. 8. The semiconductor integrated circuit device according to claim 1, wherein said etching is performed by anisotropic dry etching and wet etching performed after said dry etching. Method. 9. The etching solution used in the wet etching contains a surfactant that acts so that the etching solution easily enters the opening of the etching mask. Item 9. A method for manufacturing a semiconductor integrated circuit device according to item 8.