JPH10241353A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exclude an indefinite data when a serial data having a data length of other than a multiple of the number of conversion bits of an S/P converter is written in a FIFO memory by writing a fraction data in another register and then reading it out. SOLUTION: Upon receipt of a reset signal RS by a control circuit 11, control signals C1-C4 such as a transfer clock and a latch signal, etc., are supplied. When N, (a) and (b) are denoted as natural numbers (b<N), a serial input data SDI(=a×N+b) is converted by the S/P converter 1 into (a) pieces of parallel data, each having a bit width N and then a fraction (b), and the (a) pieces of parallel data, each having the bit width N are stored in turn in a FIFO RAM 2, while the fraction (b) is stored in a register 4. The (a) pieces of parallel data, each having the bit width N are called in turn by a P/S converter 3A, and are converted in turn into serial data in the same order as in the input case, and moreover, the fraction (b) is read out of the register 4 and is converted into a serial data, which is then added to the above converted serial data, so as to be outputted as a serial output data SDO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a first-in first-out type semiconductor memory device used for video signal processing and the like.

[0002]

2. Description of the Related Art FIG. 3 is a configuration diagram of a conventional first-in first-out (hereinafter referred to as FIFO) semiconductor memory device. In FIG. 3, a serial / parallel converter (hereinafter, referred to as an S / P converter) 1 is a converter for sequentially converting serial input data SDI into N-bit parallel data, that is, a parallel word PD1 having a bit width N. It is a vessel. The RAM 2 is a storage element for sequentially writing and storing the converted parallel words PD1. Parallel-to-serial converter
3B is a bit width N from RAM2.
Are sequentially read, and the read parallel words PD2 are in the same order as in input.
This is a converter for sequentially converting into serial data consisting of bits. The converted serial data is output as serial output data SDO. The control circuit 11 is a control circuit for supplying control signals C1, C2, and C3 to the S / P converter 1, the RAM 2, and the P / S converter 3B when receiving the reset signal RS from the outside.

FIG. 4 is a timing chart of the semiconductor memory device of FIG. With reference to FIGS. 3 and 4, an example will be described in which serial input data SDI including a series of serial data A1, A2,. When the control circuit 11 receives R1 which is the first reset signal RS, the control circuit 11 supplies a control signal C1 to the S / P converter 1. The S / P converter 1 converts the serial data A1 into parallel data A1. RAM 2 stores control signal C
2, the parallel data A1 is stored at address 0. P
The / S converter 3B reads the parallel data A1 from the address 0 of the RAM 2 according to the control signal C3, and reads the parallel data A1 in the same order as the input data.
Convert to By the same data processing, a series of input serial data A1, A2,.
Are sequentially stored in address 0, address 1,... Of address 2, and address 0, address 1
Addresses,..., And a series of serial data A
1, A2,... Are output as serial output data SDO.

[0004]

However, in the above configuration, the data length a × N + b as shown in FIG.
A problem arises when serial input data SDI consisting of bits is input. Here, N, a, and b are natural numbers, and b is 1, 2,. Of the serial input data SDI, serial data A3 composed of b bits is converted into parallel data A3 + X including undefined data X composed of N−b bits. Since the parallel data A3 + X is written to the address 2 of the RAM 2, when reading from the RAM 2, 2
After sequentially reading (= a) N-bit parallel data A1 and A2, N-bit parallel data including undefined data X is read. That is, the serial input data S
If the data length of DI is not equal to a multiple of the number N of conversion bits of the S / P converter 1, the problem is that undefined data X not included in the serial input data SDI is included in the serial output data SDO and output. There is.

In view of the above problems, the present invention provides a method for writing serial data having a data length other than a multiple of the number of conversion bits of an S / P converter without including indefinite data and writing the serial data. It is an object of the present invention to provide a FIFO type semiconductor memory device which can read out the same serial data.

[0006]

In order to solve the above-mentioned problems, the present invention provides a FIFO type semiconductor memory device.
When N, a, and b are natural numbers (b <N), a × N + b
An S / P converter for converting the serial input data composed of bits into a first parallel words each composed of N bits and a second parallel word composed of N bits including the remaining b bits; a first storage unit for sequentially storing a first parallel words, and a third parallel word composed of b bits included in serial input data among the second parallel words. And a serial output comprising a × N + b bits of a first parallel words stored in the first storage means and a third parallel word stored in the second storage means. A P / S converter for converting the data into data; and a control circuit for controlling operations of the S / P converter, the first storage unit, the second storage unit, and the P / S converter described above. Configuration Than it is.

With the above arrangement, the serial data consisting of b bits less than N bits of the serial input data is subjected to serial / parallel conversion and stored in the second storage means as a third parallel word consisting of b bits. The third parallel word is read from the second storage means, parallel-to-serial converted, and included in the serial output data as b-bit serial data.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to the present invention
For example, it is used for a video signal processing circuit used in a picture-in-picture system or the like. Hereinafter, a specific example of the present invention will be described with reference to FIGS.

FIG. 1 is a configuration diagram of a semiconductor memory device according to the present invention. In FIG. 1, an S / P converter 1 converts a serial input data SDI into a parallel word PD having a bit width N.
This is a converter for sequentially converting to 1. The RAM 2 is a storage element for sequentially writing and storing parallel words having a bit width N of the converted parallel words PD1. The register 4 is a storage element for writing and storing a parallel word having a bit width less than N, that is, fractional data having a bit number less than N, of the parallel word PD1 converted by the S / P converter 1. It is. The P / S converter 3A sequentially reads the parallel word PD2 having the bit width N from the RAM 2, sequentially converts the read parallel word PD2 into serial data of N bits in the same order as input, and furthermore, the register 4 This is a converter for reading a parallel word PD3 whose bit width is less than N from, and converting the read parallel word PD3 into serial data having the same order and the same number of bits as at the time of input. The converted serial data of N bits and the converted serial data of less than N bits are sequentially output as serial output data SDO. The control circuit 11 outputs a reset signal R
When S is received from the outside, a control signal C1 including N transfer clocks, latch signals, and the like is sent to the S / P converter 1,
Control signals C2 and C4 each comprising a transfer clock, a write enable signal, a read enable signal, etc., are transmitted to the RAM 2 and the register 4, and a latch signal, a control signal comprising a required number of transfer clocks, etc., to the P / S converter 3A. C
3 is a control circuit for supplying each of them.

FIG. 2 is a timing chart of the semiconductor memory device of FIG. 1 and 2, the data length a × N + b bits (a
= 2) will be described. The control circuit 11 outputs the first reset signal RS
The control circuit 11 supplies a control signal C1 to the S / P converter 1 when R1 is received. The S / P converter 1 converts N-bit serial data A1 which is a part of the serial input data SDI into parallel data A1 having a bit width N.
Convert to The control circuit 11 sends the control signal C2 to the RAM2.
Supply. The RAM 2 stores the parallel data A1 at address 0 according to the control signal C2. S / P converter 1 and R
AM2 performs the above sequence 2 (= a) times, and converts two (= a) serial data A1 and A2 of the serial input data SDI into two parallel words PD1 each having a bit width N. Parallel data A1 and A
2 and the parallel data A1 and A2 are sequentially stored at addresses 0 and 1 of the RAM 2.

When the input of the serial input data SDI composed of 2 × N + b bits is completed and the control circuit 11 receives the second reset signal R2, the control circuit 11 executes the S / P
The control signal C1 is supplied to the converter 1. S / P converter 1
Is the bit width N including b bits that are the remaining fractional data.
Is supplied. Where X is N
-Data consisting of b bits. However, the parallel data A3 + X is not written to the RAM2. The control circuit 11 supplies a control signal C4 to the register 4.
The register 4 stores only the b-bit parallel data A3 according to the control signal C4.

On the other hand, the control circuit 11 includes a P / S converter 3A
And the control signal C2 to the RAM2.
Supply. The P / S converter 3A sequentially reads the parallel data A1 and A2 having the bit width N from the addresses 0 and 1 of the RAM 2 by the control signal C3, and outputs the parallel data A1 and A2 at the same time as the input. The serial data is sequentially converted into two serial data A1 and A2 each consisting of N bits. Further, the control circuit 11 supplies the control signal C3 to the P / S converter 3A and the control signal C4 to the register 4.
Supply. The P / S converter 3A reads the parallel data A3 having the bit width b from the register 4 in response to the control signal C4, and reads the read parallel data A3 from the serial data of b bits in the same order as when input. A
Convert to 3. Therefore, P / S converter 3A has the same data length of 2 × N + b bits as serial input data SDI and outputs serial output data SDO in the same order. Further, the control circuit 11 outputs the second reset signal R
2, the data processing of a series of serial data B1, B2, B3 is started by the same sequence.

As described above, according to the present invention, S
When writing / reading serial data having a data length other than a multiple of the number N of conversion bits of the / P converter 1, RA for storing a parallel word having a bit width N is used.
In addition to M2, a register 4 for storing fractional data less than N bits is provided. As a result, when the serial input data SDI having the fraction data is written, only the fraction data is read from the register 4, so that undefined data generated due to the difference between the conversion bit number N and the fraction data is not included, and the serial data is not included. Serial output data SDO equal to the input data SDI can be read.

[0014]

According to the semiconductor memory device of the present invention,
When writing and reading serial data having fractional data less than the number of conversion bits of the S / P converter, serial data that does not include indefinite data generated by the fractional data and is equal to the input serial data is read. As a result, it is possible to provide a FIFO type semiconductor memory device that writes serial data having an arbitrary data length and reads serial data equal to the input data.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to the present invention.

FIG. 2 is a timing chart of the semiconductor memory device of FIG. 1;

FIG. 3 is a configuration diagram of a conventional semiconductor memory device.

FIG. 4 is a timing chart of the semiconductor memory device of FIG. 3;

[Explanation of symbols]

 Reference Signs List 1 S / P converter (serial / parallel converter) 2 RAM (first storage means) 3A P / S converter (parallel / serial converter) 4 Register (second storage means) 11 Control circuit

Claims (1)

[Claims] 1. A first-in first-out type semiconductor memory device, wherein N × a + b is a natural number (b <N), wherein a × N + b
A serial-to-parallel converter for converting the serial input data consisting of bits into a first parallel words each consisting of N bits and a second parallel word comprising the remaining b bits and consisting of N bits; A first storage means for sequentially storing the a first parallel words each consisting of N bits; and a third storage means consisting of the b bits of the second parallel words each consisting of N bits. Storage means for storing the parallel words, a first parallel words stored in the first storage means, and a third parallel word stored in the second storage means And a parallel-serial converter for converting the data into serial output data composed of a × N + b bits, the serial-parallel converter, first storage means, and second
And a control circuit for controlling the operation of the parallel-serial converter.