KR100704984B1 - Data processing system for image reliability insurance - Google Patents

Abstract

The present invention relates to a data processing system for securing image reliability. The present invention relates to a single system and a single memory clock to perform write and read operations. The advantage is that one input data can be distributed at the same time.

A data processing system according to the present invention is a data processing system for processing a bit-width image data output from an image sensor every frame, wherein the output a bit-width image data is stored according to a first memory clock. A first memory converting the stored image data into image data of 2a bit width or more and outputting the converted image data according to a second memory clock; A third memory having a plurality of addresses and including a first region and a second region capable of writing and reading according to the second memory clock; Selecting one of the first and second regions of the third memory to write image data for the current frame converted and output from the first memory in the selected region according to the second memory clock, and already A memory controller which controls to read image data of the previous frame written to the converted size in another area not selected, and outputs read data having the converted size according to the second memory clock; A data bus connected between the third memory and a memory controller, the data bus including address data and a control line; And a second memory configured to convert read data output from the memory controller into image data having a bit width and to output the converted image data according to the second memory clock.

Data processing system, single memory, single memory clock, bandwidth,

Description

DATA PROCESSING SYSTEM FOR IMAGE RELIABILITY INSURANCE}

1 is a block diagram of a data processing system according to the prior art.

2 is a diagram illustrating an operation of a first and a second memory controller for a frame and first and second memory clocks according to the related art.

3 is a block diagram of a data processing system according to the present invention;

4 is a configuration diagram of a third memory according to the present invention;

5 illustrates an operation of a memory controller for a frame and a memory clock according to the present invention.

<Description of Major Symbols in Drawing>

300: data processing system 301: first memory

302: Third memory 302a: First region

302b: second region 303: memory controller

304: second memory 305: data bus

f1: first memory clock f2: second memory clock

The present invention relates to a data processing system for securing image reliability. The present invention relates to a single system and a single memory clock to perform write and read operations. A data processing system capable of simultaneously distributing one input data.

In general, there are many systems that process and display image data. A system for processing image data commonly includes an image sensor module. In general, an image sensor module using a CMOS or CCD sensor is most commonly used.

The image sensor module outputs an image of about 30 frames per second in the VGA class, and a system that receives and processes image data output from the image sensor module is called a data processing system.

Such a data processing system needs to process image data input to the system well and convert the image data into a desired image, so that the reliability and sufficient bandwidth of the image data should be secured to output a more complete image.

However, since the operation clocks of the image sensor module and the data processing system are different, it is very difficult to secure the reliability of the image data, and many studies have been conducted to more easily secure such data reliability.

FIG. 1 is a block diagram of a data processing system 100 according to the prior art, and FIG. 2 is a diagram illustrating operations of the first and second memory controllers for a frame and first and second memory clocks according to the prior art.

As illustrated in FIG. 1, the data processing system 100 according to the related art includes a first flip flop 101, a first memory 102a, a second memory 102b, a first memory controller 103a, And a second memory controller 103b, a second flip flop 104, a first data bus 105a, a second data bus 105b, a data write selector 106a, and a data read selector 106b.

Hereinafter, an operation process of the data processing system 100 having the above configuration will be described with reference to FIGS. 1 and 2.

Continuous image frame data is input to the data processing system 100 according to the input clock f1, and the output of the input data is performed in real time according to the output clock f2.

First, the data write selector 106a selects the first memory 102a and the first memory controller 103a to store the input image data, and the first memory controller 103a selects the input image. The data is written to the first memory 102a.

In this case, the first memory controller 103a operates according to a first memory clock, and the first memory clock includes an input clock f1 and an output clock f2.

Thus, as shown in FIG. 2, the first memory controller 103a transmits an output control signal and input data to the first memory 102a according to the input clock f1, and transmits the received data. The control signal and the data signal are used to write to the storage space in the first memory 102a.

On the other hand, while the first memory controller 103a writes to the first memory 102a, the second memory controller 103b is selected by the data lead selector 106b and is already present in the second. The image data of the previous frame written to the memory 102b is read according to the output clock f2.

That is, the second memory controller 103b transmits a read control signal to the second memory 102b according to the output clock f2 and uses the transferred read control signal to transmit the read memory signal to the second memory 102b. Read image data already written therein.

Finally, the read data is output to the second flip flop 104.

Therefore, if the data processing system 100 configured as described above reads from the first memory 102a in an arbitrary frame and reads from the second memory 102b, in the next frame, The second memory 102b is written to and read from the first memory 102a.

However, the data processing system according to the related art as described above has a problem in that it cannot be used as a single memory because two different clocks are used for input and output, and clocks used for writing and reading are different, and two memory and memory controllers must be used. There was this.

In addition, since the clocks used for writing and reading are different in both the first and second memory controllers, the system design itself is very difficult.

Accordingly, the present invention has been made to solve the above problems, by using a method of increasing the bandwidth and securing the reliability of the image by unifying the system design to perform a write and read operation using a single memory and a single memory clock The present invention provides a data processing system capable of simultaneously distributing input data.

A data processing system according to the present invention for achieving the above object is a data processing system for processing a bit-width image data output in every frame from the image sensor, the first image data of the a bit width is output; A first memory configured to store according to a memory clock, convert the stored image data into image data of 2a bit width or more, and output the converted image data according to a second memory clock; A third memory having a plurality of areas and including a first area and a second area capable of writing and reading image data according to the second memory clock; Selecting one of the first and second regions of the third memory to write image data for the current frame converted and output from the first memory in the selected region according to the second memory clock, and already A memory controller which controls to read image data of the previous frame written to the converted size in another area not selected, and outputs read data having the converted size according to the second memory clock; A data bus connected between the third memory and a memory controller, the data bus including address data and a control line; And a second memory configured to convert read data output from the memory controller into image data having a bit width and to output the converted image data according to the second memory clock.

Herein, the data bus is divided in time.

The memory controller may control the write and the read to be alternately performed through the divided data bus.

In addition, the memory controller is characterized in that, when the frame is changed, the area to be written and the area to be read are controlled to be interchanged.

The third memory may have an address area for simultaneously writing and reading the current frame and the previous frame.

The first memory may have an address twice or more than a minimum address that can be written to and read from the third memory.

The first and second memories may be FIFOs.

The first and second memories may be dual port memories.

The frequency of the first memory clock may be less than or equal to the frequency of the second memory clock.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of the data processing system 300 according to the present invention, and FIG. 4 is a block diagram showing the configuration of the third memory 302 according to the present invention.

3 and 4, the data processing system 300 according to the present invention includes a first memory 301, a third memory 302, a memory controller 303, a second memory 304, It consists of a data bus 305.

Here, the first memory 301 may use a FIFO or a dual port memory having two ports, and in the case of using the dual port memory, an additional logic circuit is required to have a first-in first-out characteristic.

In addition, as shown in FIG. 4, the third memory 302 includes a first area 302a having a plurality of address areas and capable of writing and reading according to the second memory clock f2. The second area 302b is included.

In this case, the third memory 302 includes a plurality of address areas for storing the current frame and the previous frame at the same time. If any one of the first and second areas writes the current frame, the remaining area is You can read the previous frame.

Here, the memory that can be used as the third memory 302 includes a synchronous RAM (SRAM), a synchronous dynamic RAM (SDRAM), a dual port memory (DPRAM), and the like, in consideration of a price-to-capacity price, etc., a synchronous dynamic RAM This is the most used.

The memory controller 303 selects any one of the first and second regions 302a and 302b of the third memory 302 to be converted and output from the first memory 301. Write image data for a frame to the selected region according to the second memory clock f2, and control to read image data for a previous frame already written to the converted size in another unselected region, and The read data having the converted size is output according to the second memory clock f2.

In addition, since the third memory 302 is a single memory, the data bus 305 is divided in time, and is connected between the third memory 302 and the memory controller 303 to include address data and a control line. It performs the function.

Also, like the first memory 301, the third memory 304 may be configured as a FIFO or a dual port memory, and the read data output from the memory controller 303 may be read by the second memory clock ( Output in accordance with f2).

Hereinafter, an operation process of the data processing system 300 having the above configuration will be described.

First, the first memory 301 stores a bit-width image data output by an image sensor (not shown) every frame according to the first memory clock f1, and stores the stored image data by 2a bit width. The image data is converted into the above-described image data, and the converted image data is output in accordance with the second memory clock f2.

In this case, the frequency of the first memory clock f1 is less than or equal to the frequency of the second memory clock f2. If the frequency of the first memory clock f1 is greater than the frequency of the second memory clock f2, image data input to the data processing system 300 may not be processed and some data may be damaged. Since the user cannot display a desired image, the frequency of the first memory clock f1 must be less than or equal to the frequency of the second memory clock f2.

Next, the memory controller 303 sets a full flag in the first memory 301 and when more image data is input than the set full flag, the first memory 301. ) 2a bit width or more of the image data is imported from the first memory 301 according to the second memory clock f2 until all the image data stored in the PDP is output, and the imported image data is transferred to the third memory 302. Either one of the first or the second area (302a, 302b) is selected to write to the selected area. At this time, the written image data is image data for the current frame.

In addition, the memory controller 303 reads image data for a previous frame already written from an unselected area among the first and second areas constituting the third memory 302. However, when the second memory 304 is full, the read operation is stopped.

Finally, the second memory 304 converts read data of 2a bit width or more output from the memory controller 303 into image data of a bit width, and converts the converted image data into the second memory clock ( Output in accordance with f2).

As described above, the write and read operation by the memory controller 303 may be implemented in the third memory 302 and the memory controller 303 having a bandwidth of 2a bit width or more according to the present invention. The reason will be described in FIG. 5 to be described later.

FIG. 5 is a view illustrating an operation of a memory controller for a frame and a memory clock f2 according to the present invention. As shown in FIG. 5, the memory controller may be configured according to the second memory clock f2 which is a single memory clock. It controls the write (W) and read (R) operation to be performed alternately.

This method is different from the conventional data processing system in which the write and read operations were simultaneously performed. Since the write and read operations are performed using the single memory, the third memory, a single data bus is used in time. Since the write and write operations must be performed using the divided data bus, the memory controller can perform the write and read operations according to the second memory clock f2. It acts as a control so that this can be done alternately.

Accordingly, the present invention has the advantage that the system design itself is very easy since the write and read operations are performed using the third memory as the single memory and the second memory clock f2 as the single memory clock.

At this time, the data divided in time and the write (W) and the read (R) is a burst operation in the size of 1 to 256 addresses, the memory controller, when the frame is changed, the area to be written (W) and read (R) It also controls the areas to be replaced.

That is, if the memory controller shown in Fig. 5 writes (W) to the first area of the third memory and reads (R) to the second area in an arbitrary frame, the memory controller shown in FIG. The light W is read and the read R is read in the first region.

In this case, when a bit width image data is input from the image sensor, the write (W) and read (R) operations may be implemented in the third memory 302 and the memory controller 303 having a bandwidth of 2a bit width or more. Can be. The reason for this is that as described above, since the write (W) and read (R) operations are not performed simultaneously but are alternately performed through the data bus divided in time, the bandwidths of the third memory and the memory controller are input bandwidth of the system. It must be at least twice as large.

Referring to the relationship between the image sensor, the third memory and the memory controller, as shown in FIG. 5, it is most preferable to use a data processing system including the third memory and the memory controller having a bandwidth of 4a bits. However, even if the image sensor is VGA or the image sensor is MEGA, It is also possible to use a data processing system that includes a third memory and a memory controller having a bandwidth of 2a bit width or more than 2a bit width if it has a certain size. Accordingly, the first memory should have at least twice as many addresses as the minimum address that can be written to and read from the third memory, and the second memory and the memory controller have 4bit, 8bit, 16bit, 24bit, 32bit, 64bit through parallel configuration. It can be implemented in various forms such as to increase bandwidth more easily.

Accordingly, the present invention also has the advantage of simultaneously distributing one input data by using a method of increasing bandwidth with only a simple memory configuration.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and various substitutions, modifications, and changes within the scope of the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It will be appreciated that such substitutions, changes, and the like should be considered to be within the scope of the following claims.

As described above, according to the data processing system for securing an image according to the present invention, as the write and read operations are performed using a single memory and a single memory clock, the system design itself is very easy and thus the reliability of the image is easily secured. Has the advantage.

In addition, there is an effect that can simultaneously distribute a single input data by using a method of increasing the bandwidth.

Claims (9)

In a data processing system for processing a bit-width image data output from the image sensor every frame, A first storing the output a bit width image data according to a first memory clock, converting the stored image data into image data of 2a bit width or more, and outputting the converted image data according to a second memory clock Memory; A third memory having a plurality of regions and including a first region and a second region capable of writing and reading according to the second memory clock; Selecting one of the first and second regions of the third memory to write image data for the current frame converted and output from the first memory in the selected region according to the second memory clock, and already A memory controller which controls to read image data of the previous frame written to the converted size in another area not selected, and outputs read data having the converted size according to the second memory clock; A data bus connected between the third memory and a memory controller, the data bus including address data and a control line; And And a second memory configured to convert read data output from the memory controller into image data having a bit width and to output the converted image data according to the second memory clock. The method of claim 1, And the data bus is divided in time. The memory controller of claim 2, wherein the memory controller comprises: And controlling the write and read to be alternately performed through the divided data bus. The memory controller of claim 3, wherein the memory controller comprises: And when the frame is changed, the area to be written and the area to be read are controlled to be interchanged with each other. The method of claim 1, wherein the third memory, And an address area for simultaneously writing and reading the current frame and the previous frame. The method of claim 1, And the first memory has an address twice or more than a minimum address that can be written to and read from the third memory. The method of claim 6, And the first and second memories are FIFOs. The method of claim 6, And the first and second memories are dual port memories. The method of claim 1, The frequency of the first memory clock is less than or equal to the frequency of the second memory clock.

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