JPH10223769A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof, wherein the width of a cannel region in a MOS field effect transistor is set independent of the width of an acid-resistant mask which is used in a selective oxidation process where a field insulating film is formed, so that the device is restrained from varying in electrical properties even if the acid- resistant mask varies in width. SOLUTION: A nitride film serving as a selective oxidation mask is left as it is, As (in case of N channel) is introduced into the peripheral part of the active region of a MOS field effect transistor to form an N-type impurity- introduced region, then the nitride film is removed, boron (B) is channel-injected to turn the N-type impurity-introduced region to a low-impurity concentration region 15A which can be prescribed in threshold voltage, a gate electrode 18G is formed traversing a part of the low-impurity concentration region 15A, and a region just under the gate electrode 18G is made to serve as a channel region 15C.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS (metal oxide semiconductor) having a structure in which the electrical characteristics are hardly affected even if the dimensions such as gate length and gate width vary.
The present invention relates to a semiconductor device including a field effect transistor and a method of manufacturing the same.

Generally, in order to highly integrate a semiconductor device including a MOS field-effect transistor, the gate length and the gate width of the MOS field-effect transistor have been reduced. Since this causes variations in device characteristics such as threshold voltage and saturation current, this problem must be solved.

[0003]

2. Description of the Related Art Generally, when a gate structure is formed in a MOS field effect transistor, for example, an n-channel MOS field effect transistor, the following process is generally performed.

(1) Selective oxidation using a nitride film as an oxidation resistant mask
Silicon: LOCOS) is applied to form a field insulating film on a silicon substrate. (2) After removing the oxidation-resistant mask, boron ions are implanted to form a channel stop layer. Incidentally, the channel stop layer is not shown. (3) The threshold voltage is adjusted by implanting boron ions into the channel region. (4) forming a gate insulating film and a gate electrode;

FIGS. 5A and 5B are explanatory views of a main part of the MOS field-effect transistor manufactured as described above. FIG. 5A is a side cross-section taken along line XX shown in FIG. Main part plane, 1 is a silicon semiconductor substrate, 2 is a field insulating film made of SiO ₂ , 3 is a channel injection region, 4 is Si
A gate insulating film made of O ₂ , 5 a gate electrode made of impurity-containing polycrystalline silicon, 6 an n ⁺ source region, and 7 an n
⁺ Drain region, W _C represents the width of the channel region respectively.

As is apparent from FIG. 5, a channel region (inversion layer) exists uniformly immediately below the gate electrode 5, and the width W _{C of the} channel region is equal to that of the field insulating film 2. In this case, the width is determined by the width of the nitride film as the oxidation resistant mask.

[0007]

When a pattern such as a gate length or a gate width is reduced in order to increase the degree of integration of a semiconductor device including a MOS field-effect transistor, variations in the pattern size are reduced to such an extent that the pattern is reduced. Not correspondingly smaller.

Further, as is apparent from the above description, the width of the channel region is determined by the width of the oxidation-resistant mask. Therefore, when the width of the oxidation-resistant mask changes, the electric characteristics of the device change.

Therefore, in a semiconductor device including a miniaturized MOS field effect transistor, the dimensional variation of an oxidation-resistant mask such as a nitride film greatly affects the electrical characteristics of the device. When the variation is large, the production yield is reduced, and a special circuit that takes the variation into consideration is required.

According to the present invention, the width of the channel region in the MOS field effect transistor is not dependent on the width of the oxidation resistant mask used for the selective oxidation when forming the field insulating film. Even if the width of
Ensure that the electrical characteristics of the device do not change.

[0011]

According to the present invention, a channel region is formed only at a peripheral portion of an element, that is, an edge of an active region, and the width of the channel region is used as a mask for selective oxidation for forming a field insulating film. Basically, it does not depend on the film width.

In order to form such a channel region,
Using the nitride film used when the field insulating film is formed by the selective oxidation method as a mask, impurities of the opposite conductivity type to the channel implantation dopant, for example, n In the case of a channel MOS field effect transistor, phosphorus (P) or arsenic (As) is introduced, and the impurity concentration is compensated between the channel implantation dopant and the impurity of the opposite conductivity type.
By performing e), the impurity concentration may be effectively reduced.

As a technique for performing ion implantation using a nitride film as a mask after forming a field insulating film by a selective oxidation method, an invention disclosed in Japanese Patent Application Laid-Open No. 5-283404 is known.

In this known invention, after a field insulating film is formed by selective oxidation, channel stop implantation is performed near the interface between the field insulating film and the active region using a nitride film as a mask.
For example, in the case of an n-channel MOS field effect transistor, boron is implanted, and then the nitride film is removed.
Channel implantation, that is, boron implantation is also performed in the case of an n-channel MOS field effect transistor.
A gate insulating film and a gate electrode are formed.

As described above, in the known invention, the impurity of the same conductivity type as that of the channel dopant is introduced using the nitride film as a mask, and the width of the channel region is reduced by the conventional MOS.
Like the field-effect transistor, the width of the nitride film used as a mask for selective oxidation for forming the field insulating film is defined by the width of the nitride film. It should be noted that the characteristics are also affected and are completely different from the present invention.

As described above, in the semiconductor device and the method of manufacturing the same according to the present invention, (1) an impurity of a conductivity type opposite to a conductivity type of a channel impurity is formed in a peripheral portion of an active region in a MOS field effect transistor. (P for an n-channel MOS field effect transistor
Or a region which acts as a substantial channel by introducing a type impurity and an n-type impurity in the case of a p-channel MOS field-effect transistor to offset the channel impurity and to define a threshold voltage. Or

(2) Oxidation resistant mask (for example, nitride film 1)
3) Applying a selective oxidation method (for example, LOCOS method) using a field insulating film (for example, field insulating film 14)
And then forming an impurity of a conductivity type opposite to the conductivity type of the channel impurity (p-type impurity or p-channel MOS in the case of an n-channel MOS field-effect transistor) in the peripheral portion of the active region while leaving the oxidation-resistant mask. A step of introducing a n-type impurity (for a field-effect transistor) to form a region (for example, an n-type impurity-introduced region 15);
A step of introducing a channel impurity (for example, boron) after removing the oxidation-resistant mask; and a step of forming a gate composed of a gate insulating film (for example, gate insulating film 17) and a gate electrode (for example, gate electrode 18G). Forming a source region (for example, the source region 19) and a drain region (for example, the drain region 20).

(3) In the above (2), an impurity of the conductivity type opposite to that of the channel impurity is ion-implanted into the peripheral portion of the active region in an oblique direction with respect to the substrate while the oxidation-resistant mask is left. Or characterized by comprising a step of forming a region, or,

(4) In the above (2), after forming the impurity-containing film (for example, the impurity-containing polycrystalline silicon film 21) with the oxidation-resistant mask left, the solid-phase diffusion is performed. A step of introducing an impurity of a conductivity type opposite to the conductivity type of the channel impurity into a peripheral portion of the active region to form a region.

Since the width of the channel region is determined irrespective of the width of the gate by adopting the above means, even if there is a dimensional variation in the nitride film at the time of forming the field insulating film, each MOS field effect in the plane can be obtained. Since the width of the channel region of the transistor is kept uniform and the electrical characteristics are uniform, a semiconductor device which is miniaturized and has a high degree of integration can be manufactured with high yield.

[0021]

FIG. 1 to FIG. 3 are main part explanatory views showing a MOS field-effect transistor at a key point in a process for explaining a first embodiment of the present invention. A)
3 (B) shows a main part plane, and the MOS field-effect transistor shown in FIGS. 1 to 3A is taken along a line XX shown in FIG. 3 (B). You can see that you have been disconnected. Here, the n-channel transistor has been described, but the p-channel transistor is obtained by inverting the conductivity type.
Of course, it can be applied to a transistor.

1 (A) 1- (1) Thermal oxidation method and chemical vapor deposition (chemical vapor deposition)
By applying a por deposition (CVD) method, a pad insulating film 12 made of SiO ₂ and a nitride film 13 serving as an oxidation-resistant mask are formed on a silicon semiconductor substrate 11.

1- (2) By applying the lithography technique, the pad insulating film 12 and the nitride film 13 are patterned to leave those covering the active region and remove the others.

1- (3) Selective thermal oxidation using the nitride film 13 as a mask is performed by applying the LOCOS method,
A field insulating film 14 of [μm] to 0.3 [μm] made of SiO ₂ is formed.

1- (4) By applying the ion implantation method, the ion acceleration energy is set to, for example, 20 keV and the dose is set to, for example, 1 × 10
Implant As ions under the condition of ¹⁴ [cm ^-2 ].

As described above, the n-type impurity-doped region 15 is formed near the interface between the nitride film 13 and the field insulating film 14, that is, at the edge of the active region.

The n-type impurity implanted here is As
The ion acceleration energy is changed to, for example, 10 keV, and the dose is changed to, for example, 1 × 10 ¹⁴ cm ⁻² .

The ion implantation conditions in this case are such that the ion acceleration energy is in the range of 10 keV to 50 keV and the dose is 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² . Each of the ranges can be selected, and these are adjusted in consideration of the thickness of the field insulating film, the set value of the threshold voltage, and the like.

The ion implantation is performed at an angle perpendicular or oblique to the silicon semiconductor substrate 11.
When performed from an oblique direction, the impurity concentration and width of the n-type impurity introduction region 15 can be adjusted.
It is useful for controlling the threshold voltage and the drain current.

After the ion implantation, a heat treatment for activating the impurities may be performed. When the heat treatment is performed, the impurities are thermally diffused and the impurity concentration distribution changes.
Can be adjusted in impurity concentration and width.

Referring to FIG. 2A, 2- (1) the whole is immersed in a nitride etchant to remove nitride film 13.

2- (2) By applying the ion implantation method, the ion acceleration energy is set to, for example, 40 keV and the dose is set to, for example, 2 × 10
^A channel stop implantation region (shown by a broken line) is formed by implanting B ions at ¹² [cm ^-2 ].

FIG. 2 (B) 2- (3) By applying the ion implantation method, the ion acceleration energy is set to, for example, 20 keV and the dose is set to, for example, 1 × 10
^A channel implantation region 16 is formed by implanting B ions at ¹³ [cm ^-2 ].

As described above, when the channel implantation of B ions is performed, the concentration of the n-type impurity-doped region 15 is substantially reduced since the n-type impurity-doped region 15 is compensated by the B ions. If the gate is formed thereon, it becomes a region that can operate as a channel of the field-effect transistor. Note that the lightly doped n-type impurity introduction region 15 is referred to as a low impurity concentration region 15A.

Referring to FIG. 3, 3- (1) a thickness of, for example, 4 nm in a wet oxidation atmosphere at a temperature of 800 ° C. by applying a thermal oxidation method after removing the pad insulating film 12. The gate insulating film 17 made of SiO ₂ is formed.

3- (2) The thickness is, for example, 150 [n] by applying the CVD method.
m] of the polycrystalline silicon film 18 is formed.

3- (3) Resist process in lithography technology, and
Etching gas of HBr (for polycrystalline silicon), CH
Reactive ion etching to be F ₃ + CF ₄ (for SiO ₂ ):
The polycrystalline silicon film 1 is formed by applying the RIE method.
8 and the gate insulating film 17 are etched to form a gate. In FIG. 3B, the gate electrode made of polycrystalline silicon is indicated by a symbol 18G, and the low impurity concentration region 15A immediately below the gate electrode 18G operates as a channel region. 15C is given.

3- (4) By applying the ion implantation method, the ion acceleration energy is set to, for example, 10 keV and the dose is set to, for example, 4 × 10
^{13 As} [cm ^-2 ], As ions are implanted, and L
A source region and a drain region for realizing a lightly doped drain (DD) structure are formed.

3- (5) The thickness is, for example, 40 [n] by applying the CVD method.
forming a SiO ₂ film of m].

3- (6) Anisotropic etching of the SiO ₂ film formed in the step 3- (5) is performed by applying the RIE method using CHF ₃ + CF ₄ as an etching gas, Form sidewalls on the sides. The side wall is not shown.

3- (7) By applying the ion implantation method, the ion acceleration energy is set to, for example, 10 keV and the dose is set to, for example, 1 × 10
^By implanting As ions at ¹⁵ [cm ^-2 ], a source region 19 and a drain region 20 for contacting the electrodes are formed.

3- (8) Thereafter, by applying a normal technique, an interlayer insulating film, electrodes and wiring, a protective film, and the like are formed to complete the process.

In the first embodiment described above, the ion implantation method is applied when forming the n-type impurity-doped region 15. However, the ion implantation method may be used even if another technique, for example, a solid-solid diffusion method is applied. good.

FIG. 4 is a fragmentary side view showing a MOS field-effect transistor at a key point in the process for explaining the second embodiment of the present invention. The symbols used in FIGS. The same symbols represent the same parts or have the same meaning.

FIG. 4 is a view for explaining a step corresponding to the step described with reference to FIG. 1. In the second embodiment, selective thermal oxidation using nitride film 13 as a mask is performed to form a field insulating film. In the next step after the formation of CV14, CV
By applying the D method, for example, a polycrystalline silicon film 21 containing As or P is formed, and a heat treatment is performed to diffuse As or P into the silicon semiconductor substrate 11 in a solid-solid state. This is for forming the type impurity introduction region 15.

The heat treatment in this case is performed, for example, at a temperature of 900.
[° C] to 1000 [° C], and the time is 10 [seconds] to 1
This is achieved by setting it to about [minutes]. Thereafter, the polycrystalline silicon film 21 is removed. The film containing impurities is not limited to a polycrystalline silicon film, but may be an amorphous silicon film or a SiO ₂ film.

[0047]

In the semiconductor device and the method of manufacturing the same according to the present invention, an impurity having a conductivity type opposite to that of the channel impurity is introduced into a peripheral portion of an active region in a MOS field effect transistor. , Thereby defining a threshold voltage, and realizing a region that acts as a substantial channel.

Since the width of the channel region is determined irrespective of the width of the gate by adopting the above configuration, even if the nitride film has a dimensional variation at the time of forming the field insulating film, each MOS field effect in the plane can be obtained. Since the width of the channel region of the transistor is kept uniform and the electrical characteristics are uniform, a semiconductor device which is miniaturized and has a high degree of integration can be manufactured with high yield.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a main part showing a MOS field-effect transistor in a process step for explaining a first embodiment of the present invention;

FIG. 2 is an explanatory view of a main part showing a MOS field-effect transistor in a process step for explaining the first embodiment of the present invention;

FIG. 3 is an explanatory view of a main part showing a MOS field-effect transistor in a process key point for explaining the first embodiment of the present invention;

FIG. 4 is a fragmentary side view showing a MOS field-effect transistor at a key point in a process for explaining a second embodiment of the present invention;

FIG. 5 is an explanatory view of a main part showing a MOS field-effect transistor manufactured according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 11 silicon semiconductor substrate 12 pad insulating film 13 nitride film (oxidation resistant mask) 14 field insulating film 15 n-type impurity introduction region 15A low impurity concentration region 15C channel region 16 channel injection region 17 gate insulating film 18 polycrystalline silicon film 18G gate Electrode 19 Source region 20 Drain region 21 (impurity-containing) polycrystalline silicon film

Claims (4)

[Claims] An impurity having a conductivity type opposite to a conductivity type of a channel impurity is introduced into a peripheral portion of an active region in a MOS field effect transistor to offset a channel impurity to define a threshold voltage and to function as a substantial channel. A semiconductor device comprising a region to be formed. A step of forming a field insulating film by applying a selective oxidation method using an oxidation-resistant mask; and a step of forming a channel impurity conductivity type in a peripheral portion of the active region with the oxidation-resistant mask left. A step of forming a region by introducing an impurity of the opposite conductivity type, a step of introducing a channel impurity after removing the oxidation-resistant mask, and a step of forming a gate composed of a gate insulating film and a gate electrode And a step of forming a source region and a drain region, and a method of manufacturing a semiconductor device. 3. A step of forming a region by ion-implanting an impurity of a conductivity type opposite to that of a channel impurity into a peripheral portion of the active region in an oblique direction with respect to the substrate while leaving the oxidation-resistant mask. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the method comprises: 4. An impurity-containing film is formed with an oxidation-resistant mask left, and then an impurity of a conductivity type opposite to that of a channel impurity is introduced into a peripheral portion of the active region by solid-phase diffusion. 3. The method for manufacturing a semiconductor device according to claim 2, further comprising the step of forming a region by forming the region.