KR19990045011A - Semiconductor device manufacturing method - Google Patents

Abstract

In a semiconductor device manufacturing method, an element including a source, a drain, and a gate electrode is formed on a silicon substrate. An interlayer film is formed on the device. The contact hole is selectively formed to reach the device of the interlayer film, thereby exposing a portion of the device at the bottom of the contact hole. The silicon substrate on which the element and the interlayer film are formed is heated. Wiring members are formed in contact with a portion of the device by filling contact holes with a conductive material.

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which wiring in contact with elements formed on a silicon substrate is made of silicon.

Silicides, such as alloys of silicon and metal, have been commonly used to reduce contact resistance or to reduce the resistance of polysilicon gate electrodes. For example, the surface of the source and drain formation region is coated with silicide that reduces the contact resistance between the source and drain electrodes.

A method of manufacturing a MOSFET (metal oxide semiconductor field effect transistor) using silicide will be briefly described.

As shown in Fig. 4A, field oxide films 602 are formed on the silicon substrate 601 at predetermined intervals. The field oxide film 602 partitions the surface of the silicon substrate 601 to form an element formation region.

In order to adjust the threshold voltage of the transistor, B is ion implanted into each element formation region of the silicon substrate 601 to form the impurity region 603. After the natural oxide film formed on the surface of the element formation region of the silicon substrate 601 is removed with an acidic cleaning solution such as dilute hydrofluoric acid, a gate insulating film 604 is formed as shown in Fig. 4B.

Polysilicon is deposited on the gate insulating film 604 by CVD (chemical vapor deposition). P (phosphorus) is added about 10 ²⁰ cm ^-3 so that the polysilicon is conductive. By using a resist pattern formed by known photolithography as a mask, the polysilicon and the gate insulating film 604 are selectively removed by dry etching using HBr or Cl gas, as shown in FIG. 4C. 605 is formed.

P is ion implanted using the gate electrode 605 as a mask to form the lightly doped regions 606 and 607 in the impurity regions 603 on both sides of the gate electrode 605.

As the insulating film is deposited on the silicon substrate 601 including the gate electrode 605 and removed by vertical anisotropic dry etching, as shown in FIG. 4D, the sidewall 605a is formed on the side of the gate electrode 605. Form. As (arsenic) is ion implanted using the gate electrode 605 and the sidewall 605a as a mask to form the source 608 and the drain 609 in the lightly doped regions 606 and 607, respectively.

In the above process, the main part of the MOSFET having the LDD (low concentration doped drain) structure is manufactured. After that, the wiring for connecting the MOSFET to the transistor is formed as follows.

In particular, as the cobalt film is deposited and heated on the silicon substrate 601 including the gate electrode 605 and the sidewall 605a, the portion where the silicon surface contacts the cobalt is silicided. After the unreacted cobalt on the top of the insulating film or the like is removed, the resulting structure is reheated. As a result, as shown in FIG. 4E, the silicide layer 610 is formed on the gate electrode 605, the source 608, and the drain 609.

As shown in FIG. 4F, a silicon oxide interlayer film 611 is formed. As shown in Fig. 4G, the contact holes 613a and 613b are formed by the predetermined etching of the interlayer film 611 on the source 608 and the drain 609 by dry etching using the resist pattern 612 as a mask. It is formed to reach the silicide layer 610 in position. After the resist pattern 612 is removed, the surface of the silicide layer 610 exposed at the bottom of the contact holes 613a and 613b is washed with dilute hydrofluoric acid or the like.

As shown in FIG. 4H, polysilicon selectively doped with P is deposited on the exposed silicide layer 610 so that contact holes 613a and 613b are embedded to form a plug 614. As shown in FIG. 4I, a plug 614 connected to the silicide layer 610 in another region is formed on the gate electrode 605.

Although not shown, for example, a tungsten silicide wiring connected to the plug 614, such as source electrode wiring and drain electrode wiring, is formed.

However, according to the conventional method, the MOSFET must have heat resistance. When the plug in contact with the source / drain is made of polysilicon, the connection resistance is higher than the plug's original resistance. In this case, as shown in FIG. 4H, the plug 614 is connected to the source 608 through the silicide layer 610. However, regardless of the medium of the silicide layer 610, the resistance of the source electrode wiring connected to the source and the plug increases.

An object of the present invention is to provide a semiconductor device manufacturing method capable of reducing the resistance of a silicon wiring connected to an element formed on a silicon substrate.

1A to 1I are cross-sectional views each illustrating the steps of manufacturing a semiconductor device according to the first embodiment of the present invention.

2 is a graph showing a relationship between a contact resistance and a diameter of a contact hole;

3A to 3I are cross-sectional views each illustrating the steps of manufacturing a semiconductor device according to the second embodiment of the present invention.

4A to 4I are cross-sectional views each illustrating steps of manufacturing a conventional semiconductor device.

※ Explanation of symbols about main part of drawing ※

101: silicon substrate

102: field oxide film

103: impurity region

104: gate insulating film

105: gate electrode

105a: sidewall

106,107: low concentration doping region

108: source

109: drain

110: silicide layer

111: interlayer film

112: resist pattern

113a, 113b: Contact hole

114: plug

In order to achieve the above object, according to the present invention, forming a device comprising a source, a drain and a gate electrode on a silicon substrate, forming an interlayer film on the device, selective to reach the device of the interlayer film Forming a contact hole through which a portion of the device at the bottom of the contact hole is exposed, heating the silicon substrate on which the device and the interlayer film are formed, and forming the contact hole. There is provided a method of manufacturing a semiconductor device, the method comprising forming a wiring member in contact with a portion of the device by being embedded with a conductive material.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First embodiment

1A to 1I show a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

As shown in Fig. 1A, field oxide films 102 are formed on silicon substrate 101 at predetermined intervals. The field oxide film 102 partitions the surface of the silicon substrate 101 to form an element formation region.

In order to adjust the threshold voltage of the transistor, B is ion implanted into each element formation region of the silicon substrate 101 to form the impurity region 103. After the natural oxide film formed on the surface of the element formation region of the silicon substrate 101 is removed with an acidic cleaning solution such as dilute hydrofluoric acid, the gate insulating film 104 is formed as shown in Fig. 1B.

Polysilicon is deposited on the gate insulating film 104 by CVD (chemical vapor deposition). P (phosphorus) is added about 10 ²⁰ cm ^-3 so that the polysilicon is conductive. By using a resist pattern formed by known photolithography as a mask, the polysilicon and the gate insulating film 104 are selectively removed by dry etching using HBr or Cl gas, so that the gate electrode as shown in Fig. 1C. 105 is formed.

P is implanted using the gate electrode 105 as a mask to form the lightly doped regions 106 and 107 in the impurity regions 103 on both sides of the gate electrode 105.

As the insulating film is deposited on the silicon substrate 101 including the gate electrode 105 and removed by vertical anisotropic dry etching, as shown in FIG. 1D, the sidewall 105a is formed on the side of the gate electrode 105. Is formed. As (arsenic) is ion implanted into the lightly doped regions 106 and 107 using the gate electrode 105 and sidewall 105a as a mask, a source 108 and a drain 109 are formed. At the same time, also P (phosphorus) is ion implanted into the gate electrode 105.

Thereafter, a cobalt film is deposited on the silicon substrate 101 including the gate electrode 105 and the sidewall 105a to a thickness of about 15 nm, and heated to about 500 to 600 ° C. (rapid thermal annealing: RTA treatment) . RTA treatment silicides the portion where the silicon surface contacts with cobalt. Unreacted cobalt on top of the insulating film is wet etched using a mixture of hydrofluoric acid and hydrogen peroxide solution. The resulting structure is then subjected to RTA treatment at a temperature higher than the annealing treatment temperature.

As a result, as shown in FIG. 1E, the silicide layer 110 made of an alloy of silicon and cobalt on the gate electrode 105, the source 108 and the drain 109 has a thickness of about 40 to 50 nm. Is formed.

As shown in FIG. 1F, a silicon oxide interlayer film 111 is formed on the silicide layer 110, the sidewalls 105a and the field oxide film 102. As shown in Fig. 1G, the contact holes 113a and 113b are formed by the predetermined etching of the interlayer film 111 on the source 108 and the drain 109 by dry etching using the resist pattern 112 as a mask. It is formed to reach the silicide layer 110 in position.

After the resist pattern 112 is removed, an RTA treatment is performed to heat the resulting structure to 800 ° C. for 10 seconds. The surface of the silicide layer 110 exposed at the bottom of the contact holes 113a and 113b is washed with dilute hydrofluoric acid or the like. The heating is carried out by lamp annealing, for example.

As shown in FIG. 1H, polysilicon doped with P selectively is deposited on the silicide layer 110 exposed at the bottom of the contact holes 113a and 113b so that the contact holes 113a and 113b are buried and plugged. 114 is formed. As shown in FIG. 1I, a plug 114 is also formed on the gate electrode 105 which is connected to the silicide layer 110 in another region.

Although not shown, for example, a tungsten silicide wiring connected to the plug 114, such as source electrode wiring and drain electrode wiring, is formed.

According to the first embodiment, annealing is performed after the contact holes 113a and 113b are formed, and the silicide layer 110 is exposed at the bottom of the contact holes 113a and 113b. After annealing and cleaning, plugs connected to the silicide layer 110 are formed in the contact holes 113a and 113b.

As shown in Fig. 2, when the contact resistance on the source 108 is measured, it is found that the resistance when annealed according to the present invention is lower than the resistance when not annealed according to the conventional method.

In a first embodiment, cobalt silicide is formed. However, the present invention is not limited to this, and other high melting point silicides may be used. For example, the same effect can be obtained by titanium silicide.

Second embodiment

Hereinafter, a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described.

As shown in FIG. 3A, a field oxide film 402 is formed on the semiconductor substrate 401. The surface of the semiconductor substrate 401 in the element formation region partitioned by the field oxide film 402 is exposed.

In order to adjust the threshold voltage of the transistor, B is ion implanted into the semiconductor substrate 401 to form the impurity region 403. After the natural oxide film formed on the exposed surface is removed with an acidic cleaning solution such as dilute hydrofluoric acid, a gate insulating film 404 is formed in the impurity region 403, as shown in FIG. 3B.

After polysilicon having P (phosphorus) added about 10 ²⁰ cm ^-3 is deposited by CVD, tungsten silicide is deposited on polysilicon. The polysilicon and tungsten silicide are selectively removed by dry etching using a resist pattern formed by known photolithography as a mask, so that the polysilicon film 405a and the tungsten silicide film 405b are shown in FIG. 3C. A gate electrode 405 made of is formed.

P is ion implanted using the gate electrode 405 as a mask to form the lightly doped regions 406 and 407 in the impurity regions 403 on both sides of the gate electrode 405. It is to be noted that the present invention is not limited to tungsten silicide and that other high melting point silicides may be used.

As the insulating film is deposited on the silicon substrate 401 including the gate electrode 405 and removed a predetermined amount by vertical anisotropic dry etching, as shown in FIG. 3D, the sidewall 405c on the side of the gate electrode 405 is shown. ) Is formed. As (arsenic) is ion implanted using the gate electrode 405 and the sidewall 405c as a mask to form the source 408 and the drain 409 in the lightly doped regions 406 and 407.

As shown in Fig. 3E, a silicon oxide interlayer film 411 is formed on the semiconductor substrate 401 including the element. As shown in FIG. 3F, the contact holes 413a and 413b are formed by the source 408 and the drain 409 at predetermined positions of the interlayer film 411 by dry etching using the resist pattern 412 as a mask. Is formed to reach. At the same time, as shown in FIG. 3G, the contact hole 413c is formed to reach the tungsten silicide film 405b at a predetermined position of the interlayer film 411.

After the resist pattern 412 is removed, an RTA treatment is performed to heat the resulting structure to 800 ° C. for 10 seconds. The surfaces of the source 408 and the drain 409 exposed to the bottom of the contact holes 413a and 413b and the surface of the tungsten silicide film 405b exposed to the bottom of the contact hole 413c are washed with dilute hydrofluoric acid or the like.

As shown in FIG. 3H, polysilicon doped with P selectively is deposited on the exposed source 408 and drain 409 so that contact holes 413a and 413b are embedded to form plug 414. . At the same time, as shown in Fig. 3I, a P-doped polysilicon plug 414 is formed in the plug 414 on the gate electrode 405 to be connected to the tungsten silicide film 405b.

Although not shown, for example, a tungsten silicide wiring connected to the plug 414, such as source electrode wiring and drain electrode wiring, is formed. In addition, in the second embodiment, the same effects as in the first embodiment can be obtained.

According to the above description, the present invention can suppress the resistance between all or a part of the silicon wiring and a predetermined region of the element to be low.

Claims (8)

Forming an element comprising a source, a drain, and a gate electrode on the silicon substrates 101 and 401, Forming interlayer films 111 and 411 on the device, Selectively forming contact holes 113a, 113b and 413c to reach the device of the interlayer film, thereby forming a contact hole through which a portion of the device at the bottom of the contact hole is exposed; Heating the silicon substrate on which the device and the interlayer film are formed, and Forming a wiring member (114 and 414) in contact with a portion of the device by filling the contact hole with a conductive material. The method of claim 1, further comprising forming silicides (110 and 405b) on the device, The forming of the contact hole includes forming the contact hole in each of the silicide exposed at the bottom, And forming the wiring member comprises forming the wiring member in contact with the silicide formed on the device. The method of claim 1, wherein the forming of the contact hole comprises forming the contact hole in the interlayer film on the source and drain electrodes. The method of claim 1, wherein forming the contact hole comprises forming the contact hole in the interlayer film on the gate electrode. 2. The method of claim 1, further comprising: cleaning the bottom of the contact hole with a cleaning solution containing hydrofluoric acid after heating the silicon substrate. The method of claim 1, wherein the wiring member is a plug-in. Forming an element including a source, a drain, and a gate electrode on the silicon substrate 101, Forming silicide 110 on the drain and the source, Forming an interlayer film 111 on the device comprising the silicide, Selectively forming contact holes 113a and 113b in the interlayer to reach the silicide, thereby forming a contact hole through which the silicide at the bottom of the contact hole is exposed; Heating the silicon substrate on which the device, the silicide and the interlayer film are formed, and Forming a plug (114) in contact with the silicide formed on the source and drain electrodes by filling the contact hole with conductive silicon. Forming an element including a source, a drain, and a gate electrode on the silicon substrate 401, Forming a silicide 405b on the gate electrode, Forming an interlayer film 411 on the device comprising the silicide, Selectively forming a contact hole 413c to reach the gate electrode in the interlayer film, thereby forming a contact hole through which the gate electrode at the bottom of the contact hole is exposed; Heating the silicon substrate on which the device, the silicide and the interlayer film are formed, and Forming a plug (414) in contact with the silicide formed on the gate electrode by filling the contact hole with conductive silicon.