JPH10214946A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for forming no conductor material at a stepped part formed of an upper material having a large pattern size. SOLUTION: The method for manufacturing a semiconductor device comprises the steps of forming a resist mask having a small pattern size and a resist mask having a large pattern size on an upper material film on a semiconductor substrate, forming the mask having the large size in a tapered shape by heat treating the mask, forming the upper material 7 having the tapered shape under the mask having large size by patterning the upper material film by dry etching with the resist mask as an etching ask, and forming a sidewall conductor film 9 only at a sidewall of the material 7 formed under the mask having smaller size by anisotropically dry etching after depositing the film on the entire surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor memory device having a capacitor electrode having a cylinder structure.

[0002]

2. Description of the Related Art Among semiconductor memory devices, there is a DRAM capable of arbitrarily inputting and outputting stored information. Where D
The memory cell of the RAM, which includes one transfer transistor and one capacitor, is structurally simple, and is widely used as the most suitable for high integration of a semiconductor memory device.

In such a memory cell capacitor,
With further increase in the degree of integration of semiconductor devices, those having a three-dimensional structure have been developed and used. And this DR
Stack type capacitors are widely used in AM memory cells having a three-dimensional structure. This stack type has high resistance to the incidence of alpha rays or noise from circuits and the like, and operates stably even when the capacitance value is relatively small. For this reason, the design standard of the semiconductor element is set to 0.
Even in a 4 gigabit DRAM of about 12 μm,
This stacked capacitor (hereinafter, referred to as a stacked capacitor) is considered to be effective. In order to further increase the effective surface area of the capacitor electrode, a cylinder structure has been proposed as the stacked capacitor.

However, in such a process of forming a capacitor electrode having a cylindrical structure, a step portion formed in a semiconductor device, particularly a step portion formed around a semiconductor chip, is provided with a conductor for a capacitor electrode such as a polysilicon film. Material remains. Then, since the remaining conductive material is peeled off in the manufacturing process of the semiconductor device, it becomes a source of particles and lowers the yield of the semiconductor device. Here, such a step portion is formed at an end portion, that is, a contour portion of a pattern such as a wafer alignment mark, a pattern dimension evaluation mark, and a registration measurement mark.

This will be described with reference to FIG. FIG. 5A is a plan view of a step portion where the conductive material remains, and FIG. 5B is a cross-sectional view taken along a line AB shown in FIG. 5A. As shown in FIG. 5, an upper material 102 is formed on a base material 101 by patterning. Then, a step is formed in the contour of the upper material 102. Thereafter, when a conductor material for the capacitor electrode is deposited and subjected to anisotropic dry etching, the sidewall conductor film 103 remains at the step. Further, when the upper material 102 is removed, the sidewall conductive film 103 comes off in a subsequent step.

A method for preventing the conductive material remaining on the stepped portion from peeling is disclosed in Japanese Patent Publication No. 8-31575.

The first method is a method of selectively removing such a conductive material serving as a source of particles by a known photolithography technique and an etching technique.

In the second method, the contour of the upper material that forms the step is formed in a zigzag shape, and the sidewall conductive film formed in such a contour is formed in a zigzag shape. It is a way to do. This will be described with reference to FIG. FIG. 6 is a plan view of a conductive material having a zigzag shape. As shown in FIG.
The two end portions, that is, the contour portion 202a, are formed in a zigzag shape. Thereafter, when a conductor material for the capacitor electrode is deposited and subjected to anisotropic dry etching, the zigzag sidewall conductor film 203 remains at the zigzag step portion.

[0009]

However, in the first method of the prior art described above, a photolithography process for protecting a memory cell region where a capacitor electrode having a cylindrical structure is formed, and an unnecessary conductive material are required. And a dry etching step for removing the metal. For this reason, the manufacturing process of the semiconductor device is increased, and the manufacturing cost is increased.

In the second method described above, since the contour of the pattern of the upper material has a zigzag shape, this method cannot be used depending on the pattern. For example,
The alignment measurement mark pattern needs to be formed so that the amount of deviation between the contour of the vernier pattern formed in the lower layer and the contour of the vernier pattern formed in the upper layer can be measured. Here, when these contours have a zigzag shape, the contours become complicated, and it becomes difficult to automatically measure the above-mentioned shift amount. That is, this method cannot be applied to the pattern of the alignment measurement mark.

Further, in transferring a pattern to a wafer in a photolithography process, as shown in FIG. 7, exposure for transferring the pattern is not performed on the entire wafer 204. That is, a wafer peripheral region 205 which is a region where the pattern is not transferred is formed. Then, a contour portion 205a is inevitably formed between the semiconductor chip region 206 where the exposure shot is made.

In this case, in order to use the above-described conventional technique at a step portion between an exposure shot for forming a pattern in a peripheral portion of a wafer and an exposure shot where a pattern is not formed, the boundary between the exposure shots must be used. Another pattern must be formed. Forming such a pattern at the boundary between shots requires that the margin between shots be at least smaller than the above-mentioned pattern. In this way, it is necessary to reduce the repeat margin of the exposure shot to about 0.5 μm or less, which makes it extremely difficult to manufacture a reticle for photolithography.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a conductive material is not formed on a step formed by an upper material having a large pattern dimension.

[0014]

For this purpose, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming an upper material film for forming a step on a semiconductor substrate, and forming a pattern on the upper material film. Forming a resist mask having a small dimension and a resist mask having a large pattern dimension; and performing a heat treatment on the resist mask to taper the end of the resist mask having the large pattern dimension.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, after forming the resist mask having a small pattern size and the resist mask having a large pattern size and before performing the heat treatment, the resist having the small pattern size may be used. The mask and the resist mask having a large pattern size are irradiated with ultraviolet rays.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, after performing a heat treatment on the resist mask having a small pattern size and the resist mask having a large pattern size,
A step of patterning the upper material film by dry etching using the resist mask as an etching mask to form an upper material having a tapered shape only under the resist mask having a large pattern dimension, and after depositing a conductive material film on the entire surface Forming a sidewall conductor film only on the side wall of the upper material formed under the resist mask having a small pattern dimension by performing anisotropic dry etching.

Here, the length of one side of the resist mask having the large pattern dimension is set to be 4 μm or more.

The sidewall conductive film is formed of D
A capacitor electrode of a memory cell of the RAM is formed.

Further, the upper material having a tapered shape formed by the resist mask having the large pattern dimension constitutes a wafer alignment mark, a pattern dimension evaluation mark, and a registration measurement mark.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2 are sectional views in the order of manufacturing steps for explaining the present invention.

As shown in FIG. 1A, a base material 1 is formed of a silicon oxide film or the like, and an upper material film 2 is deposited on the base material 1. Here, the upper material film 2 has a thickness of 1
It is a BPSG film (silicon oxide film containing boron glass and phosphorus glass) of about μm. Then, a resist mask 3 and a resist mask 4 are formed on the upper material film 2 by a photolithography technique. Here, these resist masks are made of a known positive-type novolak-based photoresist, and have a film thickness of 1 μm to 1.5 μm. Then, a resist mask 3 having a small pattern dimension
Is for forming a capacitor electrode of a memory cell, and its size is about 1 μm × 2 μm. Also,
The resist mask 4 having a large pattern size is for forming patterns such as a wafer alignment mark, a pattern size evaluation mark, and a registration measurement mark.

Next, as shown in FIG. 1B, the entire surface is irradiated with far ultraviolet light 5. This far ultraviolet light 5 has a wavelength of 300 nm.
The following irradiation light is used. In this irradiation, the temperature of the substrate is 1
The irradiation energy and the irradiation time are set at 300 mW / cm @ 2 and about 10 seconds, respectively. By the irradiation of the extra-vision light 5, the surface layers of the resist masks 3 and 4 are thermally cured. Here, the thickness of the heat-cured surface layer is about 200 nm.

Next, heat treatment is performed at a temperature of 140 ° C. and an atmosphere gas of nitrogen. As shown in FIG. 1C, the end of the resist mask 4 having a large pattern dimension becomes tapered by this heat treatment. Here, the taper angle is about 60 degrees. Thus, the tapered resist mask 4
a will be formed. In this case, there is no change in the shape of the resist mask 3 having a small pattern dimension.

The reason why a taper is formed in the resist mask 4 having a large pattern dimension is that a large volume of the non-thermosetting photoresist is apt to generate heat flow during heat treatment. On the other hand, in the case of the resist mask 3 having a small pattern dimension, the photoresist does not undergo heat flow as described above, and remains unchanged. Such pattern size dependence will be described later.

Next, the upper material film 2 is dry-etched using the resist mask 3 and the tapered resist mask 4a as etching masks. By this dry etching, as shown in FIG. 1D, a core oxide film 6 is formed in the region of the resist mask 3 on the base material 1. The upper material 7 is formed in the tapered resist mask 4a region. Here, the upper material 7 has a tapered shape, and its angle is substantially the same as the taper angle of the tapered resist mask 4a.

Next, the resist mask 3 and the tapered resist mask 4a are removed. And FIG.
As shown in (a), a conductor material film 8 is formed on the surfaces of the base material 1, the core oxide film 6, and the upper material 7 by chemical vapor deposition (C).
VD) method. Here, the conductor material film 8 is a polysilicon film containing impurities having a thickness of about 100 nm.

Next, the conductive material film 8 on the entire surface is etched by anisotropic dry etching. That is, etch back is performed. Here, the reaction gas used for the etch back is a mixed gas of CF ₄ and O ₂ . In this way, as shown in FIG. 2B, the sidewall conductor film 9 is formed on the side wall of the core oxide film 6. But,
Such a conductor film is not formed on the side wall of the upper material 7. This is because the taper is formed on the side wall of the upper material 7 and is removed in the etch-back process.

Next, the core oxide film 6 and the upper material 7 are selectively etched away in anhydrous hydrogen fluoride gas. In this way, as shown in FIG. 2C, the sidewall conductor film 9 is selectively formed only in a predetermined region on the base material 1.

In the above embodiment, the resist mask 3
The surface of each of Nos. 4 and 4 was irradiated with extraterrestrial light, and its surface layer was previously thermoset before heat treatment. The effect of this is that the control of the taper angle in the taper formation by the subsequent heat treatment is facilitated. Here, it should be noted that the effect of the present invention is produced even without the irradiation of the far ultraviolet light.

Next, the effects of the present invention and the pattern dimensions of the upper material will be described with reference to FIG. FIG. 3 shows FIG.
9 is a graph showing the relationship between the residual ratio of the sidewall conductive film 9 and the pattern size of the upper material described in FIG.
However, here, the upper material is formed in a square pattern. The resist mask, heat treatment, and the like are as described in the first embodiment.

As can be seen from FIG. 3, when the size of the rectangular pattern of the base material becomes 4 μm or more, the sidewall conductor film 9 shown in FIG. 2B is not formed. This is shown in FIG.
As described in (c), after the heat treatment, the resist mask 4
This is because a sufficient tapered shape is formed. Thus, it can be seen that in the present invention, the pattern size of the resist mask 4 for forming the base material should be set to 4 μm or more.

Next, a case where a memory cell of a DRAM is formed by a stacked capacitor having a cylinder structure according to the present invention will be described as a second embodiment with reference to FIG. FIG. 4 is a diagram schematically showing a cross section of a main part of a semiconductor device at a main point in a manufacturing process. Here, the same components as those described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 4A, first, the LOCO
S (Local Oxidation of Sili)
con), etc., using a normal element isolation method.
1, a field oxide film 12 is formed, and an element active region surrounded by them is formed. Then, the gate electrode 1 on the element active region via the gate oxide film 13 is formed.
4. A MOS transistor including the diffusion layer 15 for capacitance and the diffusion layer 16 for bit lines is formed. The MOS transistor thus formed becomes a transfer transistor of the memory cell.

Next, an interlayer insulating film 17 covering the field oxide film 12 and the gate electrode 14 is formed. Here, the interlayer insulating film 17 is a silicon oxide film deposited by a known chemical vapor deposition (CVD) method. The surface is planarized by a chemical mechanical polishing (CMP) method.

Next, a contact hole is opened on the capacitance diffusion layer 15 of the MOS transistor, and a conductive material film 18 is formed to fill the contact hole. Here, the conductive material film 18 is a polysilicon film having a thickness of about 200 nm, into which impurities such as phosphorus are introduced.

Next, as shown in FIG. 4B, the upper material film 2 is formed on the conductor material film 18. The upper material film 2 is a BPSG film deposited by a CVD method, and its thickness is set to about 1 μm. And
The resist mask 3 is formed so as to have a pattern having a size of 1 μm × 2 μm.

Then, a heat treatment at a temperature of about 140 ° C. is performed. Alternatively, far ultraviolet irradiation is performed prior to this heat treatment step. Thus, the resist mask 3 having a small pattern dimension described in the first embodiment is thermally cured. In such a process, a taper is formed on a resist mask having a large pattern dimension.

Next, the upper material film 2 is dry-etched using the resist mask 3 as an etching mask,
A core oxide film 6 as shown in FIG. 4C is formed. The conductive material film 18 is patterned by using the resist mask 3 as an etching mask to form the lower electrode 19 shown in FIG. Then, the resist mask 3 is removed.

Next, a conductive material film covering the whole is deposited. This conductor material film is a polysilicon film containing a phosphorus impurity or the like and having a thickness of about 100 nm.

Next, the entire surface of the conductive material film is etched back by anisotropic dry etching. Here, the reaction gas used for the etch back is a mixed gas of CF ₄ and O ₂ . In this way, as shown in FIG. 4C, the sidewall conductor film 9 is formed on the side wall of the core oxide film 6.

Although not shown, the core oxide film 6 is selectively etched away in anhydrous hydrogen fluoride gas. Thus, a capacitor electrode having a cylindrical structure is formed. Thereafter, a capacitive insulating film and an upper electrode are formed on the surfaces of the lower electrode 19 and the sidewall conductor film 9 by lamination.

As described above, the gate oxide film 1 of the transfer transistor constituting the memory cell is formed in the active region other than the field oxide film 12 on the surface of the silicon substrate 11.
3. A gate electrode 14, a capacity diffusion layer 15 serving as a source / drain region, a bit line diffusion layer 16, a lower electrode 19 electrically connected to the capacity diffusion layer 15 and serving as an information storage electrode, and a sidewall conductive film. 9, a stack type capacitor having a cylinder structure is formed.

A resist mask having a small pattern size and a resist mask having a large pattern size are formed on the upper material film 2 on such a semiconductor substrate, and the resist mask is subjected to a heat treatment so that an end of the resist mask having a large pattern size is formed. It should be noted that making the taper shape can be applied other than the step of forming the capacitor electrode.

[0044]

As described above, according to the present invention, in the step of forming a capacitor electrode having a cylindrical structure, for example, the taper is automatically formed at the end of the upper material having a large pattern dimension to form a step. Will be formed.

For this reason, in the step of forming the sidewall conductor film, the sidewall conductor film at the end having a large pattern dimension is automatically removed. In addition, a photolithography process and a dry etching process for removing unnecessary conductive material, which are found in the related art, become unnecessary. Then, the manufacturing process of the semiconductor device is shortened, and the manufacturing cost is reduced.

Further, according to the present invention, the contour of the pattern does not have a zigzag shape unlike the prior art. Then, any pattern can be handled.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in the order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a first embodiment of the present invention in a process order.

FIG. 3 is a graph for explaining the effect of the present invention.

FIG. 4 is a cross-sectional view in the order of steps for explaining a second embodiment of the present invention.

5A and 5B are a plan view and a cross-sectional view of a step portion where a conductive material remains, explaining a conventional technique.

FIG. 6 is a plan view of a step portion where a conductive material remains to explain a conventional technique.

FIG. 7 is a plan view of a wafer substrate for explaining a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 Base material 2 Upper material film 3,4 Resist mask 4a Tapered resist mask 5 Far-sighted light 6 Core oxide film 7,102,202 Upper material 8,18 Conductor material film 9,103,203 Sidewall conductor Film 11 Silicon substrate 12 Field oxide film 13 Gate oxide film 14 Gate electrode 15 Diffusion layer for capacitance 16 Diffusion layer for bit line 17 Interlayer insulating film 19 Lower electrode 202 a, 205 a Contour portion 204 Wafer 205 Wafer peripheral region 206 Semiconductor chip region

Claims (6)

[Claims] 1. A step of forming an upper material film for forming a step on a semiconductor substrate, and a step of forming a resist mask having a small pattern size and a resist mask having a large pattern size on the upper material film. And a step of subjecting the resist mask to a heat treatment to form an end of the resist mask having a large pattern dimension into a tapered shape. 2. After forming the resist mask having a small pattern size and the resist mask having a large pattern size, and before performing the heat treatment, the resist mask having the small pattern size and the resist mask having the large pattern size are combined. 2. The method according to claim 1, wherein the semiconductor device is irradiated with ultraviolet rays. 3. A heat treatment is performed on the resist mask having a small pattern dimension and the resist mask having a large pattern dimension, and thereafter, the upper material film is patterned by dry etching using the resist mask as an etching mask. A step of forming an upper material having a tapered shape only under the resist mask, and a sidewall of the upper material formed under the resist mask having a small pattern size by performing anisotropic dry etching after depositing a conductive material film on the entire surface 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a sidewall conductor film only on the semiconductor device. 4. The resist mask according to claim 1, wherein said resist mask having a large pattern dimension has a rectangular shape, and one side thereof has a length of 4 μm or more. A method for manufacturing a semiconductor device. 5. The method according to claim 1, wherein the sidewall conductive film is a DRAM.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the capacitor electrode of the memory cell is formed. 6. The method according to claim 1, wherein the upper material having a tapered shape formed by the resist mask having a large pattern size constitutes a wafer alignment mark, a pattern size evaluation mark, or a registration measurement mark. The method of manufacturing a semiconductor device according to claim 1.