JPH10209308A - Nonvolatile semiconductor memory device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown strength between a source and a drain without scarifying the driving capacity. SOLUTION: This device is provided with n-type source and drain regions 9, leaving a space in the surface region of a p-type silicon substrate 10, and is provided with a floating gate electrode 3 through a gate oxide film 2 on the channel region caught between the source region and the drain region, and is provided with a control gate electrode 5 through an insulating film 4 on the floating gate electrode 3. The distribution of the impurity concentration of the floating gate electrode 3 is thick at the center 3b in the longitudinal direction of the channel, and thin at the part 3a on the side of the source region and the drain region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device of the first conductivity type, in which a source region and a drain region of a second conductivity type are provided at an interval in a surface region of a semiconductor substrate of a first conductivity type, and a gate insulating film is interposed on a channel region. A floating gate electrode is provided,
The present invention relates to a stacked gate nonvolatile semiconductor memory device in which a control gate electrode is provided on a floating gate electrode via an insulating film, and a method for manufacturing the same.

[0002]

2. Description of the Related Art One of the process parameters affecting the electrical characteristics of a stacked gate type memory device having a floating gate electrode is an impurity concentration in the floating gate electrode. The impurity concentration in the floating gate electrode has the following effects on device characteristics.

[0003] First, when the impurity concentration of the floating gate electrode is relatively thick and unit volume per 10 ²⁰ or more, the floating gate electrode acts as a perfect conductor. In this case, since the potential of the control gate electrode is effectively applied to the channel through the floating gate electrode, sufficient driving capability can be secured. This is because the capacitance between the floating gate electrode and the substrate is large.

However, a large capacitance between the floating gate electrode and the substrate means a large capacitance between the floating gate electrode and the drain. This means that the drain voltage is easily transmitted to the floating gate electrode, and the potential of the floating gate electrode is easily increased by the drain voltage. As a result, even if the potential of the control gate electrode is low, a channel is formed under the influence of the drain voltage, and an unintended leak current flows between the source and the drain. That is, if the impurity concentration in the floating gate electrode is high, the withstand voltage between the source and drain of the non-selected bit decreases, and the device may malfunction.

[0005] Therefore, the impurity concentration in the floating gate electrode is relatively thin, less than unit volume per 10 ^20, a depletion layer in the floating gate electrode is formed, the decrease in the source-drain breakdown voltage as described above Does not happen. However, if a depletion layer is formed in the floating gate electrode, it becomes difficult for the potential of the control gate electrode to be transmitted to the channel, and as a result, it becomes difficult to secure sufficient driving capability.

As described above, it is preferable that the impurity concentration in the floating gate electrode is high in order to secure the driving capability. On the contrary, in order to increase the source-drain breakdown voltage, the impurity concentration in the floating gate electrode is high. There is a contradictory demand that the lower is the better.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a stacked gate memory device having a high withstand voltage between source and drain without sacrificing the driving capability of a transistor and a method of manufacturing the same. It is.

[0008]

According to the stacked gate type nonvolatile semiconductor memory device of the present invention, the impurity concentration distribution in the floating gate electrode is deeper at the center in the channel length direction and thinner at the source region side and the drain region side. Has become.

It has been proposed to locally vary the impurity concentration in the floating gate electrode. In these proposals, the impurity concentration is reduced on the substrate side (Japanese Unexamined Patent Publication No.
No. 46374, JP-A-2-295170, JP-A-3-132078, etc.) and those in which the substrate side and the control gate electrode side are thin and the center portion is thick (see JP-A-5-175508) ). The reason why the impurity concentration in the floating gate electrode is reduced on the substrate side is to prevent impurities from being eluted from the polycrystalline silicon film of the floating gate electrode into the gate insulating film to form traps, and The reason why the impurity concentration is reduced on both the substrate side and the control gate electrode side is to improve the data retention characteristics by rounding the edge of the floating gate electrode. Therefore, these proposals have a different configuration from the present invention, and have different purposes.

[0010] As in the present invention, the first aspect of the manufacturing method of making the impurity concentration distribution in the floating gate electrode deeper in the center in the channel length direction and thinner in the source region side and the drain region side is as follows. A floating gate electrode is formed including A) to (E). (A) forming a first-layer polycrystalline silicon film for a floating gate on a semiconductor substrate via a gate insulating film;
Providing a groove in the polycrystalline silicon film to separate adjacent floating gates in the channel width direction;
(B) a step of forming an insulating film on the first polycrystalline silicon film, and further forming a second polycrystalline silicon film for the control gate electrode thereon, and (C) a second polycrystalline silicon film. Forming a resist pattern for forming a control gate electrode on the silicon film, patterning the second polycrystalline silicon film and the insulating film thereunder using the resist pattern as a mask to form a control gate electrode, ( D) Rotational and oblique implantation of impurities at an inclination angle where a region where impurities implanted from the source side and impurities implanted from the drain side coexist exists below the control gate electrode in the first-layer polycrystalline silicon film. (E) Thereafter, using the resist pattern as a mask, the first polycrystalline silicon film is etched to form a floating gate electrode. .

In a second aspect of the manufacturing method for obtaining the impurity concentration distribution in the floating gate electrode as in the present invention, the floating gate electrode is formed by including the following steps (A) to (E). (A) A first-layer polycrystalline silicon film doped with a first conductivity type impurity for a floating gate is formed on a semiconductor substrate via a gate insulating film, and is adjacent to the polycrystalline silicon film in a channel width direction. Providing a trench for separating the floating gates to be formed, (B) forming an insulating film on the first polycrystalline silicon film and further forming a second polycrystalline silicon film for the control gate electrode thereon Process,
(C) A resist pattern for forming a control gate electrode is formed on the second polycrystalline silicon film, and the second polycrystalline silicon film and the insulating film thereunder are patterned using the resist pattern as a mask. (D) forming a region where impurities implanted from the source side and impurities implanted from the drain side coexist below the control gate electrode in the first-layer polycrystalline silicon film. An ion implantation step of obliquely implanting impurities with a non-existent inclination angle; and (E) a step of forming a floating gate electrode by etching the first-layer polycrystalline silicon film using the resist pattern as a mask.

[0012]

FIG. 1D shows a main part of an embodiment of a stack gate type nonvolatile semiconductor memory device according to the present invention. N-type source / drain regions 9 are provided at intervals in a surface region of a P-type silicon substrate 10, and a floating gate electrode is provided on a channel region sandwiched between the source region and the drain region via a gate oxide film 2. 3, and a control gate electrode 5 is provided on the floating gate electrode 3 via an insulating film 4. The impurity concentration distribution of the floating gate electrode 3 is deeper at the central portion 3b in the channel length direction, and thinner at the source region side and drain region side portions 3a.

A first embodiment of the manufacturing method of the present invention will be described with reference to FIGS. (A) P-type silicon substrate 1 having a specific resistance of 10 to 20 Ωcm
0, a field oxide film 1 having a thickness of 500 nm is formed,
The active region separated by the field oxide film 1 has a thickness of 20
A gate oxide film 2 of nm is formed. Next, a first 200 nm thick first layer is formed on the field oxide film 1 and the gate oxide film 2.
Is formed. In the polycrystalline silicon film 3, a groove for separating adjacent floating gates in the channel width direction (perpendicular to the paper surface) is formed by photolithography and etching. Thereafter, an insulating film 4 having a thickness of 20 nm is formed on the polycrystalline silicon film 3, and a second polycrystalline silicon film 5 having a thickness of 200 nm is further deposited thereon. On the polycrystalline silicon film 5, a resist pattern 6 for forming a control gate electrode is formed by photolithography. The insulating film 4 is, for example, an ONO film composed of a silicon oxide film, a silicon nitride film thereon, and a silicon oxide film thereon.

(B) Using the resist pattern 6 as a mask, the polycrystalline silicon film 5 and the insulating film 4 are sequentially etched and patterned. (C) Phosphorus 7, which is an N-type impurity, has an energy of 30 ke.
Rotational ion implantation is performed under the conditions of V, a dose of 1 × 10 ¹⁵ / cm ² and an incident angle θ = 45 °.

(D) Using the resist pattern 6 as a mask, the polycrystalline silicon film 3 is patterned by etching to form a floating gate electrode 3 to complete a stacked gate electrode. Source / drain regions 9 are formed by implanting N-type impurities into the substrate using the stack gate electrode as a mask. As a result, the floating gate electrode 3 has a region 3b with a high impurity concentration at the center in the channel length direction and regions 3a and 3a with a low impurity concentration on both sides in the channel length direction.

The mechanism of the oblique rotation injection in the step (C) will be described in detail with reference to FIG. As shown in FIG. 2A, the impurity 7a is implanted at an angle of 45 ° from the left side and enters right below the control gate electrode 5. As a result, impurity region 8a is selectively formed only in the left half of polycrystalline silicon film 3 for the floating gate electrode. Similarly, as shown in FIG. 2B, impurity region 8b is selectively formed only in the right half of polycrystalline silicon film 3 by impurity 7b implanted from the right side. Here, as shown in FIG. 2C, immediately below the control gate electrode 5,
Since the impurity has been implanted twice into the portion 8 where the impurity regions 8a and 8b overlap, the impurity concentration in that portion is higher than that on both sides.

Now, let the width of the control gate electrode 5 be L
Assuming that the thickness of the polycrystalline silicon film 3 is D, the conditions under which the impurities implanted from both sides of the control gate electrode 5 overlap immediately below the control gate electrode 5 are as follows. This is to incline the incident angle θ in the injection to be equal to or more than the critical angle θ ₀ represented by the following equation (1). θ ₀ = tan ⁻¹ (L / 2D) (1) That is, each inclination θ of the ion implantation in this embodiment is θ ≧ θ ₀ .

FIG. 3 shows a second embodiment of the manufacturing method of the present invention.
This will be described with reference to (A) to (C). 1A and 1B are the same as the embodiment of FIG. 1 except that the polycrystalline silicon film 3 is preliminarily doped with an impurity, for example, phosphorus or arsenic at a high concentration. (C) An impurity of a conductivity type opposite to the conductivity type of the impurity previously doped into the polycrystalline silicon film 3, for example, boron is applied at an energy of 30 keV and a dose of 1 × 10
Rotational ion implantation is performed under the conditions of ¹⁵ / cm ² and an incident angle θ = 10 °.

At this time, the inclination angle θ of the ion implantation is small (θ <θ ₀ ), so that the ions implanted from the left and right in the channel length direction do not overlap in the region directly below the control gate electrode 5. That is, as shown in (C-1), the impurities implanted from both sides are the same as the impurities doped in advance and the impurities of the opposite conductivity type implanted later in the regions 8a and 8b into which the impurities are implanted. Offset each other's carriers, so that the electrical impurity concentration is reduced. That is, as shown in (C-2), in the portion immediately below the control gate electrode 5, no carrier cancellation occurs in the intermediate portion 8 between the impurity injection regions 8a and 8b. Is higher than the impurity concentration of the portions 8a and 8b. Thereafter, similarly to the embodiment of FIG. 1, the polysilicon film 3 is patterned to form a floating gate electrode, thereby completing a stacked gate electrode. Impurities are implanted into the substrate using the stack gate electrode as a mask to form source / drain regions.

[0020]

According to the memory device of the present invention, since the impurity concentration in the floating gate electrode is reduced on the drain side, the capacitance between the floating gate electrode and the drain can be reduced. As a result, the potential of the floating gate electrode does not increase due to the drain voltage, and the problem that an unintended leak current flows between the source and the drain hardly occurs. Since the impurity concentration in the floating gate electrode is higher at the center in the channel length direction, the potential of the control gate electrode is effectively applied to the channel through the floating gate electrode. As a result, a sufficient driving capability can be ensured. As described above, it is possible to obtain a stack-gate type memory device having both high driving capability and high source-drain withstand voltage, which were conventionally difficult to realize. According to the manufacturing method of the present invention, the concentration distribution of the floating gate electrode can be formed at a time by ion implantation, and the manufacturing is easy.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a first embodiment of a manufacturing method.

FIG. 2 is a process sectional view showing an ion implantation process in the embodiment.

FIG. 3 is a process sectional view showing a second embodiment of the manufacturing method,
FIG. 4 is a cross-sectional view showing the ion implantation mechanism.

[Explanation of symbols]

Reference Signs List 2 Gate oxide film 3 Polycrystalline silicon film for floating gate electrode 4 Insulating film 5 Polycrystalline silicon film for control gate electrode 6 Resist pattern 7 Implanted ions 3a, 8a, 8b Low-concentration portion of floating gate electrode 3b, 8 High concentration part 9 Source / drain region 10 Silicon substrate

Claims (3)

[Claims] 1. A source region and a drain region of a second conductivity type are provided at intervals on a surface region of a semiconductor substrate of a first conductivity type, and a floating gate electrode is provided on a channel region via a gate insulating film. In a stack gate type nonvolatile semiconductor memory device in which a control gate electrode is provided on a floating gate electrode via an insulating film, the impurity concentration distribution in the floating gate electrode is:
A non-volatile semiconductor memory device characterized by being darker at a central portion in a channel length direction and thinner at a source region side and a drain region side. 2. A method for manufacturing a nonvolatile semiconductor memory device, comprising forming a floating gate electrode including the following steps (A) to (E). (A) forming a first-layer polycrystalline silicon film for a floating gate on a semiconductor substrate via a gate insulating film;
Providing a trench in the polycrystalline silicon film to separate floating gates adjacent in the channel width direction; (B) an insulating film on the first polycrystalline silicon film, and further thereon a control gate electrode Forming a second-layer polycrystalline silicon film; (C) forming a resist pattern for forming a control gate electrode on the second-layer polycrystalline silicon film, and using the resist pattern as a mask to form a second-layer polycrystalline silicon film; Forming a control gate electrode by patterning the polycrystalline silicon film and the insulating film thereunder; (D) a portion of the first polycrystalline silicon film below the control gate electrode and implanted from the source side An ion implantation step of rotating and obliquely implanting the impurity at an inclination angle in which a region where the impurity and the impurity implanted from the drain side coexist exists; Forming a floating gate electrode by etching the first polycrystalline silicon film using the turn as a mask. 3. A method for manufacturing a nonvolatile semiconductor memory device, comprising forming a floating gate electrode including the following steps (A) to (E). (A) A first-layer polycrystalline silicon film doped with a first conductivity type impurity for a floating gate is formed on a semiconductor substrate via a gate insulating film, and is adjacent to the polycrystalline silicon film in a channel width direction. (B) forming an insulating film on the first polycrystalline silicon film, and further forming a second polycrystalline silicon film for the control gate electrode thereon. (C) forming a resist pattern for forming a control gate electrode on the second-layer polycrystalline silicon film and using the resist pattern as a mask to form a second-layer polycrystalline silicon film and an insulating film thereunder; Forming a control gate electrode by patterning; (D) an impurity and a drain implanted from the source side below the control gate electrode in the first polycrystalline silicon film Ion implantation step of rotating and obliquely implanting impurities at an inclination angle where there is no region where impurities implanted from the substrate coexist. (E) After that, the first polycrystalline silicon film is etched by using the resist pattern as a mask and floating. Forming a gate electrode;