JPH0560670B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a floating gate type nonvolatile semiconductor memory device that can be made smaller in area.

[Prior Art] A static induction transistor (SIT) is known as a transistor that consumes little power and operates at high speed. In conventional nonvolatile semiconductor memory devices using MNOS and MONOS floating gates, the sources, operating regions, drains, electron trap layers, control gates, etc. that make up individual memory elements are placed laterally on the surface of the semiconductor substrate. It is arranged and formed. For this reason, each memory element on the semiconductor substrate occupies a large area, making it difficult to achieve high integration.

[Problems to be Solved by the Present Invention] The present invention is directed to a highly integrated SIT (in this specification, vertical channel MIS static induction transistor,
Refers to a vertical bulk channel MIS transistor. The purpose of this invention is to provide MNOS type and MONOS type nonvolatile semiconductor memory devices.

[Means for Solving the Problems] A nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate of a first conductivity type, and a second semiconductor substrate formed on the surface of the semiconductor substrate and serving as one of a drain region and a source region. a conductive type impurity buried layer; a second conductive type epitaxial layer formed on the surface of the impurity buried layer; and an actuator extending vertically from the surface of the epitaxial layer to the impurity buried layer. In order to define a region from the epitaxial layer, an insulating barrier wall surrounding the active region and extending vertically from the surface of the epitaxial layer to the impurity buried layer, and a tunneling effect on the active region are provided. a silicon nitride layer extending vertically from the surface of the epitaxial layer to the impurity buried layer while separating a silicon oxide film having a thickness that allows the formation of a silicon oxide film, and between the insulating partition wall and the silicon nitride layer; at least one control gate extending vertically from the surface of the epitaxial layer to the impurity buried layer while separating the silicon oxide film and the silicon nitride layer from the operating region;
The device is characterized in that it has a second conductivity type impurity region formed on the surface of the operating region and serving as the other of the drain region and the source region.

That is, in the nonvolatile semiconductor memory device of the present invention, a drain, an active region, a silicon nitride layer, a control gate, and a source constituting each memory element are arranged in the thickness direction of the semiconductor substrate, that is, in the vertical direction. This increases the integration density of memory elements.

The semiconductor substrate constituting the nonvolatile semiconductor memory device of the present invention may be of either P type or N type, and the type of the semiconductor substrate is referred to as a first conductivity type in the present invention.

A second conductivity type impurity buried layer is formed on the surface of the semiconductor substrate. Here, the second conductivity type is the first conductivity type.
It means a conductivity type that is the opposite of a conductivity type. That is, when the first conductivity type is P type, the second conductivity type is N type.

A second conductivity type epitaxial layer is formed on this impurity buried layer. The thickness of the epitaxial layer is 2 to 10 μm, and the impurity concentration is 1×10 ¹⁴ to
It is about 5×10 ¹⁴ cm ^-3 .

An active region is formed in this epitaxial layer. Practically speaking, it is preferable to form a large number of active regions for one buried layer. The active region is substantially defined and formed by so-called vertically formed oxide partition walls extending from the surface of the epitaxial layer toward the buried layer. This insulating barrier wall extends from the surface of the epitaxial layer to the impurity buried layer, and substantially divides the epitaxial layer into each operating region.

A silicon nitride layer and a control gate are formed substantially within this insulating barrier. The silicon nitride layer is a thin film extending vertically from the active region through an oxide layer (20 to 100 Å) thick enough to cause a tunnel effect. The silicon nitride layer may be formed continuously over all portions of the oxide barrier surrounding the active region.

A control gate is formed within the insulator barrier in a portion of the silicon nitride layer opposite the adjacent active region. This control gate is typically formed of polycrystalline silicon. A plurality of control gates, such as two, four, etc., can be provided for one operating region. Each control gate needs to be arranged in parallel in the vertical direction. Note that even when a plurality of control gates are provided for one operating region, the silicon nitride layer may be one continuous layer. However, a silicon nitride layer must be present between each control gate and the active region. It is also preferable to interpose an oxide layer between the control gate and the silicon nitride layer as in the normal MONOS type. In this case, the thickness of the oxide layer is preferably about several tens of angstroms.

An impurity region serving as the other of the source region and the drain region is formed in the surface portion of the active region.

Further, in order to ensure conductivity between the impurity buried layer and the substrate surface, an impurity region is formed on the surface of the epitaxial layer in a portion other than the operating region. Note that the surface of the epitaxial layer and each impurity region are covered with an oxide layer, and an aluminum electrode is formed in a portion penetrating this oxide layer. Note that it is preferable to provide an insulating film that is thin enough to cause a tunnel effect between either the drain or source electrode and the impurity region adjacent to that electrode. This tunnel insulating film eliminates leakage current during cut-off between the source and drain, resulting in high impedance.

Note that although a SiO ₂ film is generally used as the insulating film, other films such as Al ₂ O ₃ , Si ₃ N ₄ and composite films thereof can also be used.

[Operation of the device of the present invention] In the nonvolatile semiconductor memory device of the present invention, one of the impurity buried layer and the impurity region formed in the active region is used as a source, and the other is used as a drain. To write to the silicon nitride layer, apply a positive voltage to the control gate adjacent to the silicon nitride layer where you want to write, and ground the other source and drain to create a tunnel from the active region to the silicon nitride layer adjacent to the control gate. A tunnel current flows through the oxide film, and electrons are accumulated between the silicon nitride layer and the oxide layer, forming an electron trap layer. Since the electron trap layer is entirely surrounded by an insulating portion such as a silicon nitride layer or an oxide film, the electrons in the electron trap layer are retained in the electron trap layer without escaping. In other words, it becomes non-volatile.

To erase an electron trap layer, set only the control gate adjacent to the electron trap layer to be erased to a low potential, and set the other control gates, source, and drain to a high potential. Electrons flow from the tunnel oxide to the active region. This allows the electron trap layer to be erased. Note that in order to erase all electron trap layers, all control gates are set to a low potential, and all sources and drains are set to a high potential, so that electrons flow out from all electron trap layers and all electron traps are erased. You can erase layers.

When electrons are stored or written into the electron trap layer, electrostatic induction in the electron trap layer creates a depletion layer in the adjacent active region.
This increases the resistance in the active region and increases the electrical resistance flowing from the source to the drain. If the silicon nitride layer is not written, no depletion layer is formed in the active region. Therefore, the electrical resistance between the source and drain is small. Due to this difference in resistance, one control gate and the adjacent silicon nitride layer have two
signals can be extracted.

Embodiment 1 FIGS. 1 and 2 show cross sections of essential parts of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 1 is a longitudinal cross-section, and FIG. 2 is a cross-section taken along the line A--A in FIG. This device consists of a P-type silicon substrate 1, an N-type impurity buried layer 2 formed in a certain area of this silicon substrate 1, an N-type epitaxial layer 3 formed on the surface of this silicon substrate 1, and this epitaxial layer 3. It is composed of an oxide layer 4 and the like that define an operating region 31 . A conductive region 32 is formed inside this oxide layer to ensure conductivity between the impurity buried layer 2 and the surface of the epitaxial layer 3. In the oxide layer 4, in contact with each operating region 31 and the impurity buried layer 2,
A tunnel oxide film 41 constituting a part of this oxide layer 4 is continuously formed to a thickness that produces a tunnel effect. Furthermore, a silicon nitride layer 5 is provided in contact with this tunnel oxide film 41. Control gates 61, 61 and 61, respectively, are in contact with the surface of the silicon nitride layer 5 that extends in the vertical direction and is opposite to each operating region 31.
62, 63, and 64 are provided. An oxide layer 42 forming a partition wall is provided between adjacent control gates 61 and 62 and 63 and 64. N-type impurity regions 71 , 72 , and 73 are formed on the upper surfaces of the operating region 31 and the conductive region 32 . The control gates 61, 62, 63, and 64 are each connected to a wiring pattern and covered with a protective insulating film 43 formed on the surface thereof. impurity region 71,
72 and 73 are connected to electrodes 91, 92, and 93 through contact holes provided in the protective insulating film 43, the silicon nitride layer 5, and the thermal oxide film 44. The nonvolatile semiconductor memory device of this embodiment is configured as described above.

Next, a method for manufacturing the nonvolatile semiconductor memory device of this embodiment will be explained with reference to FIGS. 3 to 9. First, as shown in FIG. 3, a (100) P type silicon substrate 1
An N-type impurity buried layer 2 is formed in a predetermined region by diffusing Group V elements (As, P, Sb) (6 to 8 Ωcm). After that, N type 1×10 ¹⁴ cm ^-3 ~ 5×10 ¹⁴ cm
^-3 epitaxial layer 3 is grown to a thickness of 2 to 10 μm. Next, in order to electrically isolate each region, as shown in FIG. 4, grooves are dug in the silicon substrate 1 and epitaxial layer 3, and SiO ₂ is formed by CVD method for isolation, and an oxide layer 4 is formed. Form. After that, as shown in Figure 5, the surface of the epitaxial layer 3 is oxidized in a steam atmosphere at 1000℃.
A thermal oxide film (SiO ₂ ) 44 of 0.8 to 1.0 μm is formed.
Then, a resist pattern 48 is formed in the area where the groove 35 is to be formed using commonly used photolithography and etching techniques, and then reactive ion etching, ion milling, reactive ion milling, etc. are performed using this resist pattern 48 as a mask. A thermal oxide film 4 is formed by anisotropic etching.
4, and then selectively anisotropically etching the epitaxial layer 3,
Etching is continued until the bottom of the etching reaches the impurity buried layer 2, forming a groove 35. This state is shown in the cross section of FIG.

Next, the resist pattern 48 is removed and the inside of the groove 35 is thermally oxidized in dry oxygen at 1000°C to 1050°C.
The inner wall surface and bottom surface of the trench 35 are oxidized to a thickness of 500 to 1000 Å, and then this thermal oxide film is removed. By performing this oxidation and removal, stains caused by reactive ion etching and roughness of the etched surface are removed. The epitaxial layer 3 continues with the silicon surface of the groove 35 exposed.
A so-called tunnel oxide film 41 having a thickness of 20 to 100 Å is formed on the side surfaces of the impurity buried layer 2 and the top surface of the impurity buried layer 2 by oxidizing in dry oxygen diluted with argon. Next, thermal CVD was performed at approximately 800°C using silicon chloride (SiCl ₄ ) or silane (SiH ₄ ) and ammonia (NH ₃ ) as the source and a mixed gas of nitrogen and hydrogen as the carrier gas.
A silicon nitride film 5 of 500 to 1000 Å is formed over the entire surface.
This state is shown in FIG.

Next, an N ⁺ type polycrystalline silicon layer containing a large amount of arsenic or phosphorus is deposited over the entire surface by LPCVD so as to fill the groove 35 in which the trannel oxide film 41 and the silicon nitride film 5 have been formed.

Next, the upper polycrystalline silicon layer is removed by an etch bag method until the surface of the thermal oxide film 44 formed on the surface by reactive ion etching or the like is partially exposed, thereby forming a wiring pattern. Subsequently, the polycrystalline silicon layer is etched to form a second groove 36 in the same manner as the groove 35 described above was formed. At this time, the control gates 61, 62, 63,
64 is formed. The state is shown in FIG.

Next, an oxidized layer 42 is deposited in the second trench 36, and a protective insulating film 43 is further deposited. Thereafter, contact holes for electrical connection are formed, and impurities are ion-implanted into predetermined regions from the contact holes to form N ⁺ impurity regions 71, 72, and 73.

Next, a generally used aluminum vapor deposition layer is formed in the contact hole portion, and electrodes 91, 92, 9 including wiring layers are formed by photolithography and etching.
form 3. In this manner, the nonvolatile semiconductor memory device of this embodiment shown in FIG. 1 is manufactured.

Note that these N ⁺ impurity regions 71, 72, 73 are
The polycrystalline silicon layer 50 shown in FIG. 7 can also be formed in an etched-back state.
Furthermore, before forming the second groove 36, the silicon nitride film 5 oxide film 44 on the surface is removed and the surface is smoothed by a so-called selective oxidation method (LOCOS method), etc. So-called normal
MOS transistors can also be formed in the epitaxial layer 3 region and P-type isolation (not shown). At this time, P-type isolation is
It may be formed at the concentration of Pwell.

In this embodiment, the device formed as described above is a so-called
Used as EEPROM.

An example of the operation of this embodiment is shown in FIG. FIG. 8 shows a write operation in which a positive (+) voltage is applied to the control gate 63 capacitively coupled to the portion of the silicon nitride layer 5 to which writing is desired. All other control gates 61, 62, 63, 64 and all electrodes 91, 92, 93 are grounded. As a result, a tunnel current flows through the tunnel oxide film 41 between the control gate 63 and the operating region 31, and electrons are accumulated in the portion between the tunnel oxide film 41 and the silicon nitride layer 5, forming an electron trap layer 411. Ru. As a result, even if no voltage is applied to the control gate 63, the depletion layer 31a extends to the operating region 31 as shown in FIG. 9 due to the charge generated by the electrons in the electron trap layer 411. The extent of this depletion layer 31a is determined by the amount of electrons in the electron trap layer 411. Further, when a large amount of electrons are written, the expansion of this depletion layer 31a becomes a certain value. This is the width of a depletion layer when an inversion layer is formed in a so-called MOS diode, and this width Xd-max is expressed by the following equation.

Here, Nd is the concentration of the epitaxial layer 3 in this embodiment. For example, epitaxial layer 3 is 1
When ×10 ¹⁴ cm ^-3 , Xd−max=2.7μm, 1×10 ¹⁵
When cm ^-3 , Xd-max=1.0 μm.

As in this example, two
When an EEPROM is used and an epitaxial layer of 1×10 ¹⁴ cm ^-3 is used, if the distance of the silicon nitride layer portion of the control region 31 is, for example, 4 μm, then
An electron trap layer is formed in the two parts, and when electrons are written, a depletion layer extends from both parts, and by pinching each other, the impurity buried layer 2 and the impurity region 72 formed in the contact part are cut off, and current no longer flows. FIG. 9 shows a state in which an electron tracking layer 411 is formed only in the portion of the silicon nitride layer 5 that is capacitively coupled to one control gate 63, and electrons are written therein. In this state, the resistance of the operating region 31 is The current will flow, although it will be higher.

Next, the case of erasing the EEPROM of this embodiment will be explained. FIG. 10 shows the state when the electron trap layer 411 is erased. That is, only the control gate 63 of the portion to be erased is set to, for example, 0 volt, and the control gates 61, 62, 64 and all other electrodes 91, 92, 93 are set to a high potential. As a result, electrons flow from the electron trap layer 411 to the active region 31 as a tunnel current and are erased.

In the nonvolatile semiconductor memory device of this embodiment, two control gates 62 and 6 are provided in one operating region 31.
3, each having a silicon nitride layer 5 with a tunnel oxide film 41 separating the operating region corresponding to the control gate. For this reason, if the silicon nitride layer 5 of any of the control gates 62 and 63 in one operating region 31 is not written (0, 0), the silicon nitride layer 5 of only one control gate 62 is written. If the electron trap layer is formed and written (1, 0),
If an electron trap layer is formed and written in a portion of the silicon nitride layer 5 of only one other control gate 63 (0, 1), and two control gates 6
In the case where an electron trap layer is formed on the silicon nitride layer 5 of 2 and 63 and written together (1, 63).
1) can store four states.

The stored state can be detected by applying a voltage to the capacitively coupled control gate and detecting the change in resistance between the source and drain. For example, when an electron trap layer is formed and written, even if a voltage is applied to the control gate capacitively coupled to the electron trap layer, the change in resistance between the source and drain is small. On the other hand, if the electron trap layer is not formed and written to, the resistance between the source and drain increases significantly when a voltage is applied to the control gate. In this way, it is possible to detect whether or not data has been written in correspondence with each control gate, and it can be used as a storage device.

In the first embodiment, two control areas are provided for one control area.
It has several control gates. The number of control gates may be one or more depending on the application. For example, as shown in FIG. 11, four control gates 62, 63,
66 and 67 can be provided. In addition, the 11th
The figure is a sectional view corresponding to FIG. 2 of the first embodiment, and is a partial cross-sectional view of the center of one operating region of the nonvolatile semiconductor memory device.

Embodiment 2 FIGS. 12 and 13 show longitudinal sectional views of essential parts of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. The nonvolatile semiconductor memory device of this embodiment has almost the same structure as the nonvolatile semiconductor memory device of the first embodiment, and includes a silicon nitride layer 5, each control gate 61, 62,
The only difference is that an oxide film 45 is provided between 63 and 64. Note that the same reference numerals indicating the same parts as in the first embodiment are used in the second embodiment as well. After the silicon nitride layer 5 is formed, this oxide film 45 is formed on the control gates 61 and 6.
Before forming layers 2, 63, and 64, a SiO ₂ film is formed on the surface of silicon nitride layer 5 by thermal oxidation.
Since this oxide film 45 has certain absolute characteristics, the electron trap layer formed between the silicon nitride layer 5 and the tunnel oxide film 41 can more reliably hold electrons, and the silicon nitride layer 5 can be It can be made thinner and the amount of writing can be increased.

[Brief explanation of the drawing]

1 and 2 show a nonvolatile semiconductor memory device according to a first embodiment of the present invention, FIG. 1 is a vertical sectional view of the main part thereof, and FIG. 2 is a sectional view taken along the line A-A in FIG. 1. ,
3 to 7 are cross-sectional views showing the main parts of the device for each main process when manufacturing the nonvolatile semiconductor memory device of the first embodiment, and FIG. 4 is a sectional view when an oxide layer is formed, FIG. 5 is a sectional view when a groove for forming a silicon nitride layer is formed, and FIG.
The figure is a cross-sectional view when a tunnel oxide film and a silicon nitride layer are formed in the trench, FIG. 7 is a cross-sectional view when a second trench for forming a control gate is formed, and FIG.
10 to 10 show the operating state of the nonvolatile semiconductor memory device of the first embodiment, FIG. 8 is a sectional view showing the wiring at the time of writing, FIG. 9 is a sectional view showing the state of the wiring at the time of detection, FIG. 10 is a cross-sectional view showing the wiring state during erasing. FIG. 11 shows a main part of a modification of the first embodiment, and is a cross-sectional view of the operating area. 12 and 13 show a nonvolatile semiconductor memory device of the second embodiment, and FIG. 12 is a vertical cross-sectional view of main parts;
FIG. 13 is a sectional view taken along the line A-A in FIG. 12. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Impurity buried layer, 3... Epitaxial layer, 31... Operating region, 11... Oxide layer, 41... Tunnel oxide film, 5... Silicon nitride layer, 61, 62 , 63, 64...control electrode, 7
1, 72, 73... impurity region.

Claims (1)

[Claims] 1: a semiconductor substrate of a first conductivity type; a buried impurity layer of a second conductivity type formed on the surface of the semiconductor substrate and serving as one of a drain region and a source region; and the implanted impurity layer. an epitaxial layer of a second conductivity type formed on the surface of the layer; and an operating region extending in the vertical direction from the surface of the epitaxial layer to the impurity buried layer, in order to define from the epitaxial layer, an insulating barrier wall that surrounds the operating region and extends vertically from the surface of the epitaxial layer to the impurity buried layer; and a silicon oxide film having a thickness that allows a tunnel effect to occur in the operating region. a silicon nitride layer extending vertically from the surface of the epitaxial layer to the impurity buried layer; and a silicon oxide film interposed between the insulating partition wall and the silicon nitride layer and directed to the active region. and at least one control gate extending vertically from the surface of the epitaxial layer to the buried impurity layer while leaving the silicon nitride layer; and the drain region and the source region formed on the surface of the operating region. a second conductivity type impurity region, the other of which is a second conductivity type impurity region. 2. The nonvolatile semiconductor memory device according to claim 1, wherein an oxide layer is interposed between the silicon nitride layer and the control gate. 3. Claim 1, wherein two control gates are provided with respect to the operating area defined by the insulating partition walls, with the operating area as a center of symmetry.
Or the nonvolatile semiconductor memory device according to item 2. 4. Claim 1, wherein four control gates are provided with respect to the operating area defined by the insulating partition walls, with the operating area as the center of symmetry.
Or the nonvolatile semiconductor memory device according to item 2. 5. The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the impurity buried layer constitutes a common region of one of the drain region and the source region. 6. The non-volatile device according to claim 1 or 2, which has an electrode formed through an insulating film having a thickness that allows a tunnel effect to occur with respect to the impurity region formed on the surface of the operating region. semiconductor memory device.