JPS6240774A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To enhance the integrated density of memory cells by arranging a drain, an operating area, a silicon nitride layer, a control gate and a source for forming a memory cell in the thicknesswise direction of a substrate. CONSTITUTION:Control gates 61-64 are formed in contact with the opposite side face to an operating region 31 in a portion extending longitudinally of a silicon nitride layer 5, and oxide layers 42 for forming partition walls are formed among adjacent control gates 61, 62 and 63, 64. N-type impurity regions 71-73 are formed on the upper surface of the operating and conductive regions 31, 32. The gates 61-64 are connected with wiring patterns, and coated on a protective insulating film 43 formed on the surface. The regions 71-73 are connected with electrodes 91-93 through contacting holes formed at the film 43, the layer 5 and a thermal oxide film 44.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to a floating gate type non-volatile semiconductor memory device that enables a reduction in area. IJ″tjru.

BACKGROUND ART A static induction transistor (SIT) is known as a transistor with low power consumption and high operating speed.

In conventional nonvolatile semiconductor memory devices using MNOS type and MONO8 type floating gates, the sources, operating regions, drains, electron trap layers, and
Control gates and the like are formed in horizontal alignment on the surface of the semiconductor substrate. For this reason, each memory element on the semiconductor substrate occupies a large area, making it difficult to achieve high integration.

[Problems to be solved by the present invention] The present invention is a highly integrated SIT that can be used for MNOS type and UMON type.
An object of the present invention is to provide an O8 type nonvolatile semiconductor memory device.

[Means for Solving the Problems] A nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate of a first conductivity type, and a second conductivity type semiconductor substrate formed on the surface of the semiconductor substrate, which is one of a drain region and a source region. forming a conductivity type impurity buried layer, a second s conductivity type epitaxial layer formed on the surface of the impurity buried layer, and an operating region extending from the surface of the epitaxial layer in the lateral direction of the impurity buried layer; an oxide partition extending in the vertical direction of the impurity buried layer from the surface of the epitaxial layer surrounding the operating region, and a silicon oxide film extending in the longitudinal direction to an extent that causes a tunnel effect in the operating region; a silicon nitride layer disposed within an oxide barrier; at least one control gate extending longitudinally within the oxide barrier on a side of the silicon nitride layer opposite the actuation region; and a surface of the actuation region. A second conductivity type impurity region is formed in the region and serves as the other of the drain region and the source region.

That is, in the nonvolatile semiconductor memory device of the present invention, a drain, an active region, a silicon nitride layer, a control gate, and a source constituting each memory element are arranged in the thickness direction of the semiconductor substrate, that is, in the vertical direction. This increases the integration density of memory elements.

The semiconductor substrate constituting the nonvolatile semiconductor memory device of the present invention may be of either P type or N type, and the type of the semiconductor substrate is referred to as a first conductivity type in the present invention.

No. 21 on the surface of this semiconductor substrate! An ffi type impurity buried layer is formed. Here, it means a conductivity type that is symmetrical to the second conductivity type and the first conductivity type. That is, the first conductivity type is P.
type, the second conductivity type is N type.

A second s-type epitaxial layer is formed on this impurity buried layer. The thickness of the epitaxial layer is 2-10
μ. The impurity concentration is about 1×10 14 to 5×10 40 m −3 .

An active region is formed in this epitaxial layer. Practically speaking, it is preferable to form a large number of active regions for one buried layer. The active region is substantially defined and formed by so-called vertically formed oxide partition walls extending from the surface of the epitaxial layer toward the buried layer. This insulating barrier wall extends from the surface of the epitaxial layer to the impurity buried layer.
A substantially epitaxial layer is defined into each active region.

The silicon nitride layer and control gate are substantially
□It is formed inside the bulkhead. The silicon nitride layer is made of oxide m(2
It is a membrane-like structure that extends vertically and separates 0 to 100 people. The silicon nitride layer may be formed continuously over all portions of the oxide barrier surrounding the active region.

A control gate is formed within the insulator barrier in a portion of the silicon nitride layer opposite the adjacent active region. This control gate is typically formed of polycrystalline silicon. 1'IgA
A plurality of 11911s such as 2, 4, etc. for the operating area of
A gate can be provided. Each control gate needs to be arranged in parallel in the vertical direction. Note that even when a plurality of control gates are provided for one operating region, the silicon nitride layer may be one continuous layer. However, a silicon nitride layer must be present between each control gate and the active region. It is also preferable to interpose an oxide layer between the control gate and the silicon nitride layer as in the normal MONO8 type. In this case, the thickness of the oxide layer is preferably about several tens of amps.

An impurity region serving as the other of the source region and the drain region is formed in the surface portion of the active region.

Further, in order to ensure conductivity between the impurity buried layer and the substrate surface, an impurity region is formed on the surface of the epitaxial layer in a portion other than the operating region. Note that the surface of the epitaxial layer and each impurity region are covered with an oxide layer, and an aluminum electrode is formed in a portion penetrating this oxide layer. In addition,
It is preferable to provide an insulating film that is thin enough to cause a tunnel effect between either the train or source electrode and the impurity region adjacent to that electrode. This tunnel insulating film eliminates leakage current during cutoff between the source and drain, resulting in high impedance.

Note that although a Sio2 film is generally used as the insulating film, other films such as AitO3, Si3N4, and composite films thereof can also be used.

[Operation of the device of the present invention] In the nonvolatile semiconductor memory device of the present invention, one of the impurity buried layer and the impurity region formed in the active region is used as a source, and the other is used as a drain. The aging of the silicon nitride layer can be done by applying a positive voltage to the control gate adjacent to the silicon nitride layer where you want to write, and by grounding the other sources and drains. A tunnel current flows through the tunnel oxide film, and electrons are accumulated between the portion of the silicon nitride layer and the oxide layer, forming an electron trap layer. Since the electron trap layer is entirely surrounded by an insulating portion such as a silicon nitride layer oxide film, the electrons in the electron trap layer are retained in the electron trap layer without escaping. In other words, it becomes non-volatile.

To erase an electron trap layer, set only the control gate adjacent to the electron trap layer to be erased to a low potential, and set the other control gates, source, and drain to a high potential. Electrons flow from the tunnel oxide to the active region. This allows the electron trap layer to be erased. Note that in order to erase all electron trap layers, all control gates are set to a low potential and all sources and drains are set to a high potential, so that electrons flow out from all electron trap layers and all electron traps are erased. You can erase layers.

When electrons are stored or written into the electron trap layer, static iI induction in the electron trap layer creates a depletion layer in the adjacent active region.

This increases the resistance in the active region and increases the electrical resistance flowing from the source to the drain. If the silicon nitride layer is not written, no depletion layer is formed in the active region. Therefore, the electrical resistance between the source and drain is small. Due to this difference in resistance, two signals can be extracted from one control gate and the adjacent silicon nitride layer.

[Embodiment 1] FIGS. 1 and 2 show cross sections of essential parts of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 1 is a longitudinal cross-section, and FIG. 2 is a cross-section taken along the line A--A in FIG. This device has a P-type silicon substrate 1.

N-type impurity implantation 1t2 formed in a certain range of the silicon substrate 1, an N-type epitaxial layer 3 formed on this surface, an oxide layer 4 dividing this epitaxial layer 3 into each operating region 31, etc. It is configured. An impurity buried layer 2 and an epitaxial layer W! are formed inside this oxide layer. A conductive region 32 is formed to ensure conductivity with the surface of 3. In the oxide layer 4, a tunnel oxide film 41 is continuously formed, which is in contact with each operating region 31 and the impurity buried layer 2, and which forms a part of the oxide layer 4 and has a thickness that causes a tunnel effect. . A silicon nitride layer 5 is deposited in rough contact with this tunnel oxide film 41. And this silicon nitride 115
Control gates 61, 62, 63, and 64 are provided on the longitudinally extending portions of the actuators 31 and on the opposite side of each actuating area 31, respectively. Between adjacent control gates 61 and 62 and 63 and 64, oxide FIJ42 constituting a partition wall is provided. Operation head tii! 31, N-type impurity regions 71, 72, and 73 are formed on the upper surface of the conductive region 32. The control gates 61, 62, 63, and 64 are each connected to a wiring pattern and covered with a protective insulating film 43 formed on the surface thereof. Impurity region 71.72.73
are connected to electrodes 91, 92, and 93 through contact holes provided in the protective insulating film 43, silicon nitride m5, and thermal oxide film 44. The non-continuous semiconductor memory device of this embodiment is constructed as described above.

Next, a method for manufacturing the nonvolatile semiconductor memory device of this embodiment will be explained with reference to FIGS. 3 to 9. First, as shown in FIG. 3, a group 5 element (As1P) is applied to a (100) P type silicon substrate 1 (6 to 8 Ωcm).

sb> is diffused to form an N-type impurity buried layer 2 in a predetermined region. Then in N type 1X10'4cm-3~5
x1Q' 4 cm-3 (1) Epitaxial layer 3 is grown to a thickness of 2 to 10 μm. Next, in order to electrically isolate each region, as shown in FIG.
And epitaxial! After making grooves in 13, SiO2 is applied by CVD method.
The oxide layer 4 is formed by performing isolation. Thereafter, as shown in FIG. 5, the surface of the epitaxial layer 3 was oxidized to 0.8
A thermal oxide film (SiOr) 44 of ~1.0 μm is formed.

Then, a resist pattern 48 is formed in the area where the groove 35 is to be formed using commonly used photolithography and etching techniques, and then using this resist pattern 48 as a mask, reactive ion etching, ion milling, reactive ion milling, etc. The thermal oxide film 44 is partially etched by anisotropic etching, and then the epitaxial layer 3 is selectively etched anisotropically, and the etching is continued until the bottom of the etching reaches the impurity buried layer 2. Form 35. This state is shown in the cross section of FIG.

Next, the resist pattern 48 is removed and the inside of the groove 35 is
Thermal oxidation in a dry 11i oven at 00°C to 1050'C,
The inner wall and bottom surface of the trench 35 are oxidized to a depth of 500 to 1000, and then this thermal oxide film is removed. By performing this oxidation and removal, stains caused by reactive ion etching and roughness of the etched surface are removed. Subsequently, the side surfaces of the epitaxial layer 3 where the silicon surface of the groove 35 was exposed and the top surface of the impurity buried layer 2 were oxidized in dry oxygen diluted with argon.
A so-called tunnel oxide film 41 of 20 to 100 layers is formed.

Next, silicon chloride (Si Cλ4) or silane (S I
A silicon nitride film 5 with a thickness of 500 to 1000 A is formed on the entire surface by thermal CVD at about 80° C. using a mixture of nitrogen and hydrogen as a carrier gas and ammonia (NH3) as a source. This state is shown in FIG.

Next, an N0 type polycrystalline silicon layer containing a large amount of arsenic or phosphorus is deposited over the entire surface by the LPCVD method so as to fill the trench 35 in which the tunnel oxide film 41 and the silicon nitride film 5 have been formed.

Next, the upper polycrystalline silicon layer is removed by an etch bag method until the surface of the thermal oxide film 44 formed on the surface by reactive ion etching or the like is partially exposed, thereby forming a wiring pattern. Subsequently, the polycrystalline silicon layer is etched in the same manner as the groove 35 described above.
A groove 36 is formed. At this time, the control gates 61, 62.
63.64 are formed. The state is shown in FIG.

Next, an oxidized layer 42 is deposited in the second trench 36, and a protective insulating film 43 is further deposited. Thereafter, contact holes for electrical connection are formed, and impurities are ion-implanted into predetermined regions from the contact holes to form N+ impurity regions 71, 72, and 73.

Next, a generally used aluminum vapor deposition layer is formed in the contact hole portion, and electrodes 91, 92, and 93 including wiring layers are formed by photolithography and etching. In this way, the non-volatile semiconductor memory +1 of this embodiment shown in FIG.
1 device is manufactured.

Note that the N1 impurity regions 71, 72, and 73 can also be formed when the polycrystalline silicon layer is etched back, as shown in FIG. 7, where the polycrystalline silicon m50 is etched back.

Also, before forming the second groove 36, the silicon nitride film 5 on the surface is oxidized 1]! 44 is removed using the so-called selective oxidation method (LOCO).
8 method) or the like, and a so-called normal MOS transistor (not shown in this embodiment) can also be formed in the epitaxial layer 3 region and P-type isolation (not shown). At this time, P-type isolation may be formed at the concentration of Pwell.

In this embodiment, the device formed as described above is a so-called EEFR.
Used as OM.

An example of the operation of this embodiment is shown in FIG. This figure 8 shows the read operation, in which the control gate j~63 capacitively coupled to the part of the silicon nitride layer 5 to be written is plus (+
) Apply voltage. All other control gates 61.62.6
3.64 and all electrodes 91.92.93 are grounded. As a result, a tunnel current flows through the tunnel oxide film 41 located between the control gate 63 and the active vJ region 31, and electrons are generated in the portion between the tunnel oxide film 41 and the silicon nitride m5, forming an electron trap layer 411. be done. As a result, even if no voltage is applied to the control gate 63, the depletion layer 31a extends to the operating region 31 due to the charge caused by the electrons in the electron trap layer 411, as shown in FIG. This depletion m
The spread of 31a is determined by the electrons in the electron trap layer 411. Further, when electrons are written in a large amount, the expansion of this depletion layer 31a becomes a certain value. So-called M
This is the width of the depletion layer when the inversion layer is formed in the OS diode, and this width xd-max is expressed by the following formula, where N
In this embodiment, d is the concentration of the epitaxial layer 3.

For example, when epitaxial m3 is 1X10'4 cm-3, Xd-maX=2°7 μm, 1x101 S(, m
-3, Xd -max-1.0 μm.

As in this embodiment, when two EEPROMs facing each other are used and an epitaxial layer of lx10'4 cm-3 is used, the distance between the silicon nitride layer portions of the control m+ region 31 is, for example, 4 μm. When an electron trap layer is formed in the two parts and electrons are written into them, the depletion layers extend in both parts, and as they stick together, the impurity buried layer 2 and the impurity region 72 formed in the contact part are cut off, and a current flows. It disappears. FIG. 9 shows a state in which an electron drag layer 411 is formed and electrons are written only in a portion of silicon nitride m5 that is capacitively coupled to one control gate 63, and in this state, the resistance of the operating region 31 is high. However, the current flows.

Next, the case of erasing the EEPROM of this embodiment will be explained. FIG. 10 shows the state when the electron trap layer 411 is erased. That is, only the control gate 63 of the portion to be erased is set to, for example, 0 volts, and the control gates 61, 62, .
64 and all other electrodes 91,92,93 are brought to a high potential. As a result, the electron trap layer 41 is transferred to the operating region 31.
Electrons flow from 1 as a tunnel current and are erased.

The non-volatile semiconductor memory device of this embodiment has two control gates 62 and 63 in one operating region 31, and the operating order and region corresponding to each control gate are controlled by nitriding the tunnel oxide film 41 apart. It has a silicon layer 5. Therefore, if the silicon nitride layer 5 of any of the control gates 62, 63 in one operating region 31 is not filled in (0, 0), one control gate □-Silicon nitride of only the controller 2 When an electron trap layer is formed and written in the layer 5 (1, 0), an electron trap layer is formed and written in the silicon nitride WJ5 part of only one other control gate 63. If (0,1), and two control gates 62.
When an electron trap layer is formed in the silicon nitride layer 5 of 63 and both are written, four states (1, 1) can be stored.

The stored state can be detected by applying a voltage to the capacitively coupled control gate and detecting the change in resistance between the source and drain. For example, when an electron trap layer is formed and written, even if a voltage is applied to the control gate capacitively coupled to the electron trap layer, the resistance change between the source and drain is small. On the other hand, if an electron trap layer is not formed and no writing is performed, the resistance between the source and drain increases significantly when a voltage is applied to the control gate. In this way, it is possible to detect whether or not data has been written in correspondence with each control gate, and it can be used as a storage device.

In the first embodiment, one control region has two control gates. The number of control gates may be one or more depending on the application. For example, as shown in FIG. 11, four control gates 62, 63, 66, . 67 can be provided.

Note that FIG. 11 is a sectional view corresponding to FIG. 2 of the first embodiment, and is a partial cross-sectional view at the center of one operating region of the nonvolatile semiconductor memory device.

(Embodiment 2) FIGS. 12 and 13 show vertical cross-sectional views of main parts of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. The nonvolatile semiconductor memory device of this embodiment has almost the same structure as the nonvolatile semiconductor memory device of the first embodiment, and has an oxide film 45 between silicon nitride W5 and each control gate 61, 62, 63, 64. The only difference is that . Note that the same reference numerals indicating the same parts as in the first embodiment are used in the second embodiment as well. After forming the silicon nitride layer 5, this oxide film 45 is applied to the control gates 61, 62, 63, 64.
s+ on the surface of silicon nitride layer 5 by thermal oxidation before forming
This forms an Of film.

Since this oxide film 45 has a certain insulating property, the electron trap layer formed between the silicon nitride layer 5 and the tunnel oxide film 41 can more reliably hold electrons.
rIJ5 can be made thinner and the amount of writing can be increased.

[Brief explanation of drawings]

1 and 2 show a nonvolatile semiconductor memory device according to a first embodiment of the present invention, FIG.
The figure is a sectional view taken along the line A-A in FIG. 1, and FIGS. 3 to 7 are sectional views showing the main parts of the apparatus for each main process when manufacturing the nonvolatile semiconductor memory wave U of the first embodiment. Fig. 3 is a cross-sectional view when an epitaxial layer is formed, Fig. 4 is a cross-sectional view when an oxide layer is formed, and Fig. 5 is a cross-sectional view when a groove for forming a silicon nitride layer is formed. 6 is a sectional view when a tunnel oxide film and a silicon nitride layer are formed in the trench, FIG. 7 is a sectional view when a second trench for forming a control gate is formed, and FIG. 8 is a sectional view when a second trench is formed for forming a control gate. 10 to 10 show the operating states of the nonvolatile semiconductor memory device of the first embodiment, and FIG.
9 is a sectional view showing the state of the wiring during writing, FIG. 9 is a sectional view showing the state of the wiring during detection, and FIG. 10 is a sectional view showing the state of the wiring during erasing. FIG. 11 shows a main part of a modification of the first embodiment, and is a cross-sectional view of the operating area. 12 and 13 show a nonvolatile semiconductor interlayer II device of the second embodiment, with FIG. 12 being a longitudinal cross-sectional view of a main part, and FIG. 13 being a cross-sectional view taken along the line A--A in FIG. 12. 1... Substrate 2... Impurity buried layer 3...
-Epitaxial layer 31...operating region 11...oxide layer 41...
- Tunnel oxide film 5...Silicon nitride layer 61.62.63.64...Control electrode 71.72.7
3... Impurity area patent applicant Nippondenso Co., Ltd. Agent Patent attorney Hirodo Okawa Patent attorney Akio Maruyama Figure 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 figure

Claims (6)

[Claims] (1) a semiconductor substrate of a first conductivity type; a buried impurity layer of a second conductivity type forming one of a drain region and a source region formed on the surface of the semiconductor substrate; the formed epitaxial layer of the second conductivity type; and the impurity embedding from the surface of the epitaxial layer surrounding the operating region to form an operating region extending from the surface of the epitaxial layer in the vertical direction of the impurity embedding layer. an insulating barrier rib extending in the vertical direction of the layer; silicon nitride extending in the vertical direction apart from a silicon oxide film to an extent sufficient to cause a tunnel effect in the operating region; and silicon nitride provided within the oxide barrier wall; at least one control gate extending in the vertical direction and provided on a side of the silicon nitride layer opposite to the active region; and a second conductive gate formed on a surface of the active region and forming the other of the drain region and the source region. 1. A nonvolatile semiconductor memory device comprising: a type impurity region. (2) The nonvolatile semiconductor memory device according to claim 1, wherein an oxide layer is interposed between the silicon nitride layer and the control gate. (3) The nonvolatile semiconductor memory device according to claim 1 or 2, wherein two control gates having the operating region as a center of symmetry are provided within an insulating partition wall surrounding the operating region. (4) The nonvolatile semiconductor memory device according to claim 1 or 2, wherein four control gates having the operating region as a center of symmetry are provided in an insulating partition wall surrounding the operating region. (5) The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the impurity buried layer constitutes a common region of one of the drain region and the source region. (6) The nonvolatile semiconductor memory device according to claim 1 or 2, wherein the impurity region formed on the surface of the active region has an electrode formed through an insulating film to the extent that a tunnel effect occurs. .