JPH10209270A - Dielectric separation semiconductor substrate and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost of a dielectric separation semiconductor substrate by reducing the peripheral section of the substrate on which no rotating element can be arranged, and to improve the degree of integration of rotating elements on the substrate and, at the same time, to make the substrate usable at a middle of withstand voltage by vertically digging separating grooves which separate semiconductor crystals from each other by dry etching, etc., regardless of the faces of the crystals. SOLUTION: A single-crystal Si wafer 10 carrying an N<+> buried layer 11 on its surface is separated into many single-crystal Si chips 18, by closely adhering a masking material 14 for trench having separating groove forming windows 12 to the upper surface of the wafer 10, and digging separating grooves 16 into the wafer 10 by dry etching. After an oxide film 20 is formed on the internal surfaces of the grooves 16 and surfaces of the chips 18, the grooves 16 are filled up by depositing Si 22 by the low-pressure CVD method. Then, the surface of the poly-Si 22 is polished to a flat surface, and the wafer 10 is stuck to a supporting substrate 26 composed of a single-crystal Si wafer carrying an oxide film 20 on the surface with the polished surface on the downside by turning over the wafer 10. Therefore, each single-crystal semiconductor chip 18 has a bottom face composed of the defective surface resulting from the formation of the separating grooves and top face composed of an active surface on the opposite side of the defective surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a dielectric isolation semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to obtain a semiconductor integrated circuit device having a large separation withstand voltage and a small separation capacity, a dielectric isolation semiconductor substrate is a substrate which is backed by separating a plurality of semiconductor single crystals from a semiconductor wafer by a separation groove. is there. Conventionally, an EPIC method has been known as a dielectric isolation semiconductor substrate.
In this method, a surface of a semiconductor single crystal wafer is oxidized, a window is opened by a photoetching technique, and chemical etching is performed using a thermal oxide film as a mask to form a separation groove.

However, according to this method, as shown in FIG. 3, since the side surface of the isolation groove 16 is a (111) plane or a plane equivalent thereto, it extends obliquely and the exposed surface of the semiconductor single crystal 18 is It is about 1.4 times the thickness. Therefore, in order to raise the breakdown voltage limit, the divided semiconductor single crystal 18
When the thickness is increased, the size also increases proportionately, and extra parts where circuit elements cannot be arranged around the surface exposed portion increase, so that the degree of integration of circuit elements does not increase and the chip area increases, resulting in high cost. Becomes

In this method, since the semiconductor polycrystalline layer 22 is adhered to the side and bottom surfaces of the semiconductor single crystal 18, there is a large difference in thermal expansion coefficient. However, there is a problem that the dielectric isolation substrate is warped or cracked due to thermal strain when forming the substrate.

[0005] Therefore, in the SODIC method shown in FIG.
A ceramic layer or a glass layer 28 is used in place of the semiconductor polycrystalline layer 22. In the DIW method shown in FIG. 4, the semiconductor polycrystalline layer 22 is thinned and is made of the same material as the semiconductor single crystal 18 via an adhesive 30. The support substrate 26 is bonded. However, in any of the above cases, since the separation groove 16 is formed by chemical etching, the separation groove 1 is formed.
6 is obliquely spread and the surface exposed surface of the semiconductor single crystal is inevitably about 1.4 times as thick as its thickness, and the chip area and the cost are still increased.

In the above-described derivative-separated semiconductor substrate, the cut-out semiconductor single crystal 18 has a thickness of 50 μm or more and has a high withstand voltage of about several hundred volts. As a dielectric isolation semiconductor substrate for low withstand voltage, there is a bonded SOI method shown in FIG. In this SOI method, after a support substrate 26 made of a Si single crystal substrate is bonded via an insulating layer 32, a relatively shallow separation groove 16 is dug vertically by using gas etching, and polycrystals are buried by oxidation separation. Polished and flattened.

[0007]

In the DIW method having a high isolation breakdown voltage as described above, in order to increase the breakdown voltage limit, if the thickness of the divided semiconductor single crystal is increased, the isolation trench is formed by chemical etching. Separation grooves are spread obliquely, and extra portions where circuit elements cannot be arranged increase around the surface exposed portion. As a result, the degree of integration of the circuit elements cannot be increased, and the chip area increases and the cost increases.

On the other hand, in the SOI method, since the separation groove is vertically sculpted, the separation groove becomes oblique as in the DIW method, and an extra portion where a circuit element cannot be arranged around the surface exposed portion increases. However, if the isolation groove is too deep because dry etching is used, there is a problem that the surface active portion of the separated semiconductor single crystal is likely to have defects, and the isolation groove cannot be made too deep.
It is not possible to meet the demand for a medium-breakdown voltage dielectric isolation substrate.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems of the conventional dielectric isolation semiconductor substrate, and has reduced the peripheral portion where the circuit element cannot be arranged, reduced the size of the chip, and integrated the circuit element. It is an object of the present invention to provide a dielectrically isolated semiconductor substrate which can be used at a medium withstand voltage of about 50 to 150 V and a method of manufacturing the same, while improving the degree of cost reduction.

[0010]

When the present inventors use chemical etching to carve a separation groove, the separation groove becomes oblique, and an extra portion where a circuit element cannot be arranged around the surface exposed portion increases. Dry etching was used to form the separation groove. However, if the isolation groove is deepened to increase the withstand voltage by dry etching, the problem of surface defects cannot be avoided. Accordingly, intensive studies have been made to solve the surface defects caused by deep dry etching. As a result, the present invention was completed with the idea that the surface defect layer was placed below and the bottom portion of the separation groove which was not affected by dry etching was used as the surface active layer.

According to a first aspect of the present invention, there is provided a dielectric isolation semiconductor substrate provided on a semiconductor single crystal separated by vertical isolation grooves provided on four sides, and on a side surface and a bottom surface of the semiconductor single crystal on the isolation groove side. An oxide film, a semiconductor polycrystal layer filled in the separation groove and the bottom surface, and a support substrate adhered to the semiconductor polycrystal layer, and the semiconductor single crystal is formed when the separation groove is formed. The gist is that the defective surface side is the bottom surface side and the opposite surface is the active surface.

According to a second aspect of the present invention, there is provided a method of manufacturing a dielectrically isolated semiconductor substrate, comprising the steps of: forming a window for forming a separation groove in a mask material for a trench; and bringing the window into close contact with the semiconductor wafer; A step of applying dry etching to dig a separation groove vertically in the semiconductor wafer to separate it into a large number of semiconductor single crystals, and forming an oxide film on the surface of the separated semiconductor single crystal and the side face of the separation groove. ,
Filling the isolation trench with semiconductor polycrystal and stacking a semiconductor polycrystal layer on the semiconductor single crystal; and grinding the stacked semiconductor polycrystal layer flat and bonding a support substrate to the ground surface. And grinding the semiconductor wafer side until the oxide film formed in the separation groove is exposed.

According to the first aspect of the present invention, the isolation trench for separating the semiconductor single crystal is dug vertically by dry etching or the like regardless of the crystal plane. The number of peripheral portions where circuit elements cannot be arranged is reduced, the size of the chip can be reduced, the degree of integration of the circuit elements can be improved, and the cost can be reduced. Also, even if a deep isolation groove is formed by dry etching or the like, the defect surface generated during the formation of the isolation groove is defined as the bottom surface and the opposite surface is defined as the active surface. Separation can be performed, and the dielectric strength of the dielectric isolation semiconductor substrate can be improved from a low voltage to a medium voltage.

According to a second aspect of the present invention, there is provided a method for manufacturing a dielectrically isolated semiconductor substrate, comprising the steps of forming a window for forming an isolation groove in a mask material for a trench, and bringing the semiconductor wafer into close contact with a semiconductor wafer. Positioning of the separation groove for separating into chips can be performed. A step of performing dry etching from above the mask in close contact with the semiconductor wafer to dig a separation groove in the semiconductor wafer vertically to separate the semiconductor wafer into a large number of semiconductor single crystals, and a surface of the separated semiconductor single crystal and a side surface on the separation groove side In the step of forming an oxide film on the substrate, a large number of semiconductor single crystal chips having vertical separation grooves on four sides are separated from the semiconductor wafer.

By filling the isolation trench with a semiconductor polycrystal and stacking a semiconductor polycrystal layer on the semiconductor single crystal, the isolation trench is filled and the semiconductor single crystal is reinforced with a semiconductor polycrystal layer. At this time, it is preferable to use a vertical low-pressure CVD technique having no orientation in order to fill the narrow and deep isolation groove with poly-Si or the like. This is because there is no orientation, so that it is not necessary to stack poly-Si thickly as in normal pressure CVD, and it is sufficient to deposit poly-Si of 10 to 20 μm including a polishing allowance at most. Next, the semiconductor single crystal chip divided by the step of grinding the stacked semiconductor polycrystalline layers flat and attaching a support substrate is attached to the support substrate. By grinding the semiconductor wafer side until the oxide film formed in the separation groove is exposed, a defect surface generated at the time of formation of the separation groove is defined as a bottom surface and the opposite surface is defined as an active surface. A thick semiconductor single crystal can be separated.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. 1 (a), 1 (b), 1 (c) and 2
(D) (e) (f) is sectional drawing of the dielectric isolation semiconductor substrate explaining the process of this invention method. As shown in FIG. 1A, a mask material 14 for a trench having a window 12 for forming a separation groove is adhered onto a Si single crystal wafer 10 having an N + buried layer 11 on the surface thereof, and FIG. As shown in b), the width is 2-3 μm and the depth is 15-25 by dry etching.
μm separating grooves 16 are formed, and a large number of Si single crystal chips 1 are formed.
8, and the mask material 14 was removed.

Next, as shown in FIG. 1 (c), an oxide film 20 is formed on the inner surface of the separation groove 16 and the surface of the Si single crystal chip 18, and poly-Si 22 is stacked by a low pressure CVD method to fill the separation groove and to form the Si film. Poly S on single crystal 18
i22 was stacked 10 to 20 μm.

Subsequently, the surface of the poly-Si 22 stacked as shown in FIG. 2D is polished flat, and the polished surface of the poly-Si 22 is turned down as shown in FIG. And a heat treatment for bonding on a support substrate 26 made of a Si single crystal wafer having an oxide film 20. Finally, as shown in FIG. 2 (f), the Si single crystal 10 was polished from the upper side of the Si single crystal wafer 10 until the oxide film 20 of the separation groove 16 was exposed to complete the product. Mount the circuit element on the completed derivative-separated semiconductor substrate of the present embodiment,
When the withstand voltage was measured, it was improved to 100V.

[0019]

According to the first aspect of the present invention, the isolation trench for separating the semiconductor single crystal is dug vertically by dry etching or the like irrespective of the crystal plane. In addition, the number of peripheral portions where the circuit elements cannot be arranged is reduced, the size of the chip can be reduced, the degree of integration of the circuit elements can be improved, and the cost can be reduced. Also, even if a deep isolation groove is formed by dry etching or the like, the defect surface generated during the formation of the isolation groove is the bottom surface and the opposite surface is the active surface. Separation can be performed, and the dielectric strength of the dielectric isolation semiconductor substrate can be improved from a low voltage to a medium voltage. In the method of manufacturing a dielectrically isolated semiconductor substrate according to claim 2 of the present invention, dry etching is performed on a mask that is in close contact with a semiconductor wafer, and a vertical separation groove is dug into the semiconductor wafer to separate a large number of semiconductor single crystals. A large number of semiconductor single crystal chips having a small number of peripheral portions where elements cannot be arranged are separated. A step of inverting the semiconductor wafer bonded to a support substrate and grinding the semiconductor wafer side until the oxide film is exposed, the defect surface generated at the time of forming the separation groove as the bottom surface and the opposite surface as the surface. It is possible to separate a thicker semiconductor single crystal than the conventional active surface.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the present invention.

FIG. 3 is a cross-sectional view of a dielectric isolation semiconductor manufactured by a conventional EPIC method.

FIG. 4 is a cross-sectional view of a dielectric isolation semiconductor manufactured by a conventional DIW method.

FIG. 5 is a cross-sectional view of a dielectric isolation semiconductor manufactured by a conventional SODIC method.

FIG. 6 is a sectional view of a dielectric isolation semiconductor manufactured by a conventional SOI method.

[Explanation of symbols]

 10 ... Si single crystal wafer 11 ... Buried layer 14 ... Mask material 16 ... Separation groove 18 ... Si single crystal chip 20 ... Oxide film 22 ... Poly Si 26 ... Support substrate 28 ... Boron glass

Claims (2)

[Claims] A semiconductor single crystal separated by vertical separation grooves provided on four sides; an oxide film provided on a side surface and a bottom surface of the semiconductor single crystal on the separation groove side; A semiconductor polycrystal layer filled and a support substrate adhered to the semiconductor polycrystal layer, wherein the semiconductor single crystal has a defect surface generated at the time of forming the separation groove as a bottom surface and a surface opposite thereto. A dielectrically isolated semiconductor substrate characterized by having an active surface. 2. A step of opening a window for forming a separation groove in a mask material for a trench and closely contacting the semiconductor wafer, and performing dry etching on the mask in close contact with the semiconductor wafer to dig a vertical separation groove in the semiconductor wafer. A step of separating into a number of semiconductor single crystals, and a step of forming an oxide film on the surface of the separated semiconductor single crystal and the side surface of the separation groove,
Filling the isolation trench with semiconductor polycrystal and stacking a semiconductor polycrystal layer on the semiconductor single crystal; and grinding the stacked semiconductor polycrystal layer flat and bonding a support substrate to the ground surface. And a step of grinding the semiconductor wafer side until the oxide film formed in the separation groove is exposed.