JPH10199236A - Dram controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency on an external bus by reducing influence of refresh of DRAM (Dynamic Random Access Memory) on an external bus. SOLUTION: A refresh control section 102 refreshes a DRAM 1 in every constant interval. The refresh control section 102 fetches, in the refresh timing, the information to indicate whether the transfer on the PCI bus 6 from a burst detecting section 101 is a burst transfer or not. The refresh control section 102 refreshes, not during the burst transfer, the DRAM 1 but protracts the refresh, during the burst transfer, and updates the refresh protracting counter 103. The refresh control section 102 refreshes DRAM1 after the burst transfer. Thereby, intermission of the PCT bus 6 during data transfer can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM controller, and more particularly, to a DRAM controller for controlling a refresh operation of a DRAM.

[0002]

2. Description of the Related Art As is well known, a DRAM (Dynami) is used.
c Random Access Memory)
It has excellent features such as large capacity and low price, and is used in various fields. However, DRAM has
There is a usage constraint that refreshing must be performed periodically. The refresh interval varies depending on the type of the DRAM, and is defined as “512 refresh / 8 ms”, “1024 refresh / 128 ms” or the like. For example, "512 refresh /
In "8 ms", all addresses must be refreshed within one refresh cycle of 8 ms. That is, the address is changed in 8 milliseconds, and 5
Twelve refresh operations must be performed. For example, in the case of a method of performing refresh once at regular intervals using a timer, "512 refresh / 8 ms" means that refresh is performed approximately every 15 microseconds.

As a method for controlling a refresh operation of a DRAM, for example, a "DRAM control method" described in Japanese Patent Application Laid-Open No. 6-4454 is known. FIG. 9 is a block diagram showing a DRAM control system described in the above-mentioned publication. In FIG. 9, the system is D
RAM 1, refresh controller 2, DMA controller 3
And The DRAM 1 and the DMA control unit 3
The DMA control unit 3 is connected to the internal bus 4 and indicates to the refresh control unit 2 that the DMA operation is being performed. The refresh control unit 2 has a built-in refresh counter, and performs a refresh operation on the DRAM 1 at regular intervals.

[0004] Assuming that the DMA control unit 3 is performing the DMA operation, the DMA control unit 3 notifies the refresh control unit 2 that the DMA operation is in progress via a signal line indicating that the DMA operation is in progress. The refresh control unit 2 does not perform the refresh operation even if it is time to perform the refresh, if the DMA operation is in progress,
The refresh operation is performed when the notification of the DMA operation is stopped. In this manner, by eliminating the refresh operation during the DMA block transfer, the interruption of the DMA block transfer is eliminated, and high-speed transfer can be performed.

[0005]

The above-described conventional refresh control method can eliminate the influence of the refresh operation on the operation of the closed function on the internal bus. However, for the operation of the function connected to the external bus, the disconnection of the transfer on the external bus by the refresh operation cannot be eliminated, and the refresh operation affects the operation on the external bus, and the transfer of the external bus is performed. The efficiency of the system is reduced.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a DRAM controller capable of reducing the influence of a refresh of a DRAM on an external bus and improving data transfer efficiency on the external bus.

[0007]

A first invention is a DRAM controller for controlling a DRAM (Dynamic Random Access Memory) connected via an internal bus. Is connected to an external bus control unit which operates as a target to be accessed to the external bus and has a function as an interface with the external bus. A refresh control unit for refreshing, and a refresh advance counter, and the burst detection unit is provided with a DRA via an external bus control unit.
Detects whether or not burst transfer (to transfer a plurality of data at a time) between M and another device on the external bus is performed and whether or not the burst transfer has been completed, and notifies the refresh control unit. When the periodic refresh timing arrives when the burst transfer is not performed, the refresh controller performs the periodic refresh on the DRAM, and the periodic refresh timing is maintained during the burst transfer. When it arrives,
The periodic refresh of the DRAM is postponed, and the count value of the refresh postponement counter is updated in the forward direction. When the burst transfer is completed, the count value of the refresh postponement counter indicates that the refresh is postponed. If the number of DRAMs corresponds to the count value,
, And the count value of the refresh advance counter is updated in the reverse direction.

According to the first aspect of the present invention, when the periodic refresh timing arrives in a state where the burst transfer is continued on the external bus, the periodic refresh of the DRAM is postponed, and after the end of the burst transfer. Since the DRAM which has been postponed is refreshed, the DRAM can be refreshed a prescribed number of times while reducing the number of times the burst transfer is cut off on the external bus. As a result, it is possible to prevent the data transfer rate on the external bus from being reduced due to the refresh.

In a second aspect based on the first aspect, the refresh control unit suspends the data transfer to the external bus control unit when the end time of the refresh cycle approaches a predetermined time while the burst transfer is continuing. And refresh of the DRAM is not postponed.

According to the second aspect, when the end time of the refresh cycle approaches the predetermined time after the burst transfer is continued, the external bus control unit is instructed to stop the data transfer and the DRAM bus is stopped. Since the refresh is not postponed, it is possible to prevent the data stored in the DRAM from being destroyed by the postponement of the refresh.

A third invention is a DRAM controller for controlling a DRAM connected via an internal bus, wherein the internal bus operates as a target to be accessed with respect to an external bus, and An external bus control unit having a function as an interface with the external bus is further connected, and includes a bus busy detection unit and a refresh control unit that periodically refreshes the DRAM,
The bus busy detector is based on the operation of the external bus controller,
The refresh control unit detects whether the external bus is in a bus busy state (a state in which data is transferred between devices on the external bus except the external bus control unit) and notifies the refresh control unit. When the external bus is in a bus busy state, the DRAM is pre-refreshed before the periodic refresh timing arrives.

According to the third aspect of the present invention, the DRAM is refreshed in advance using the bus busy state of the external bus, that is, a period during which no access to the DRAM is performed. During this time, the number of times that data transfer on the external bus is interrupted for refreshing is reduced. Therefore, it is possible to prevent the data transfer speed on the external bus from being reduced due to the refresh.

According to a fourth aspect of the present invention, in the third aspect, a preceding refresh counter is further provided, and the refresh control unit performs a preceding refresh of the DRAM in response to the external bus being in a bus busy state. When the count value of the preceding refresh counter is updated in the forward direction, and when the periodic refresh timing arrives, the count value of the preceding refresh counter indicates that the preceding refresh is being performed, The count value of the preceding refresh counter is updated in the reverse direction without performing the periodic refresh, and when the periodic refresh timing arrives, the count value of the preceding refresh counter indicates that the preceding refresh has not been performed. The feature is to periodically refresh the DRAM if To.

According to the fourth aspect, when the preceding refresh of the DRAM is performed, the count value of the preceding refresh counter is updated in the forward direction, and when the periodic refresh timing arrives, the count of the preceding refresh counter is counted. When the numerical value indicates that the preceding refresh is being performed, the count value of the preceding refresh counter is updated in the reverse direction without performing the periodic refresh of the DRAM. The number of regular refreshes can be reliably reduced by the number of times, and as a result, the number of times data transfer on the external bus is interrupted by the refresh can be further reduced.

According to a fifth aspect of the present invention, there is provided a DRAM controller for controlling a DRAM connected via an internal bus, wherein the internal bus operates as a target to be accessed with respect to an external bus, and An external bus control unit having a function as an interface with the external bus is further connected. The external bus control unit includes an access detection unit and a refresh control unit that periodically refreshes the DRAM. The refresh control unit detects whether the internal element of the external bus control unit is accessed and notifies the refresh control unit.The refresh control unit notifies the access control unit that the internal element of the external bus control unit is accessed. When received, before the periodic refresh timing arrives, the preceding refresh of the DRAM is performed. That.

According to the fifth aspect, the DRAM is refreshed in advance by utilizing the state in which the internal elements of the external bus control unit are accessed via the external bus, that is, the period in which the access to the DRAM is not performed. Therefore, the number of times data transfer on the external bus is interrupted for refreshing during access from the external bus is reduced. Therefore, it is possible to prevent the data transfer speed on the external bus from being reduced due to the refresh.

In a sixth aspect based on the fifth aspect, the apparatus further comprises a preceding refresh counter, wherein the refresh control section refreshes the DRAM in response to an access to an internal element of the external bus control section. When the count value of the preceding refresh counter is updated in the forward direction, and the periodic refresh timing arrives, if the count value of the preceding refresh counter indicates that the preceding refresh is being performed, the DRAM is updated. , The count value of the preceding refresh counter is updated in the reverse direction without performing the periodic refresh, and when the periodic refresh timing arrives, the count value of the preceding refresh counter indicates that the preceding refresh has not been performed. In this case, it is recommended that the DRAM be periodically refreshed. To.

According to the sixth aspect of the present invention, when the preceding refresh of the DRAM is performed, the count value of the preceding refresh counter is updated in the forward direction. When the numerical value indicates that the preceding refresh is being performed, the count value of the preceding refresh counter is updated in the reverse direction without performing the periodic refresh of the DRAM. The number of regular refreshes can be reliably reduced by the number of times, and as a result, the number of times data transfer on the external bus is interrupted by the refresh can be further reduced.

A seventh aspect of the present invention is a DRAM controller for controlling a DRAM connected via an internal bus, wherein the internal bus acquires a right to use the bus with respect to an external bus and performs data transfer. An external bus control unit, which operates as a bus master and has a function as an interface with the external bus, is further connected, and includes a transfer size detection unit, a refresh control unit for periodically refreshing the DRAM, a preceding refresh counter, When the external bus control unit attempts to transfer data from now on as a bus master, the transfer size detection unit determines the time period necessary for data transfer from the size of the transferred data, and occurs within the time period. The number of times of the refresh timing is calculated and notified to the refresh control unit. When a notification indicating the number of refresh timings is received from the clock detection unit, before the periodic refresh timing arrives, the preceding refresh of the DRAM is performed for the notified number of times, and the count value of the preceding refresh counter is adjusted. Updating in the forward direction by the number of times, and when the periodic refresh timing arrives, if the count value of the preceding refresh counter indicates that the preceding refresh is being performed,
The count value of the preceding refresh counter is updated in the reverse direction without performing the periodic refresh of the DRAM, and when the periodic refresh timing arrives, it is confirmed that the count value of the preceding refresh counter has not been performed. In this case, the DRAM is periodically refreshed.

According to the seventh aspect, when the external bus control unit attempts to transfer data from now on as a bus master, the refresh timing generated within the time period required for data transfer is determined based on the size of the data to be transferred. Since the number of times is obtained and the DRAM is refreshed in advance by the corresponding number, the number of times data transfer on the external bus is interrupted for refreshing during access from the external bus is reduced. Therefore, it is possible to prevent the data transfer speed on the external bus from being reduced due to the refresh.

An eighth invention is a DRAM controller for controlling a DRAM connected via an internal bus. The DRAM controller acquires a right to use the bus with respect to an external bus and transfers data to the internal bus. An external bus control unit, which operates as a bus master and has a function as an interface with the external bus, is further connected, and includes an occupancy period detection unit, a refresh control unit for periodically refreshing the DRAM, a preceding refresh counter, The occupancy period detection unit is configured such that when the external bus control unit attempts to transfer data from now on as a bus master,
The time period during which the external bus can be occupied in one data transfer is detected, the number of refresh timings occurring during the time period is calculated and notified to the refresh control unit, and the refresh control unit detects the occupation period. When the notification indicating the number of refresh timings is received from the unit, before the periodic refresh timing arrives, the preceding refresh of the DRAM is performed for the notified number of times and the count value of the preceding refresh counter is set to the corresponding number of times. If the count value of the preceding refresh counter indicates that the preceding refresh is being performed when the periodic refresh timing arrives, the DRAM is periodically refreshed. The counter value of the preceding refresh counter is updated in the reverse direction When the refresh timing has arrived, when the count value of the previous refresh counter indicates that it is not subjected to the preceding refresh, and performs periodic refresh against DRAM.

According to the eighth aspect, when the external bus control unit attempts to transfer data from now on as a bus master, the time period during which the external bus control unit can occupy the external bus in one data transfer The number of refresh timings that occur within
Since the RAM is refreshed in advance, the number of times data transfer on the external bus is interrupted for refreshing during access from the external bus is reduced. Therefore, it is possible to prevent the data transfer speed on the external bus from being reduced due to the refresh.

In a ninth aspect based on the eighth aspect, a master latency timer is provided in the external bus control unit, and the occupation period detecting unit detects the master latency timer based on a timer value set in the master latency timer. The external bus control unit detects a time period in which the external bus can be occupied in one data transfer.

According to a tenth aspect, there is provided a DRAM controller for controlling a DRAM connected via an internal bus. The internal bus acquires a right to use the bus with respect to an external bus and performs data transfer. An external bus control unit that operates as a bus master and has a function as an interface with an external bus is further connected, and includes a burst size calculation unit, a refresh control unit that periodically refreshes the DRAM, a preceding refresh counter, With
When the external bus controller attempts to transfer data as a bus master, the burst size calculator can occupy the external bus in the time period required for data transfer and the external bus controller in one data transfer. The refresh control unit detects the shortest time period, selects the shorter one of the time periods, calculates the number of refresh timings occurring within the selected time period, and notifies the refresh control unit of the number. When a notification indicating the number of refresh timings is received from the size calculation unit, before the periodic refresh timing arrives, the preceding refresh of the DRAM is performed by the notified number and the count value of the preceding refresh counter is supported. Update in the forward direction by the number of times At this time, if the count value of the preceding refresh counter indicates that the preceding refresh is being performed, the count value of the preceding refresh counter is updated in the reverse direction without performing the periodic refresh of the DRAM. When the periodic refresh timing arrives, if the count value of the preceding refresh counter indicates that the preceding refresh has not been performed, the DRAM is periodically refreshed. .

According to the tenth aspect, when the external bus control unit intends to transfer data from now on as a bus master, the time period required for data transfer and the external bus control unit can control the external bus in one data transfer. Is selected, the shorter of the time periods in which the DRAM can be occupied, the number of refresh timings occurring in the selected time period is determined, and the DRAM is refreshed earlier by the corresponding number of times. Therefore, the number of times data transfer on the external bus is interrupted for refreshing during access from the external bus is reduced. Therefore, it is possible to prevent the data transfer speed on the external bus from being reduced due to the refresh.

An eleventh invention is a DRAM controller for controlling a DRAM connected via an internal bus, wherein the internal bus acquires a right to use the bus with respect to an external bus and performs data transfer. An external bus control unit that operates as a bus master and has a function as an interface with an external bus is further connected thereto. A burst size calculation unit, a refresh control unit that periodically refreshes the DRAM, a refresh advance counter, And a preceding refresh counter, and when the external bus control unit attempts to transfer data from now on as a bus master, the burst size calculation unit performs the time period necessary for data transfer and the external bus control unit in one data transfer. Detects time periods during which the external bus can be occupied, and within these time periods The shorter one is selected, the number of refresh timings occurring within the selected time period is calculated and notified to the refresh controller, and when the data transfer by the external bus controller is completed, the end of the data transfer is refreshed. Notify the control unit, the refresh control unit,
When a notification indicating the number of refresh timings is received from the burst size calculation unit, before the periodic refresh timing arrives, the preceding refresh of the DRAM is performed for the notified number of times. If the count value indicates that the advance of refresh is not performed, the count value of the preceding refresh counter is updated in the forward direction by the corresponding number of times, and the count value of the refresh advance counter is determined to be forward of refresh. If it indicates that the data transfer by the external bus control unit has been completed from the burst size calculation unit, the count value of the refresh advance counter is updated in the reverse direction by the corresponding number of times. Number of times corresponding to the count value of the refresh advance counter Performs refresh of DRAM, when the count value of the refresh postponed counter is updated in the opposite direction, periodic refresh timing external bus controller for the duration of the transfer of the data has arrived, DRAM
Is periodically postponed, and in this case, if the count value of the preceding refresh counter indicates that the preceding refresh has not been performed, the count value of the preceding refresh counter is updated in the forward direction, and the preceding refresh counter is updated. If the count value of the preceding refresh counter indicates that the preceding refresh is being performed, the count value of the preceding refresh counter is updated in the reverse direction. Is reached, if the count value of the preceding refresh counter indicates that the preceding refresh is being performed, the count value of the preceding refresh counter is updated in the reverse direction without performing periodic DRAM refresh. In the state where data transfer by the external bus control unit is not performed, Tsu when the shoe timing has arrived, when the count value of the previous refresh counter indicates that it is not subjected to the preceding refresh, DR
It is characterized in that the AM is periodically refreshed.

According to the eleventh aspect, when the external bus control unit attempts to transfer data from now on as a bus master, the time period required for data transfer and the external bus control unit can control the external bus in one data transfer. Is selected, the shorter of the time periods in which the DRAM can be occupied, the number of refresh timings occurring in the selected time period is determined, and the DRAM is refreshed earlier by the corresponding number of times. Therefore, the number of times data transfer on the external bus is interrupted for refreshing during access from the external bus is reduced. Further, when the periodic refresh timing arrives while the burst transfer is continuing on the external bus, the periodic refresh of the DRAM is postponed.
Since the RAM is refreshed, the DRAM can be refreshed a specified number of times while reducing the number of times burst transfer is cut off on the external bus. As a result, it is possible to prevent the data transfer rate on the external bus from being reduced due to the refresh.

According to a twelfth aspect, in the eleventh aspect,
The refresh control unit instructs the external bus control unit to stop the data transfer when the end time of the refresh cycle approaches a predetermined time while the external bus control unit is continuing the data transfer, and also performs the DRAM The refresh is not postponed.

According to the twelfth aspect, when the end time of the refresh cycle approaches the predetermined time after the external bus control unit is continuing the data transfer, the data transfer to the external bus control unit is stopped. Instruct and DRAM
Is not postponed, it is possible to prevent the data stored in the DRAM from being destroyed by the postponement of the refresh.

According to a thirteenth aspect, in the eleventh aspect,
The advance refresh counter and the refresh advance counter are configured by one advance / advance refresh counter. When the refresh is advanced, the refresh control unit updates the advance / advance refresh counter in the reverse direction and performs the advance refresh. Is characterized in that a forward / previous refresh counter is updated in the forward direction, and whether the refresh is advanced or a preceding refresh is determined based on the sign of the count value of the preceding / previous refresh counter. .

According to the thirteenth aspect, the advanced refresh counter and the advanced refresh counter are constituted by one advanced / preliminary refresh counter, so that a DRAM controller with a simple configuration and low cost can be obtained.

A fourteenth invention is a DRAM controller for controlling a DRAM connected via an internal bus, wherein the internal bus operates as a target to be accessed for an external bus, and An external bus control unit having a function as an interface with an external bus is further connected, and a single transfer instruction unit and a DRAM
A refresh control unit that periodically refreshes the data.The refresh control unit notifies the single transfer instructing unit when the timing of the periodic refresh approaches a predetermined time later, and the single transfer instructing unit performs the refresh operation. In response to the notification from the control unit, the external bus control unit is instructed to transfer data having a short data length.

According to the fourteenth aspect, when the periodic refresh timing approaches, the external bus control unit is caused to perform single data transfer (transfer of short size data). The probability that the refresh can be interrupted without requiring the interruption processing to the external bus is increased. As a result, the number of disconnections of data transfer can be reduced, and the external bus can be used efficiently.

In a fifteenth aspect based on any one of the second to fourteenth aspects, the refresh control unit is configured to, if the count value of the preceding refresh counter is equal to the number of remaining refreshes in the current refresh cycle, Refresh is not performed until the refresh cycle is completed.

According to the fifteenth aspect, when the count value of the preceding refresh counter is equal to the number of remaining refreshes in the current refresh cycle, refresh is not performed until the current refresh cycle ends. , Reduce the number of extra refreshes,
The external bus can be used more efficiently.

In a sixteenth aspect based on any one of the second to fourteenth aspects, the refresh control unit determines that the current value of the preceding refresh counter is equal to the number of remaining refreshes in the current refresh cycle. , The next refresh cycle is started assuming that one refresh cycle is completed.

According to the sixteenth aspect, when the count value of the preceding refresh counter is equal to the number of remaining refreshes in the current refresh cycle, it is determined that the current refresh cycle has ended and the next refresh cycle is started. Therefore, the DRAM can be refreshed at an earlier timing, and the possibility that the data stored in the DRAM is destroyed due to insufficient refresh is further reduced.

According to a seventeenth aspect, in any one of the first to sixteenth aspects, a PCI local bus is used as the external bus.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to FIGS. Here, as an example, a DRAM controller is a PCI (Peripheral Compo) as an example of an external bus.
(Non-Interconnect) A case where the local bus is connected will be described.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. In FIG. 1, the control system includes a PCI control unit 5 and a DRA.
An M controller 100 and a DRAM 1 are provided, each of which is connected to the internal bus 4. Further, the PCI control unit 5 is connected to a PCI bus 6. The DRAM controller 100 includes a burst detection unit 101, a refresh control unit 102, and a refresh advance counter 1
03 is included.

The PCI control unit 5 operates as an interface between the PCI bus 6 and the internal bus 4, and reads and writes data from and to the DRAM 1. In the present embodiment, the PCI control unit 5 operates as a target for the PCI bus 6. The DRAM 1 is a memory composed of rewritable storage elements that require updating of stored information at regular intervals. The burst detector 101
The operation of the CI control unit 5 is constantly monitored, and other devices (not shown, such as a CPU and a hard disk device) connected to the PCI bus 6 via the PCI control unit 102 are
It is detected whether or not burst transfer (data transfer by continuous reading or writing, that is, data transfer in which a plurality of pieces of data are sent together) is performed with the RAM 1. The refresh control unit 102 is a DRAM
1 is refreshed. Refresh control unit 102
Needs to finish refreshing the entire space of the DRAM 1 within a certain time. For example, a method of performing refresh at regular intervals of time is used. The refresh advance counter 103 counts the number of times the refresh control unit 102 did not perform the refresh at the timing when it should be performed.

The operation of the DRAM controller 100 according to the first embodiment configured as described above will be described below. First, the refresh control unit 102 refreshes the DRAM 1 at regular intervals. For example, in the case of a DRAM having a refresh cycle in which 512 refreshes must be performed in 8 milliseconds, about 15
A refresh operation must be performed every microsecond. When the timing to perform the refresh operation has arrived, the refresh control unit 102
The PCI status signal is input from the CPU 01 and a determination is made as to whether or not a burst transfer is being performed between the device connected to the PCI bus 6 via the PCI control unit 5 and the DRAM 1.
The PCI control unit 5 is, for example, an F
By monitoring the RAME # and IRDY # signals,
It is detected whether or not the CI bus 6 is performing burst transfer.

The refresh controller 102 is connected to the DRAM 1 and another device (PCI bus 6) via the PCI controller 5.
If no data transfer is performed between the DRAM 1 and the device (not shown) connected to the DRAM 1, the DRAM 1 is immediately refreshed. Also, the DRAM is controlled via the PCI control unit 5.
If data transfer other than burst transfer (ie, one-time data transfer) is being performed between 1 and another device, or if the last data transfer in burst transfer is being performed, 100 Since the transfer can be expected to be completed in about nanoseconds, the refresh control unit 10
2 refreshes the DRAM 1 after a lapse of several clock cycles (operation clock on the PCI bus 6). On the other hand, when burst transfer is being performed between the DRAM 1 and another device via the PCI control unit 5, the refresh control unit 102 postpones the refresh operation and increments the refresh postponement counter 103 by one. . After that, the refresh control unit 102 refreshes the DRAM 1 by the number of times corresponding to the count value of the refresh advance counter 103 as soon as the completion of the burst transfer is notified by the burst notification signal from the burst detection unit 103. At this time, the refresh control unit 102 decrements the refresh advance counter 103 by the number of executed refreshes.

However, when the end time of the entire refresh cycle is approaching (for example, a predetermined threshold value is set, the refresh control unit 102 sets the time for postponing the refresh to the time corresponding to the threshold value). In other words, other control is performed without incrementing the refresh advance counter 103. That is, in this case, the refresh control unit 102
Sends a transfer interruption signal to the PCI control unit 5 to interrupt the data transfer even during the burst transfer, and refreshes the DRAM 1 after the transfer is completed.

According to the first embodiment, a prescribed number of refreshes can be performed on the DRAM 1 while reducing the number of disconnections of the burst transfer on the PCI bus 6. More specifically, the data transfer on the PCI bus 6 continues for about 7.7 microseconds per burst transfer, if the disconnection does not occur, depending on the setting for the device. on the other hand,
Assuming that the refresh cycle of the DRAM 1 is 15 microseconds, the burst transfer is interrupted about once every two transfers. 2 for disconnecting PCI bus 6 and resuming transfer
It is assumed that it takes 40 nanoseconds (8 clocks at 33.3 MHz operation) and 260 nanoseconds for refresh (when the read / write cycle is 130 nanoseconds). There may be cases where the PCI bus 6 can be used during the refresh or not, but when the PCI bus 6 cannot be used, a loss of 500 nanoseconds per 30 microseconds can be reduced. When the PCI bus 6 can be used, a loss of 240 nanoseconds can be reduced.

As described above, in the first embodiment, the PC
The number of times that the burst transfer on the I bus 6 is cut off can be reduced, and as a result, the data transfer rate on the PCI bus 6 can be prevented from lowering due to refresh.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. In FIG. 2, the control system includes a PCI control unit 5 and a DRA.
An M controller 200 and a DRAM 1 are provided, each of which is connected to the internal bus 4. Further, the PCI control unit 5 is connected to a PCI bus 6. Further, the DRAM controller 200 includes a bus busy detection unit 201, a refresh control unit 202, and a preceding refresh counter 2
03 is included.

The bus busy detecting section 201 is connected to the PCI bus 6
It is determined whether or not the upper part is busy, and the determination result is notified to the refresh control unit 202. Here, “bus busy” refers to a state in which data is being transferred between two devices (not shown) connected to the PCI bus 6. In other words, when the bus is busy, the PCI bus 6
Are not accessed via the DRAM 1. The preceding refresh counter 203 counts the number of executions of the preceding refresh performed before the original refresh timing.

The operation of the DRAM controller 200 according to the second embodiment configured as described above will be described below. The bus busy detection unit 201 includes the PCI control unit 5
When it is detected that the PCI bus 6 is busy on the basis of the PCI status signal from the CPU, a bus busy notification signal is output to notify the refresh control unit 202 that the bus is busy. Note that the PCI control unit 5
For example, it is possible to detect whether or not an access to a device under its control exists and to detect a bus busy by sampling the FRAME # signal on the PCI bus 6. When receiving the notification of the bus busy from the bus busy detection unit 201, the refresh control unit 202 performs the preceding refresh of the DRAM 1 and outputs the count-up / down signal even if the original refresh timing has not arrived, and outputs the count-up / down signal. The refresh counter 203 is incremented by one.

On the other hand, let us consider a case where the original refresh timing has arrived in the refresh control unit 202 and a value other than 0 has been set in the preceding refresh counter 203. In this case, the count value of the preceding refresh counter 203 indicates that the preceding refresh is being performed. At this time, the refresh control unit 202
Decrements the preceding refresh counter 203 by one without performing the refresh operation. However, when the notification of the bus busy is received, the refresh control unit 20
No. 2 performs a preceding refresh. Also, the original refresh timing has arrived in the refresh control unit 202 and 0 has been set in the preceding refresh counter 203, and the DRAM has been set via the PCI bus 6.
When data transfer is being performed between the first device and another device, the refresh control unit 202 sends a transfer interrupt signal to the PC.
The data is sent to the I control unit 5 to instruct interruption of data transfer and refresh the DRAM 1.

As described above, the DRAM of the second embodiment
According to the controller 200, refreshing can be performed using a bus busy state, that is, a period in which access to the DRAM 1 is not performed. In other words, by performing the refresh ahead of the original refresh timing, the number of times the data transfer on the PCI bus 6 is interrupted for the refresh during the access from the PCI bus 6 is reduced. More specifically, PCI
If another device (not shown) exists on the bus 6 and one transfer is performed during a refresh cycle of 15 microseconds, the influence of the refresh on the PCI bus 6 can be completely eliminated. As in the first embodiment described above, a loss of about 500 nanoseconds can be reduced for one transfer interruption. Therefore, the use efficiency of the PCI bus 6 can be improved.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. In FIG. 3, the control system includes a PCI control unit 5 and a DRA
M controller 300 and DRAM 1
Each is connected to the internal bus 4. In addition, PC
The I control unit 5 is connected to the PCI bus 6. Also, DR
The AM controller 300 includes a configuration access detection unit 301, a refresh control unit 302,
And a preceding refresh counter 303.

Configuration access detector 3
01 determines whether or not the access from the PCI bus 6 is a configuration access and notifies the refresh control unit 302 of the access. Here, the configuration access is an access to a control register (located at a different position from the address space of the DRAM 1) in the PCI control unit 5, and does not use the internal bus 4. In other words, the DRAM 1 is not accessed from the PCI bus 6 during the configuration access. By writing various attribute information into this register, setting of a base address on the PCI bus 6, setting of a function to be used, and the like can be performed. The writing to the register is performed by, for example, the PCI bus 6
This is performed by a CPU (not shown) connected to the CPU.

The operation of the DRAM controller 300 according to the third embodiment configured as described above will be described below. The operation is almost the same as that of the second embodiment, and only different points will be described. The refresh control unit 202 according to the second embodiment performs the preceding refresh operation when the bus busy detection unit 201 detects the bus busy, but the refresh control unit 302 according to the third embodiment is configured such that the configuration access detection unit 301 When a configuration access is detected, a preceding refresh operation is performed. That is, when the refresh control unit 302 receives the notification of the configuration access from the configuration access detection unit 301, it performs the preceding refresh of the DRAM 1 even if the original refresh timing has not arrived, and counts up / down signals. Is output, and the preceding refresh counter 303 is incremented by one.

On the other hand, let us consider a case where the original refresh timing has arrived in the refresh control unit 302 and a value other than 0 has been set in the preceding refresh counter 303. In this case, the count value of the preceding refresh counter 303 indicates that the preceding refresh is being performed. At this time, the refresh control unit 302
Decrements the preceding refresh counter 303 by 1 without performing the refresh operation. However, when the notification of the configuration access is received, the refresh control unit 202 performs the preceding refresh.
In the refresh control unit 302, the original refresh timing has arrived, and the preceding refresh counter 303 has been set to 0, and data is transferred between the DRAM 1 and another device via the PCI bus 6. The refresh control unit 302
Sends a transfer interruption signal to the PCI control unit 5, instructs interruption of data transfer, and refreshes the DRAM 1.

As described above, by performing the preceding refresh during the configuration access, the PCI
The effect of refresh on access to the bus 6 can be reduced. In particular, in a system specification in which at least one configuration cycle exists in one refresh cycle, it is possible to completely eliminate the influence of the refresh on the PCI bus 6. More specifically, similar to the first embodiment, a loss of about 500 nanoseconds can be reduced for one elimination of transfer disconnection,
The use efficiency of the external bus can be improved.

(Fourth Embodiment) FIG. 4 shows a fourth embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. In FIG. 4, the control system includes a PCI control unit 5 and a DRA
An M controller 400 and a DRAM 1 are provided, each of which is connected to the internal bus 4. Further, the PCI control unit 5 is connected to a PCI bus 6. Further, the DRAM controller 400 includes a transfer size detection unit 401, a refresh control unit 402, and a preceding refresh counter 4
03 is included.

In the DRAM control system shown in FIG.
The control unit 5 operates as a bus master that acquires the right to use the bus with respect to the PCI bus 6 and performs data transfer. The transfer size detection unit 401 detects the size of the data transferred by the PCI control unit 5 based on the PCI status signal from the PCI control unit 5, outputs a preceding refresh instruction signal, and sends the preceding refresh instruction signal to the refresh control unit 104. Indicate the number of times.

The operation of the DRAM controller 400 according to the fourth embodiment configured as described above will be described below. The basic refresh cycle in the refresh control unit 402 is performed at regular intervals, as in the second embodiment. However, the transfer size detection unit 401
Detects that the PCI control unit 5 performs data transfer as a bus master and performs DRA prior to the data transfer.
The refresh control unit 402 is instructed to refresh M1. At this time, the transfer size detection unit 401 calculates the number of refreshes to be executed by the refresh control unit 402 in advance based on the time corresponding to the size of the data transferred by the PCI control unit 5, and instructs the refresh control unit 402. I do. Refresh control unit 40
2 receives a preceding refresh instruction from the transfer size detection unit 401, performs a refresh operation the number of times instructed by the transfer size detection unit 401 even if the original refresh timing has not arrived, and executes the executed refresh. Refresh counter 40 for the number of times
3 is incremented.

On the other hand, let us consider a case where the original refresh timing has arrived in the refresh control unit 402 and a value other than 0 has been set in the preceding refresh counter 403. In this case, the count value of the preceding refresh counter 403 indicates that the preceding refresh is being performed. At this time, the refresh control unit 402
Decrements the preceding refresh counter 403 by 1 without performing the refresh operation. When the original refresh timing arrives in the refresh control unit 402 and 0 is set in the preceding refresh counter 403, the refresh control unit 402
Performs refresh of the DRAM 1. At this time, the count value of the preceding refresh counter 403 does not change.

As described above, in the fourth embodiment, the PC
Before the I control unit 5 performs a data transfer operation as a bus master, refresh is performed in advance for a number of times corresponding to a time required for data transfer. More specifically, for example, when transferring 1 kilobyte of data, 256 clocks are required on the PCI bus 6. Assuming that the operation clock on the PCI bus 6 is 33.3 MHz, a transfer of one kilobyte of data requires at least about 7.7 microseconds. If the refresh cycle is the same as that of the first embodiment, and the refresh is performed about every 15 microseconds, then normally,
Data transfer is interrupted once every two times. However, in the fourth embodiment, this disconnection can be eliminated by performing refresh before data transfer.

By performing the refresh control as described above, in the fourth embodiment, refresh does not occur during data transfer, and it is not necessary to disconnect data transfer for refresh. As in the first embodiment, it is possible to reduce a loss of about 500 nanoseconds per one elimination of the transfer disconnection, and to improve the transfer speed.

(Fifth Embodiment) FIG. 5 shows a fifth embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. In FIG. 5, the control system includes a PCI control unit 5 and a DRA.
M controller 500 and DRAM 1
Each is connected to the internal bus 4. In addition, PC
The I control unit 5 is connected to the PCI bus 6. Also, DR
The AM controller 500 includes a master latency timer value detection unit 401, a refresh control unit 402, and a preceding refresh counter 403.

In the DRAM control system shown in FIG.
The control unit 5 controls the P as in the DRAM control system of FIG.
It operates as a bus master that acquires the right to use the bus with respect to the CI bus 6 and performs data transfer. The master latency timer value detection unit 501 detects a master latency timer value set in a PCI configuration register (not shown) in the PCI control unit 5, and based on the detected master latency timer value, a refresh control unit 502. To refresh. Here, the master latency timer value defines a period during which the PCI control unit 5 as the bus master is guaranteed to occupy the PCI bus 6 in one data transfer.

The operation of the DRAM controller 500 according to the fifth embodiment configured as described above will be described below. The basic refresh cycle in the refresh control unit 502 is performed at regular intervals, as in the second embodiment. Master latency timer value detector 5
01, similar to the transfer size detection unit 401 of the fourth embodiment, when the PCI control unit 5 detects that the data transfer is performed as a bus master, the DR control is performed prior to the data transfer.
The refresh controller 502 is instructed to refresh the AM1. At this time, based on the master latency timer value, master latency timer value detection section 501 calculates the number of refreshes to be performed in advance and instructs refresh control section 502. Here, the master latency timer value indicates a time during which the use of the bus is guaranteed per data transfer. If a large value is set as the master latency timer value, the PCI control unit 5 can keep using the PCI bus 6 for a long time. As described above, since the time period corresponding to the master latency timer value means that data transfer can be continued, the master latency timer value detection unit 501 calculates the number of refreshes occurring during that time, and Instruct 502. Upon receiving the preceding refresh instruction from the master latency timer value detecting unit 501, the refresh control unit 502 refreshes the number of times specified by the master latency timer value detecting unit 501 even when the original refresh timing has not arrived. The operation is performed, and the preceding refresh counter 503 is incremented by the number of times of the executed refresh.

On the other hand, let us consider a case where the original refresh timing has arrived in the refresh controller 502 and a value other than 0 has been set in the preceding refresh counter 503. In this case, the count value of the preceding refresh counter 503 indicates that the preceding refresh is being performed. At this time, the refresh control unit 502
Decrements the preceding refresh counter 503 by 1 without performing the refresh operation. When the original refresh timing arrives in the refresh control unit 502 and the preceding refresh counter 503 is set to 0, the refresh control unit 502
Performs refresh of the DRAM 1. At this time, the count value of the preceding refresh counter 503 does not change.

As described above, in the fifth embodiment, the PC
Before the I control unit 5 performs the data transfer operation as the bus master, refresh is performed in advance for the number of times corresponding to the time defined by the master latency timer value. More specifically, the set value of the master latency timer value is 0 to 256. This is PCI
This is the number of operation clocks on the bus 6, for example, 33.3 MHz operation, and if the set value of the master latency timer is 256, it is guaranteed that 7.7 microsecond transfer can be performed. If the master latency timer value is 256 and the refresh cycle is the same as in the first embodiment, one transfer interruption occurs every two transfers. In the fifth embodiment, this transfer interruption occurs. Can be eliminated.

As described above, according to the fifth embodiment,
The same effects as in the fourth embodiment can be obtained. At least within the time period of the master latency timer value, refresh does not occur during data transfer, and there is no need to disconnect data transfer for refreshing. As a result, transfer speed can be improved.

(Sixth Embodiment) FIG. 6 shows a sixth embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. In FIG. 6, the control system includes a PCI control unit 5 and a DRA.
An M controller 600 and a DRAM 1 are provided, each of which is connected to the internal bus 4. Further, the PCI control unit 5 is connected to a PCI bus 6. Also, the DRAM controller 600 includes a burst size calculation unit 601;
A refresh control unit 602 and a preceding refresh counter 603 are included.

In the DRAM control system shown in FIG.
The control unit 5 operates as a bus master that acquires the right to use the PCI bus 6 and transfers data, similarly to the DRAM control system of FIGS. 4 and 5. The burst size calculation unit 601 detects a master latency timer value set in a PCI configuration register in the PCI control unit 5 and a size of data transferred by the PCI control unit 5 as a bus master, and performs refresh control based on the detected values. The unit 502 calculates the number of refreshes to be executed, and instructs the refresh control unit 602.

The operation of the DRAM controller 600 according to the sixth embodiment configured as described above will be described below. The basic refresh cycle in the refresh control unit 602 is performed at regular intervals, as in the second embodiment. Also, a burst size calculation unit 601
Is similar to the master latency timer value detection unit 501 in the fifth embodiment, when it detects that the PCI control unit 5 is in a state of performing data transfer as a bus master, it performs refreshing prior to this data transfer. , The refresh control unit 602. However, the burst size calculation unit 601 calculates the number of executions of the refresh based on the master latency timer value and the size of the data to be transferred, and instructs the refresh control unit 602. At this time, when the size of the data to be transferred is large enough that the transfer does not end within the time corresponding to the master latency timer value, the burst size calculation unit 601 calculates the number of refreshes by giving priority to the master latency timer value. I do. Conversely, if the size of the data to be transferred is a small size that ends within the time corresponding to the master latency timer value, the number of refreshes is calculated giving priority to the transfer size. Refresh control unit 6
02 receives a preceding refresh instruction from the master latency timer value detection unit 601 and performs a refresh operation the number of times specified by the master latency timer value detection unit 601 even when the original refresh timing has not arrived. , The preceding refresh counter 603 is incremented by the number of executed refreshes.

On the other hand, consider a case where the original refresh timing has arrived in the refresh controller 602 and a value other than 0 has been set in the preceding refresh counter 603. In this case, the count value of the preceding refresh counter 603 indicates that the preceding refresh is being performed. At this time, the refresh control unit 602
Decrements the preceding refresh counter 603 by 1 without performing the refresh operation. When the original refresh timing arrives in the refresh control unit 602 and 0 is set in the preceding refresh counter 603, the refresh control unit 602
Performs refresh of the DRAM 1. At this time, the count value of the preceding refresh counter 603 does not change.

By performing the refresh control as described above, in the sixth embodiment, the refresh may occur during the transfer at least within the time of the master latency timer value as in the fifth embodiment. Gone
There is no need to disconnect the transfer for refreshing.
Further, since the number of times of preceding refresh is calculated based on both the master latency timer value and the size of data to be transferred, it is possible to perform more appropriate preceding refresh than in the fifth embodiment. Therefore, the transfer speed can be improved.

(Seventh Embodiment) FIG. 7 shows a seventh embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. 7, the system includes a PCI control unit 5, a DRAM controller 700, and a DRAM 1, each of which is connected to the internal bus 4. Further, the PCI control unit 5
Connected to PCI bus 6. The DRAM controller 700 includes a burst size calculation unit 701, a refresh control unit 702, and a preceding refresh counter 703.
And a refresh advance counter 704.

In the DRAM control system shown in FIG.
The control unit 5 operates as a bus master that acquires the right to use the bus and transfers data to the PCI bus 6. The refresh advance counter 704 counts the number of refreshes advanced in the middle of data transfer, similarly to the refresh advance counter 103 of the first embodiment.

The operation of the DRAM controller 700 according to the seventh embodiment configured as described above will be described below. When detecting that the PCI control unit 5 performs data transfer as a bus master, the burst size calculation unit 701, like the burst size calculation unit 601 of the sixth embodiment, performs refreshing prior to the data transfer. , To the refresh control unit 702. At this time, the burst size calculation unit 701 calculates the number of times of execution of the refresh based on the master latency timer value and the size of the data to be transferred, and
Instruct 2 When receiving the instruction of the preceding refresh from the burst size calculation unit 701, the refresh control unit 702 performs the refresh operation for the number of times specified by the burst size calculation unit 701 even when the original refresh timing has not arrived. Advance refresh counter 70 for the number of executed refreshes
3 is incremented.

On the other hand, consider a case where the original refresh timing has arrived in the refresh control unit 702 and a value other than 0 has been set in the preceding refresh counter 703. In this case, the count value of the preceding refresh counter 703 indicates that the preceding refresh is being performed. At this time, the refresh control unit 702
Decrements the preceding refresh counter 703 by 1 without performing the refresh operation. When the original refresh timing has arrived in the refresh control unit 702 and 0 is set in the preceding refresh counter 703, the refresh control unit 702
Performs refresh of the DRAM 1. At this time, the count value of the preceding refresh counter 703 does not change.

By the way, in the control system of FIG.
Even when data transfer on the PCI bus 6 using the I control unit 5 as a bus master does not end within a time corresponding to the master latency timer value, the data transfer may continue without interruption. For example, when another device (not shown) on the PCI bus 6 does not use the PCI bus 6, or when the priority of the PCI control unit 5 is higher than other devices (not shown) on the PCI bus 6 It is. After the start of data transfer on the PCI bus 6 using the PCI control unit 5 as a bus master, the refresh control unit 702 sets the original refresh timing Arrives, the refresh control unit 702 postpones the refresh of the DRAM 1 and increments the post-refresh counter 704 by one, as in the first embodiment. After the data transfer is completed, the refresh control unit 702 refreshes the DRAM 1 for the number of times corresponding to the count value of the refresh advance counter 704.

However, if the entire refresh cycle end time is approaching (for example, a predetermined threshold value is set, and the refresh delay time is longer than the threshold time) If no), another control is performed without delaying the refresh. That is, in this case, the refresh control unit 702
Sends a transfer interruption signal to the PCI control unit 5 to interrupt the data transfer even during the data transfer, and refreshes the DRAM 1 after the transfer is completed.

When the refresh is postponed when the preceding refresh counter 703 is other than 0, the refresh controller 702 determines whether the preceding refresh counter 70
Decrements 3 by 1. Conversely, if the refresh is performed in advance when the refresh advanced counter 704 is other than 0, the refresh advanced counter 70
Decrement 4 by 1.

By performing the refresh control as described above, in the seventh embodiment, it is not necessary to interrupt the data transfer for refresh even in the data transfer exceeding at least the master latency timer value.
It is possible to perform more appropriate preceding refresh than in the sixth embodiment. Therefore, the transfer speed can be improved.

(Eighth Embodiment) FIG. 8 shows an eighth embodiment of the present invention.
Using the DRAM controller according to the embodiment of the present invention
FIG. 2 is a block diagram illustrating a configuration of an M control system. 8, the system includes a PCI control unit 5, a DRAM controller 800, and a DRAM 1, each of which is connected to the internal bus 4. Further, the PCI control unit 5
Connected to PCI bus 6. The DRAM controller 800 includes a single transfer instruction unit 801 and a refresh control unit 802.

In the eighth embodiment, description of the same points as in the first embodiment will be omitted, and only different points will be described. The differences from the first embodiment are that a single transfer instructing unit 801 is provided instead of the burst detecting unit 10 and that the refresh advance counter 103 is deleted. The single transfer instructing unit 801 instructs the PCI control unit 5 to transfer small data or single data.

The operation of the DRAM controller 800 according to the eighth embodiment configured as described above will be described below. The basic operation in the eighth embodiment is the same as that of the first embodiment, but the refresh control unit 80
When the count value of the internal refresh counter (not shown) indicates that the original refresh timing is approaching, the number 2 notifies the single transfer instruction unit 801 of that fact. In response, single transfer instructing section 801 notifies PCI control section 5 that single data (single data or data having a small data size) is to be transferred. Accordingly, when single data exists, the PCI control unit 5 transfers the single data with priority. On the other hand, if there is no single data,
The I control unit 5 performs the transfer as before. In this case, the refresh control unit 802 performs disconnection processing of data transfer at the timing of refresh. When the refresh timing approaches, the PCI controller 5 transfers single data, so that the probability of being able to interrupt the refresh to the DRAM 1 without interrupting the PCI bus 6 is increased. As in the first embodiment,
A time loss of about 500 nanoseconds can be reduced for eliminating one cut.

As described above, by transferring data of a short size in the vicinity of the refresh timing, disconnection of data transfer can be reduced, and the bus can be used efficiently. .

(Other Embodiments) As DRAM controllers of other embodiments, the following (1) to (3)
As shown in 2), a DRAM controller having a configuration in which the first to seventh embodiments are appropriately combined is conceivable. (1) First Embodiment + Second Embodiment (2) Second Embodiment + Third Embodiment (3) First Embodiment + Third Embodiment (4) First Embodiment + Second Embodiment + Third Embodiment (5) First Embodiment + Fourth Embodiment (6) Second Embodiment + Fourth Embodiment (7) Third Embodiment + Third Embodiment Fourth embodiment (8) First embodiment + second embodiment + fourth embodiment (9) Second embodiment + third embodiment + fourth embodiment (10) First embodiment Embodiment + Third Embodiment + Fourth Embodiment (11) First Embodiment + Second Embodiment + Third Embodiment + Fourth Embodiment (12) First Embodiment + Third Embodiment Fifth Embodiment (13) Second Embodiment + Fifth Embodiment (14) Third Embodiment + Fifth Embodiment (15) First Embodiment + Second Embodiment + Fifth Embodiment Embodiment (16) Second Embodiment + Third Embodiment + Fifth Embodiment (17) First Embodiment + Third Embodiment + Fifth Embodiment (18) First Embodiment + 2nd embodiment + 3rd embodiment + 5th embodiment (19) 1st embodiment + 6th embodiment (20) 2nd embodiment + 6th embodiment (21) Third Embodiment + Sixth Embodiment (22) First Embodiment + Second Embodiment + Sixth Embodiment (23) Second Embodiment + Third Embodiment + Sixth Embodiment (24) First Embodiment + Third Embodiment + Sixth Embodiment (25) First Embodiment + Second Embodiment + Third Embodiment + Sixth Embodiment (26) Third Embodiment First Embodiment + Seventh Embodiment (27) Second Embodiment + Seventh Embodiment (28) Third Embodiment + Seventh Embodiment (29) First Embodiment + Second Embodiment + Seventh Embodiment (30) Second Embodiment + Third Embodiment + Seventh Embodiment (31) First Embodiment + Third Embodiment + Third Embodiment Seventh Embodiment (32) First Embodiment + Second Embodiment + Third Embodiment + Seventh Embodiment

In this case, since the burst transfer, the bus busy state, and the configuration access do not occur at the same time, even if the burst detection unit, the bus busy detection unit, and the configuration access detection unit are arbitrarily combined, based on the respective detection results. The refresh of the DRAM 1 can be controlled independently. In the above embodiments (5) to (32), the PCI control unit 5
Operate as a target and a bus master with respect to the PCI bus 6, but since the operation of the target and the operation of the bus master do not occur simultaneously, it is possible to independently control the refresh of the DRAM 1 in each operation. .

In each of the above embodiments (1) to (32), both the refresh advance counter and the advance refresh counter are provided, but the refresh control unit sets the count values of both counters as follows. Update control. (A) When the refresh of the DRAM 1 is advanced When the count value of the preceding refresh counter is 0, the count value of the refresh advanced counter is incremented by one. If the count value of the preceding refresh counter is other than 0, the count value of the preceding refresh counter is decremented by 1 while keeping the count value of the advanced refresh counter. (B) When the preceding refresh of the DRAM 1 is performed When the count value of the refresh advance counter is 0, the count value of the preceding refresh counter is incremented by one. If the count value of the refresh advance counter is other than 0, the count value of the refresh advance counter is decremented by 1 while keeping the count value of the preceding refresh counter.

In each of the embodiments described above, the case where the PCI bus 6 is used as the external bus has been described. However, the same effects as those of the embodiments can be obtained by using another bus as the external bus.

In the seventh embodiment, the refresh advance counter 704 and the advance refresh counter 703 are used. However, these two counters are constituted by one up / down counter. Even if the count value of the counter is decremented by 1 and refreshing is performed in advance, the same effect as in the seventh embodiment can be obtained even if the count value of the up / down counter is incremented by 1. However, the count value of the up / down counter becomes a negative value during the refreshing advance, and a positive value when the refreshing is advanced. Also, the same effect as described above can be obtained by incrementing 1 when the refresh is advanced and decrementing 1 when the refresh is performed in advance.

Further, in the second to seventh embodiments, when the refresh for one cycle is completed as a result of performing the refresh in advance, the refresh is stopped until the next refresh cycle is entered at that time. You may. In this case, the same effects as those of the embodiments can be obtained. Further, in the second to seventh embodiments, when one cycle of refresh is completed as a result of performing the refresh in advance, the preceding refresh counter is reset at that time and the next refresh cycle is started. Is also good. In this case, the same effects as those of the embodiments can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a DRAM control system using a DRAM controller according to an eighth embodiment of the present invention.

FIG. 9 is a block diagram showing a conventional DRAM control system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DRAM 4 ... Internal bus 5 ... PCI control part 6 ... PCI bus 100,200,300,400,500,600,7
00, 800: DRAM controller 101: Burst detector 102, 202, 302, 402, 502, 602, 7
02, 802 refresh controller 103 refresh advance counter 201 bus busy detector 203, 303, 403, 503, 603, 703 preceding refresh counter 301 configuration access detector 401 transfer size detector 501 master latency timer Value detection unit 601, 701: burst size calculation unit 801: single transfer instruction unit

Claims (17)

[Claims] 1. A DRAM connected via an internal bus.
A DRAM controller for controlling a dynamic random access memory, wherein the internal bus operates as a target to be accessed with respect to an external bus, and functions as an interface with the external bus. An external bus control unit having: a burst detection unit; a refresh control unit for periodically refreshing the DRAM; and a refresh advance counter; and the burst detection unit includes the external bus control unit. And detecting whether or not a burst transfer (to transfer a plurality of data at a time) between the DRAM and another device on the external bus via the external bus is completed and whether the burst transfer is completed. The refresh control unit notifies the refresh control unit that the burst transfer is performed. When the periodic refresh timing arrives when the burst transfer is not performed, the periodic refresh is performed on the DRAM. Forwarding the refresh and updating the count value of the refresh advance counter in the forward direction, if the count value of the refresh advance counter indicates that the refresh advance is performed when the burst transfer is completed, A DRAM controller which refreshes the DRAM by the number of times corresponding to the count value and updates the count value of the refresh advance counter in the reverse direction. 2. The refresh control unit instructs the external bus control unit to stop data transfer when a refresh cycle end time approaches a predetermined time after the burst transfer is continued, The DRA
2. The DRAM controller according to claim 1, wherein refresh of M is not postponed. 3. A DRAM controller for controlling a DRAM connected via an internal bus, wherein the internal bus operates as a target to be accessed with respect to an external bus, and is connected to the external bus. An external bus control unit having a function as an interface of the external bus control unit; a bus busy detection unit; and a refresh control unit for periodically refreshing the DRAM, wherein the bus busy detection unit includes the external bus control unit. And the refresh control unit detects whether or not the external bus is in a bus busy state (a state in which data is transferred between devices on the external bus except the external bus control unit). The refresh control unit notifies the refresh control unit periodically when the external bus is in a bus busy state. There before arriving, and performing the preceding refreshing of the DRAM, DRAM controller. 4. The semiconductor device according to claim 1, further comprising a preceding refresh counter, wherein the refresh control unit counts the preceding refresh counter when performing the preceding refresh of the DRAM in response to the external bus being in a bus busy state. When the numerical value is updated in the forward direction, and the periodic refresh timing arrives, if the count value of the preceding refresh counter indicates that the preceding refresh is being performed, the DR
The count value of the preceding refresh counter is updated in the reverse direction without performing the AM periodic refresh, and when the periodic refresh timing arrives, the count value of the preceding refresh counter has not been updated. In the case of indicating, the D
4. The DRAM controller according to claim 3, wherein the RAM is periodically refreshed. 5. A DRAM controller for controlling a DRAM connected via an internal bus, wherein the internal bus operates as a target to be accessed with respect to an external bus, and is connected to the external bus. An external bus control unit having a function as an interface is further connected, comprising: an access detection unit; and a refresh control unit for periodically refreshing the DRAM. The access detection unit is connected to the external bus via the external bus. Detecting whether the internal element of the external bus control unit is being accessed and notifying the refresh control unit that the internal element of the external bus control unit is accessed from the access control unit. Before receiving the notification that the DRAM has been refreshed before the periodic refresh timing arrives. And performing a fresh, DRAM controller. 6. A refresh control unit, further comprising: a preceding refresh counter, wherein the refresh control unit refreshes the DRAM in response to an internal element of the external bus control unit being accessed.
When the count value of the preceding refresh counter is updated in the forward direction, and when the periodic refresh timing arrives, the count value of the preceding refresh counter indicates that the preceding refresh is being performed, DR
The count value of the preceding refresh counter is updated in the reverse direction without performing the AM periodic refresh, and when the periodic refresh timing arrives, the count value of the preceding refresh counter has not been updated. In the case of indicating, the D
6. The DRAM controller according to claim 5, wherein the RAM is periodically refreshed. 7. A DRAM controller for controlling a DRAM connected via an internal bus, wherein said internal bus operates as a bus master for acquiring a right to use the bus with respect to an external bus and performing data transfer. And an external bus control unit having an interface with an external bus, further comprising a transfer size detection unit, a refresh control unit for periodically refreshing the DRAM, and a preceding refresh counter. When the external bus control unit attempts to transfer data from now on as the bus master, the transfer size detection unit obtains a time period required for data transfer from the size of the data to be transferred, and occurs within the time period. Calculating the number of refresh timings and notifying the refresh controller, When receiving a notification indicating the number of refresh timings from the transfer size detection unit, before the periodic refresh timing arrives, the unit performs the preceding refresh of the DRAM by the notified number of times and performs the preceding refresh. If the count value of the counter is updated in the forward direction by the corresponding number of times, and when the periodic refresh timing arrives, the count value of the preceding refresh counter indicates that the preceding refresh is being performed. , The DR
The count value of the preceding refresh counter is updated in the reverse direction without performing the AM periodic refresh, and when the periodic refresh timing arrives, the count value of the preceding refresh counter has not been updated. In the case of indicating, the D
A DRAM controller characterized by periodically refreshing a RAM. 8. A DRAM controller for controlling a DRAM connected via an internal bus, wherein said internal bus operates as a bus master for acquiring a right to use the bus with respect to an external bus and performing data transfer. And an external bus control unit having an interface with an external bus, further comprising an occupation period detection unit, a refresh control unit for periodically refreshing the DRAM, and a preceding refresh counter. The occupancy period detection unit detects a time period in which the external bus control unit can occupy the external bus in one data transfer when the external bus control unit attempts to transfer data from now on as a bus master. Then, the number of refresh timings occurring during the time period is calculated and transmitted to the refresh control unit. When the refresh control unit receives a notification indicating the number of refresh timings from the occupation period detection unit, before the regular refresh timing arrives, the refresh control unit performs the same number of times as the number of times the preceding refresh of the DRAM is notified. At the same time, the count value of the preceding refresh counter is updated in the forward direction by the corresponding number of times, and when the periodic refresh timing comes, it is confirmed that the count value of the preceding refresh counter is being subjected to the preceding refresh. If indicated, the DR
The count value of the preceding refresh counter is updated in the reverse direction without performing the AM periodic refresh, and when the periodic refresh timing arrives, the count value of the preceding refresh counter has not been updated. In the case of indicating, the D
A DRAM controller characterized by periodically refreshing a RAM. 9. A master latency timer is provided in the external bus control unit, and the occupation period detection unit determines whether the external bus control unit has one based on a timer value set in the master latency timer. 9. The DRAM controller according to claim 8, wherein a time period during which the external bus can be occupied in one data transfer is detected. 10. A DRAM connected via an internal bus
The internal bus has a function as an interface with the external bus, operating as a bus master that acquires the right to use the bus with respect to the external bus and performs data transfer. An external bus control unit is further connected, comprising: a burst size calculation unit; a refresh control unit that periodically refreshes the DRAM; and a preceding refresh counter. When data transfer is to be performed as a bus master, a time period necessary for data transfer and a time period during which the external bus control unit can occupy the external bus in one data transfer are detected. Select the shorter of the time periods and refresh timers that occur during the selected time period. The refresh control unit calculates the number of times of the timing and notifies the refresh control unit. The preceding refresh of the DRAM is performed by the notified number of times, and the count value of the preceding refresh counter is updated in the forward direction by the corresponding number of times. If the count value indicates that the preceding refresh is being performed, the DR
The count value of the preceding refresh counter is updated in the reverse direction without performing the AM periodic refresh, and when the periodic refresh timing arrives, the count value of the preceding refresh counter has not been updated. In the case of indicating, the D
A DRAM controller characterized by periodically refreshing a RAM. 11. A DRAM connected via an internal bus
The internal bus has a function as an interface with the external bus, operating as a bus master that acquires the right to use the bus with respect to the external bus and performs data transfer. An external bus control unit is further connected, comprising: a burst size calculation unit; a refresh control unit for periodically refreshing the DRAM; a refresh advance counter; and a preceding refresh counter, wherein the burst size calculation unit includes: When the external bus control unit intends to transfer data from now on as a bus master, a time period required for data transfer and a time period during which the external bus control unit can occupy the external bus in one data transfer are set. Detect and select the shorter of these time periods and select Calculating the number of refresh timings occurring within a period and notifying the refresh control unit; when the data transfer by the external bus control unit is completed, notifying the refresh control unit of the end of the data transfer; The control unit, when receiving a notification indicating the number of refresh timings from the burst size calculation unit, performs the preceding refresh of the DRAM for the number of times notified before the periodic refresh timing arrives. In the above, if the count value of the refresh advance counter indicates that refresh advance is not performed, the count value of the advance refresh counter is updated in the forward direction by a corresponding number of times, and the count value of the refresh advance counter is updated. Is postponed for refresh Indicates that the count value of the refresh advance counter is updated in the reverse direction by the corresponding number of times, and when a notification that the data transfer by the external bus control unit is completed is received from the burst size calculation unit. ,
The DRAM is refreshed by the number of times corresponding to the count value of the refresh advance counter, the count value of the refresh advance counter is updated in the reverse direction, and the external bus control unit periodically updates the data while continuing the data transfer. When the refresh timing arrives, the DRAM
In this case, if the count value of the preceding refresh counter indicates that the preceding refresh has not been performed, the count value of the preceding refresh counter is updated in the forward direction,
If the count value of the preceding refresh counter indicates that the preceding refresh is being performed, the count value of the preceding refresh counter is updated in the reverse direction. If the count value of the preceding refresh counter indicates that the preceding refresh is being performed when a proper refresh timing has arrived, the count value of the preceding refresh counter is skipped without performing the periodic refresh of the DRAM. Is updated in the reverse direction, and when the periodic refresh timing arrives in a state where the data transfer by the external bus control unit is not performed, the count value of the preceding refresh counter indicates that the preceding refresh has not been performed. If you have
A DRAM controller, which periodically refreshes the DRAM. 12. The refresh control unit stops data transfer to the external bus control unit when a refresh cycle end time approaches a predetermined time after the external bus control unit is continuing data transfer. 12. The DRAM controller according to claim 11, wherein the instruction is not issued and the refresh of the DRAM is not postponed. 13. The advance refresh counter and the refresh advance counter comprise one advance / advance refresh counter, and the refresh control unit, when the refresh is advanced, causes the advance / advance refresh counter to reverse. When the refresh is performed and the preceding refresh is performed, the preceding / previous refresh counter is updated in the forward direction. Depending on whether the count value of the preceding / previous refresh counter is positive or negative, whether the refresh is advanced or the preceding refresh is performed. 12. The DRAM controller according to claim 11, wherein it is determined whether the DRAM controller is operating. 14. A DRAM connected via an internal bus
The internal bus further includes an external bus control unit that operates as a target to be accessed with respect to the external bus and has a function as an interface with the external bus. A single transfer instructing unit, and a refresh control unit for periodically refreshing the DRAM. The refresh control unit, when the timing of the periodic refresh approaches a predetermined time later, notifies that effect. Notifying a single transfer instruction unit, wherein the single transfer instruction unit instructs the external bus control unit to transfer data having a short data length in response to the notification from the refresh control unit. , DRAM controller. 15. The refresh control unit, when the count value of the preceding refresh counter is equal to the number of remaining refreshes in the current refresh cycle,
15. The DRAM controller according to claim 2, wherein refresh is not performed until a current refresh cycle ends. 16. The refresh control unit, when the count value of the preceding refresh counter is equal to the number of remaining refreshes in a current refresh cycle,
3. The method according to claim 2, wherein the current refresh cycle is completed and the next refresh cycle is started.
15. The DRAM controller according to any one of claims 14 to 14. 17. The DRAM controller according to claim 1, wherein a PCI local bus is used as said external bus.